29 lines
856 B
Diff
29 lines
856 B
Diff
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From ffddd794d834f39e120603d6764d7f25bf24ddc0 Mon Sep 17 00:00:00 2001
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From: Marc Zyngier <marc.zyngier@arm.com>
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Date: Sat, 26 Apr 2014 13:17:03 +0100
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Subject: [PATCH 28/36] ARM: HYP/non-sec: add a barrier after setting SCR.NS==1
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A CP15 instruction execution can be reordered, requiring an
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isb to be sure it is executed in program order.
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Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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---
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arch/arm/cpu/armv7/nonsec_virt.S | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
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index 6367e09..12de5c2 100644
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--- a/arch/arm/cpu/armv7/nonsec_virt.S
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+++ b/arch/arm/cpu/armv7/nonsec_virt.S
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@@ -46,6 +46,7 @@ _secure_monitor:
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#endif
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mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set)
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+ isb
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#ifdef CONFIG_ARMV7_VIRT
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mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value
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--
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1.9.0
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