Fix libvirt + seccomp combo (bz #855162) Fix scsi hotplug crash (bz #879657) Fix QOM refcount crash (bz #881486)
968 lines
34 KiB
Diff
968 lines
34 KiB
Diff
From 138dfa905538bf918af390ff365a27de49364578 Mon Sep 17 00:00:00 2001
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From: Richard Henderson <rth@twiddle.net>
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Date: Fri, 23 Mar 2012 23:27:39 +0100
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Subject: [PATCH] tcg-sparc: Fix qemu_ld/st to handle 32-bit host.
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At the same time, split out the tlb load logic to a new function.
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Fixes the cases of two data registers and two address registers.
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Fixes the signature of, and adds missing, qemu_ld/st opcodes.
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Signed-off-by: Richard Henderson <rth@twiddle.net>
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Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
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---
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tcg/sparc/tcg-target.c | 777 ++++++++++++++++++++++---------------------------
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1 file changed, 348 insertions(+), 429 deletions(-)
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diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
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index 23c2fda..d89c19b 100644
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--- a/tcg/sparc/tcg-target.c
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+++ b/tcg/sparc/tcg-target.c
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@@ -59,8 +59,6 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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};
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#endif
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-#define ARG_OFFSET 1
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-
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static const int tcg_target_reg_alloc_order[] = {
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TCG_REG_L0,
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TCG_REG_L1,
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@@ -288,6 +286,16 @@ static inline int tcg_target_const_match(tcg_target_long val,
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#define ASI_PRIMARY_LITTLE 0x88
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#endif
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+#define LDUH_LE (LDUHA | INSN_ASI(ASI_PRIMARY_LITTLE))
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+#define LDSH_LE (LDSHA | INSN_ASI(ASI_PRIMARY_LITTLE))
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+#define LDUW_LE (LDUWA | INSN_ASI(ASI_PRIMARY_LITTLE))
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+#define LDSW_LE (LDSWA | INSN_ASI(ASI_PRIMARY_LITTLE))
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+#define LDX_LE (LDXA | INSN_ASI(ASI_PRIMARY_LITTLE))
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+
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+#define STH_LE (STHA | INSN_ASI(ASI_PRIMARY_LITTLE))
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+#define STW_LE (STWA | INSN_ASI(ASI_PRIMARY_LITTLE))
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+#define STX_LE (STXA | INSN_ASI(ASI_PRIMARY_LITTLE))
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+
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static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2,
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int op)
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{
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@@ -360,64 +368,43 @@ static inline void tcg_out_movi(TCGContext *s, TCGType type,
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}
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}
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-static inline void tcg_out_ld_raw(TCGContext *s, int ret,
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- tcg_target_long arg)
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-{
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- tcg_out_sethi(s, ret, arg);
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- tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
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- INSN_IMM13(arg & 0x3ff));
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-}
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-
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-static inline void tcg_out_ld_ptr(TCGContext *s, int ret,
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- tcg_target_long arg)
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+static inline void tcg_out_ldst_rr(TCGContext *s, int data, int a1,
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+ int a2, int op)
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{
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- if (!check_fit_tl(arg, 10))
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- tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ffULL);
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- if (TCG_TARGET_REG_BITS == 64) {
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- tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) |
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- INSN_IMM13(arg & 0x3ff));
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- } else {
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- tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
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- INSN_IMM13(arg & 0x3ff));
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- }
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+ tcg_out32(s, op | INSN_RD(data) | INSN_RS1(a1) | INSN_RS2(a2));
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}
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-static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op)
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+static inline void tcg_out_ldst(TCGContext *s, int ret, int addr,
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+ int offset, int op)
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{
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- if (check_fit_tl(offset, 13))
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+ if (check_fit_tl(offset, 13)) {
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tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |
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INSN_IMM13(offset));
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- else {
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+ } else {
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
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- tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
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- INSN_RS2(addr));
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+ tcg_out_ldst_rr(s, ret, addr, TCG_REG_I5, op);
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}
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}
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-static inline void tcg_out_ldst_asi(TCGContext *s, int ret, int addr,
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- int offset, int op, int asi)
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-{
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- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
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- tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
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- INSN_ASI(asi) | INSN_RS2(addr));
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-}
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-
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static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
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TCGReg arg1, tcg_target_long arg2)
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{
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- if (type == TCG_TYPE_I32)
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- tcg_out_ldst(s, ret, arg1, arg2, LDUW);
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- else
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- tcg_out_ldst(s, ret, arg1, arg2, LDX);
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+ tcg_out_ldst(s, ret, arg1, arg2, (type == TCG_TYPE_I32 ? LDUW : LDX));
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}
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static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
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TCGReg arg1, tcg_target_long arg2)
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{
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- if (type == TCG_TYPE_I32)
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- tcg_out_ldst(s, arg, arg1, arg2, STW);
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- else
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- tcg_out_ldst(s, arg, arg1, arg2, STX);
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+ tcg_out_ldst(s, arg, arg1, arg2, (type == TCG_TYPE_I32 ? STW : STX));
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+}
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+
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+static inline void tcg_out_ld_ptr(TCGContext *s, int ret,
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+ tcg_target_long arg)
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+{
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+ if (!check_fit_tl(arg, 10)) {
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+ tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ff);
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+ }
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+ tcg_out_ld(s, TCG_TYPE_PTR, ret, ret, arg & 0x3ff);
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}
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static inline void tcg_out_sety(TCGContext *s, int rs)
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@@ -442,14 +429,15 @@ static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
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}
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}
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-static inline void tcg_out_andi(TCGContext *s, int reg, tcg_target_long val)
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+static inline void tcg_out_andi(TCGContext *s, int rd, int rs,
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+ tcg_target_long val)
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{
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if (val != 0) {
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if (check_fit_tl(val, 13))
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- tcg_out_arithi(s, reg, reg, val, ARITH_AND);
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+ tcg_out_arithi(s, rd, rs, val, ARITH_AND);
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else {
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tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, val);
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- tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_AND);
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+ tcg_out_arith(s, rd, rs, TCG_REG_I5, ARITH_AND);
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}
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}
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}
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@@ -718,418 +706,328 @@ static const void * const qemu_st_helpers[4] = {
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helper_stl_mmu,
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helper_stq_mmu,
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};
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-#endif
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-#if TARGET_LONG_BITS == 32
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-#define TARGET_LD_OP LDUW
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-#else
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-#define TARGET_LD_OP LDX
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-#endif
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+/* Perform the TLB load and compare.
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-#if defined(CONFIG_SOFTMMU)
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-#if HOST_LONG_BITS == 32
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-#define TARGET_ADDEND_LD_OP LDUW
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+ Inputs:
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+ ADDRLO_IDX contains the index into ARGS of the low part of the
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+ address; the high part of the address is at ADDR_LOW_IDX+1.
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+
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+ MEM_INDEX and S_BITS are the memory context and log2 size of the load.
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+
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+ WHICH is the offset into the CPUTLBEntry structure of the slot to read.
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+ This should be offsetof addr_read or addr_write.
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+
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+ The result of the TLB comparison is in %[ix]cc. The sanitized address
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+ is in the returned register, maybe %o0. The TLB addend is in %o1. */
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+
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+static int tcg_out_tlb_load(TCGContext *s, int addrlo_idx, int mem_index,
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+ int s_bits, const TCGArg *args, int which)
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+{
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+ const int addrlo = args[addrlo_idx];
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+ const int r0 = TCG_REG_O0;
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+ const int r1 = TCG_REG_O1;
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+ const int r2 = TCG_REG_O2;
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+ int addr = addrlo;
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+ int tlb_ofs;
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+
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+ if (TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 64) {
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+ /* Assemble the 64-bit address in R0. */
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+ tcg_out_arithi(s, r0, addrlo, 0, SHIFT_SRL);
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+ tcg_out_arithi(s, r1, args[addrlo_idx + 1], 32, SHIFT_SLLX);
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+ tcg_out_arith(s, r0, r0, r1, ARITH_OR);
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+ }
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+
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+ /* Shift the page number down to tlb-entry. */
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+ tcg_out_arithi(s, r1, addrlo,
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+ TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS, SHIFT_SRL);
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+
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+ /* Mask out the page offset, except for the required alignment. */
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+ tcg_out_andi(s, r0, addr, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
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+
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+ /* Compute tlb index, modulo tlb size. */
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+ tcg_out_andi(s, r1, r1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
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+
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+ /* Relative to the current ENV. */
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+ tcg_out_arith(s, r1, TCG_AREG0, r1, ARITH_ADD);
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+
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+ /* Find a base address that can load both tlb comparator and addend. */
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+ tlb_ofs = offsetof(CPUArchState, tlb_table[mem_index][0]);
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+ if (!check_fit_tl(tlb_ofs + sizeof(CPUTLBEntry), 13)) {
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+ tcg_out_addi(s, r1, tlb_ofs);
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+ tlb_ofs = 0;
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+ }
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+
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+ /* Load the tlb comparator and the addend. */
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+ tcg_out_ld(s, TCG_TYPE_TL, r2, r1, tlb_ofs + which);
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+ tcg_out_ld(s, TCG_TYPE_PTR, r1, r1, tlb_ofs+offsetof(CPUTLBEntry, addend));
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+
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+ /* subcc arg0, arg2, %g0 */
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+ tcg_out_cmp(s, r0, r2, 0);
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+
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+ /* If the guest address must be zero-extended, do so now. */
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+ if (TCG_TARGET_REG_BITS == 64 && TARGET_LONG_BITS == 32) {
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+ tcg_out_arithi(s, r0, addrlo, 0, SHIFT_SRL);
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+ return r0;
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+ }
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+ return addrlo;
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+}
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+#endif /* CONFIG_SOFTMMU */
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+
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+static const int qemu_ld_opc[8] = {
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+#ifdef TARGET_WORDS_BIGENDIAN
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+ LDUB, LDUH, LDUW, LDX, LDSB, LDSH, LDSW, LDX
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#else
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-#define TARGET_ADDEND_LD_OP LDX
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-#endif
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+ LDUB, LDUH_LE, LDUW_LE, LDX_LE, LDSB, LDSH_LE, LDSW_LE, LDX_LE
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#endif
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+};
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-#if TCG_TARGET_REG_BITS == 64
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-#define HOST_LD_OP LDX
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-#define HOST_ST_OP STX
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-#define HOST_SLL_OP SHIFT_SLLX
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-#define HOST_SRA_OP SHIFT_SRAX
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+static const int qemu_st_opc[4] = {
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+#ifdef TARGET_WORDS_BIGENDIAN
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+ STB, STH, STW, STX
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#else
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-#define HOST_LD_OP LDUW
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-#define HOST_ST_OP STW
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-#define HOST_SLL_OP SHIFT_SLL
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-#define HOST_SRA_OP SHIFT_SRA
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+ STB, STH_LE, STW_LE, STX_LE
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#endif
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+};
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-static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
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- int opc)
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+static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int sizeop)
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{
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- int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
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+ int addrlo_idx = 1, datalo, datahi, addr_reg;
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#if defined(CONFIG_SOFTMMU)
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- uint32_t *label1_ptr, *label2_ptr;
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+ int memi_idx, memi, s_bits, n;
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+ uint32_t *label_ptr[2];
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#endif
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- data_reg = *args++;
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- addr_reg = *args++;
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- mem_index = *args;
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- s_bits = opc & 3;
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-
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- arg0 = TCG_REG_O0;
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- arg1 = TCG_REG_O1;
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- arg2 = TCG_REG_O2;
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+ datahi = datalo = args[0];
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+ if (TCG_TARGET_REG_BITS == 32 && sizeop == 3) {
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+ datahi = args[1];
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+ addrlo_idx = 2;
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+ }
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#if defined(CONFIG_SOFTMMU)
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- /* srl addr_reg, x, arg1 */
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- tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
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- SHIFT_SRL);
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- /* and addr_reg, x, arg0 */
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- tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
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- ARITH_AND);
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+ memi_idx = addrlo_idx + 1 + (TARGET_LONG_BITS > TCG_TARGET_REG_BITS);
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+ memi = args[memi_idx];
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+ s_bits = sizeop & 3;
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+
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+ addr_reg = tcg_out_tlb_load(s, addrlo_idx, memi, s_bits, args,
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+ offsetof(CPUTLBEntry, addr_read));
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+
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+ if (TCG_TARGET_REG_BITS == 32 && sizeop == 3) {
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+ int reg64;
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+
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+ /* bne,pn %[xi]cc, label0 */
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+ label_ptr[0] = (uint32_t *)s->code_ptr;
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+ tcg_out32(s, (INSN_OP(0) | INSN_COND(COND_NE, 0) | INSN_OP2(0x1)
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+ | ((TARGET_LONG_BITS == 64) << 21)));
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+
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+ /* TLB Hit. */
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+ /* Load all 64-bits into an O/G register. */
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+ reg64 = (datalo < 16 ? datalo : TCG_REG_O0);
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+ tcg_out_ldst_rr(s, reg64, addr_reg, TCG_REG_O1, qemu_ld_opc[sizeop]);
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+
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+ /* Move the two 32-bit pieces into the destination registers. */
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+ tcg_out_arithi(s, datahi, reg64, 32, SHIFT_SRLX);
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+ if (reg64 != datalo) {
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+ tcg_out_mov(s, TCG_TYPE_I32, datalo, reg64);
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+ }
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- /* and arg1, x, arg1 */
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- tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
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+ /* b,a,pt label1 */
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+ label_ptr[1] = (uint32_t *)s->code_ptr;
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+ tcg_out32(s, (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x1)
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+ | (1 << 29) | (1 << 19)));
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+ } else {
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+ /* The fast path is exactly one insn. Thus we can perform the
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+ entire TLB Hit in the (annulled) delay slot of the branch
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+ over the TLB Miss case. */
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+
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+ /* beq,a,pt %[xi]cc, label0 */
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+ label_ptr[0] = NULL;
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+ label_ptr[1] = (uint32_t *)s->code_ptr;
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+ tcg_out32(s, (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1)
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+ | ((TARGET_LONG_BITS == 64) << 21)
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+ | (1 << 29) | (1 << 19)));
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+ /* delay slot */
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+ tcg_out_ldst_rr(s, datalo, addr_reg, TCG_REG_O1, qemu_ld_opc[sizeop]);
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+ }
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- /* add arg1, x, arg1 */
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- tcg_out_addi(s, arg1, offsetof(CPUArchState,
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- tlb_table[mem_index][0].addr_read));
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+ /* TLB Miss. */
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- /* add env, arg1, arg1 */
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- tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD);
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+ if (label_ptr[0]) {
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+ *label_ptr[0] |= INSN_OFF19((unsigned long)s->code_ptr -
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+ (unsigned long)label_ptr[0]);
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+ }
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+ n = 0;
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+ tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[n++], TCG_AREG0);
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+ if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
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+ tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[n++],
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+ args[addrlo_idx + 1]);
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+ }
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+ tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[n++],
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+ args[addrlo_idx]);
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- /* ld [arg1], arg2 */
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- tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) |
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- INSN_RS2(TCG_REG_G0));
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+ /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
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+ global registers */
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+ tcg_out_st(s, TCG_TYPE_REG, TCG_AREG0, TCG_REG_CALL_STACK,
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+ TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
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+ sizeof(long));
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- /* subcc arg0, arg2, %g0 */
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- tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC);
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-
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- /* will become:
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- be label1
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- or
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- be,pt %xcc label1 */
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- label1_ptr = (uint32_t *)s->code_ptr;
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- tcg_out32(s, 0);
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-
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- /* mov (delay slot) */
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- tcg_out_mov(s, TCG_TYPE_PTR, arg0, addr_reg);
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-
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- /* mov */
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- tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index);
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- /* XXX/FIXME: suboptimal */
|
|
- tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3],
|
|
- tcg_target_call_iarg_regs[2]);
|
|
- tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2],
|
|
- tcg_target_call_iarg_regs[1]);
|
|
- tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1],
|
|
- tcg_target_call_iarg_regs[0]);
|
|
- tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
|
|
- TCG_AREG0);
|
|
-
|
|
- /* XXX: move that code at the end of the TB */
|
|
/* qemu_ld_helper[s_bits](arg0, arg1) */
|
|
tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_ld_helpers[s_bits]
|
|
- (tcg_target_ulong)s->code_ptr) >> 2)
|
|
& 0x3fffffff));
|
|
- /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
|
|
- global registers */
|
|
- // delay slot
|
|
- tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
|
|
- TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
|
|
- sizeof(long), HOST_ST_OP);
|
|
- tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
|
|
- TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
|
|
- sizeof(long), HOST_LD_OP);
|
|
-
|
|
- /* data_reg = sign_extend(arg0) */
|
|
- switch(opc) {
|
|
+ /* delay slot */
|
|
+ tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[n], memi);
|
|
+
|
|
+ /* Reload AREG0. */
|
|
+ tcg_out_ld(s, TCG_TYPE_REG, TCG_AREG0, TCG_REG_CALL_STACK,
|
|
+ TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
|
|
+ sizeof(long));
|
|
+
|
|
+ n = tcg_target_call_oarg_regs[0];
|
|
+ /* datalo = sign_extend(arg0) */
|
|
+ switch (sizeop) {
|
|
case 0 | 4:
|
|
- /* sll arg0, 24/56, data_reg */
|
|
- tcg_out_arithi(s, data_reg, arg0, (int)sizeof(tcg_target_long) * 8 - 8,
|
|
- HOST_SLL_OP);
|
|
- /* sra data_reg, 24/56, data_reg */
|
|
- tcg_out_arithi(s, data_reg, data_reg,
|
|
- (int)sizeof(tcg_target_long) * 8 - 8, HOST_SRA_OP);
|
|
+ /* Recall that SRA sign extends from bit 31 through bit 63. */
|
|
+ tcg_out_arithi(s, datalo, n, 24, SHIFT_SLL);
|
|
+ tcg_out_arithi(s, datalo, datalo, 24, SHIFT_SRA);
|
|
break;
|
|
case 1 | 4:
|
|
- /* sll arg0, 16/48, data_reg */
|
|
- tcg_out_arithi(s, data_reg, arg0,
|
|
- (int)sizeof(tcg_target_long) * 8 - 16, HOST_SLL_OP);
|
|
- /* sra data_reg, 16/48, data_reg */
|
|
- tcg_out_arithi(s, data_reg, data_reg,
|
|
- (int)sizeof(tcg_target_long) * 8 - 16, HOST_SRA_OP);
|
|
+ tcg_out_arithi(s, datalo, n, 16, SHIFT_SLL);
|
|
+ tcg_out_arithi(s, datalo, datalo, 16, SHIFT_SRA);
|
|
break;
|
|
case 2 | 4:
|
|
- /* sll arg0, 32, data_reg */
|
|
- tcg_out_arithi(s, data_reg, arg0, 32, HOST_SLL_OP);
|
|
- /* sra data_reg, 32, data_reg */
|
|
- tcg_out_arithi(s, data_reg, data_reg, 32, HOST_SRA_OP);
|
|
+ tcg_out_arithi(s, datalo, n, 0, SHIFT_SRA);
|
|
break;
|
|
+ case 3:
|
|
+ if (TCG_TARGET_REG_BITS == 32) {
|
|
+ tcg_out_mov(s, TCG_TYPE_REG, datahi, n);
|
|
+ tcg_out_mov(s, TCG_TYPE_REG, datalo, n + 1);
|
|
+ break;
|
|
+ }
|
|
+ /* FALLTHRU */
|
|
case 0:
|
|
case 1:
|
|
case 2:
|
|
- case 3:
|
|
default:
|
|
/* mov */
|
|
- tcg_out_mov(s, TCG_TYPE_REG, data_reg, arg0);
|
|
+ tcg_out_mov(s, TCG_TYPE_REG, datalo, n);
|
|
break;
|
|
}
|
|
|
|
- /* will become:
|
|
- ba label2 */
|
|
- label2_ptr = (uint32_t *)s->code_ptr;
|
|
- tcg_out32(s, 0);
|
|
-
|
|
- /* nop (delay slot */
|
|
- tcg_out_nop(s);
|
|
-
|
|
- /* label1: */
|
|
-#if TARGET_LONG_BITS == 32
|
|
- /* be label1 */
|
|
- *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) |
|
|
- INSN_OFF22((unsigned long)s->code_ptr -
|
|
- (unsigned long)label1_ptr));
|
|
-#else
|
|
- /* be,pt %xcc label1 */
|
|
- *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1) |
|
|
- (0x5 << 19) | INSN_OFF19((unsigned long)s->code_ptr -
|
|
- (unsigned long)label1_ptr));
|
|
-#endif
|
|
-
|
|
- /* ld [arg1 + x], arg1 */
|
|
- tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) -
|
|
- offsetof(CPUTLBEntry, addr_read), TARGET_ADDEND_LD_OP);
|
|
-
|
|
-#if TARGET_LONG_BITS == 32
|
|
- /* and addr_reg, x, arg0 */
|
|
- tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
|
|
- tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND);
|
|
- /* add arg0, arg1, arg0 */
|
|
- tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD);
|
|
+ *label_ptr[1] |= INSN_OFF19((unsigned long)s->code_ptr -
|
|
+ (unsigned long)label_ptr[1]);
|
|
#else
|
|
- /* add addr_reg, arg1, arg0 */
|
|
- tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD);
|
|
-#endif
|
|
+ addr_reg = args[addrlo_idx];
|
|
+ if (TCG_TARGET_REG_BITS == 64 && TARGET_LONG_BITS == 32) {
|
|
+ tcg_out_arithi(s, TCG_REG_I5, addr_reg, 0, SHIFT_SRL);
|
|
+ addr_reg = TCG_REG_I5;
|
|
+ }
|
|
+ if (TCG_TARGET_REG_BITS == 32 && sizeop == 3) {
|
|
+ int reg64 = (datalo < 16 ? datalo : TCG_REG_O0);
|
|
|
|
-#else
|
|
- arg0 = addr_reg;
|
|
-#endif
|
|
+ tcg_out_ldst_rr(s, reg64, addr_reg, TCG_REG_G0, qemu_ld_opc[sizeop]);
|
|
|
|
- switch(opc) {
|
|
- case 0:
|
|
- /* ldub [arg0], data_reg */
|
|
- tcg_out_ldst(s, data_reg, arg0, 0, LDUB);
|
|
- break;
|
|
- case 0 | 4:
|
|
- /* ldsb [arg0], data_reg */
|
|
- tcg_out_ldst(s, data_reg, arg0, 0, LDSB);
|
|
- break;
|
|
- case 1:
|
|
-#ifdef TARGET_WORDS_BIGENDIAN
|
|
- /* lduh [arg0], data_reg */
|
|
- tcg_out_ldst(s, data_reg, arg0, 0, LDUH);
|
|
-#else
|
|
- /* lduha [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
|
- tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUHA, ASI_PRIMARY_LITTLE);
|
|
-#endif
|
|
- break;
|
|
- case 1 | 4:
|
|
-#ifdef TARGET_WORDS_BIGENDIAN
|
|
- /* ldsh [arg0], data_reg */
|
|
- tcg_out_ldst(s, data_reg, arg0, 0, LDSH);
|
|
-#else
|
|
- /* ldsha [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
|
- tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSHA, ASI_PRIMARY_LITTLE);
|
|
-#endif
|
|
- break;
|
|
- case 2:
|
|
-#ifdef TARGET_WORDS_BIGENDIAN
|
|
- /* lduw [arg0], data_reg */
|
|
- tcg_out_ldst(s, data_reg, arg0, 0, LDUW);
|
|
-#else
|
|
- /* lduwa [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
|
- tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUWA, ASI_PRIMARY_LITTLE);
|
|
-#endif
|
|
- break;
|
|
- case 2 | 4:
|
|
-#ifdef TARGET_WORDS_BIGENDIAN
|
|
- /* ldsw [arg0], data_reg */
|
|
- tcg_out_ldst(s, data_reg, arg0, 0, LDSW);
|
|
-#else
|
|
- /* ldswa [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
|
- tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSWA, ASI_PRIMARY_LITTLE);
|
|
-#endif
|
|
- break;
|
|
- case 3:
|
|
-#ifdef TARGET_WORDS_BIGENDIAN
|
|
- /* ldx [arg0], data_reg */
|
|
- tcg_out_ldst(s, data_reg, arg0, 0, LDX);
|
|
-#else
|
|
- /* ldxa [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
|
- tcg_out_ldst_asi(s, data_reg, arg0, 0, LDXA, ASI_PRIMARY_LITTLE);
|
|
-#endif
|
|
- break;
|
|
- default:
|
|
- tcg_abort();
|
|
+ tcg_out_arithi(s, datahi, reg64, 32, SHIFT_SRLX);
|
|
+ if (reg64 != datalo) {
|
|
+ tcg_out_mov(s, TCG_TYPE_I32, datalo, reg64);
|
|
+ }
|
|
+ } else {
|
|
+ tcg_out_ldst_rr(s, datalo, addr_reg, TCG_REG_G0, qemu_ld_opc[sizeop]);
|
|
}
|
|
-
|
|
-#if defined(CONFIG_SOFTMMU)
|
|
- /* label2: */
|
|
- *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
|
|
- INSN_OFF22((unsigned long)s->code_ptr -
|
|
- (unsigned long)label2_ptr));
|
|
-#endif
|
|
+#endif /* CONFIG_SOFTMMU */
|
|
}
|
|
|
|
-static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
|
|
- int opc)
|
|
+static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int sizeop)
|
|
{
|
|
- int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
|
|
+ int addrlo_idx = 1, datalo, datahi, addr_reg;
|
|
#if defined(CONFIG_SOFTMMU)
|
|
- uint32_t *label1_ptr, *label2_ptr;
|
|
+ int memi_idx, memi, n;
|
|
+ uint32_t *label_ptr;
|
|
#endif
|
|
|
|
- data_reg = *args++;
|
|
- addr_reg = *args++;
|
|
- mem_index = *args;
|
|
-
|
|
- s_bits = opc;
|
|
-
|
|
- arg0 = TCG_REG_O0;
|
|
- arg1 = TCG_REG_O1;
|
|
- arg2 = TCG_REG_O2;
|
|
+ datahi = datalo = args[0];
|
|
+ if (TCG_TARGET_REG_BITS == 32 && sizeop == 3) {
|
|
+ datahi = args[1];
|
|
+ addrlo_idx = 2;
|
|
+ }
|
|
|
|
#if defined(CONFIG_SOFTMMU)
|
|
- /* srl addr_reg, x, arg1 */
|
|
- tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
|
|
- SHIFT_SRL);
|
|
-
|
|
- /* and addr_reg, x, arg0 */
|
|
- tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
|
|
- ARITH_AND);
|
|
-
|
|
- /* and arg1, x, arg1 */
|
|
- tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
|
-
|
|
- /* add arg1, x, arg1 */
|
|
- tcg_out_addi(s, arg1, offsetof(CPUArchState,
|
|
- tlb_table[mem_index][0].addr_write));
|
|
+ memi_idx = addrlo_idx + 1 + (TARGET_LONG_BITS > TCG_TARGET_REG_BITS);
|
|
+ memi = args[memi_idx];
|
|
+
|
|
+ addr_reg = tcg_out_tlb_load(s, addrlo_idx, memi, sizeop, args,
|
|
+ offsetof(CPUTLBEntry, addr_write));
|
|
+
|
|
+ if (TCG_TARGET_REG_BITS == 32 && sizeop == 3) {
|
|
+ /* Reconstruct the full 64-bit value in %g1, using %o2 as temp. */
|
|
+ /* ??? Redefine the temps from %i4/%i5 so that we have a o/g temp. */
|
|
+ tcg_out_arithi(s, TCG_REG_G1, datalo, 0, SHIFT_SRL);
|
|
+ tcg_out_arithi(s, TCG_REG_O2, datahi, 32, SHIFT_SLLX);
|
|
+ tcg_out_arith(s, TCG_REG_G1, TCG_REG_G1, TCG_REG_O2, ARITH_OR);
|
|
+ datalo = TCG_REG_G1;
|
|
+ }
|
|
|
|
- /* add env, arg1, arg1 */
|
|
- tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD);
|
|
+ /* The fast path is exactly one insn. Thus we can perform the entire
|
|
+ TLB Hit in the (annulled) delay slot of the branch over TLB Miss. */
|
|
+ /* beq,a,pt %[xi]cc, label0 */
|
|
+ label_ptr = (uint32_t *)s->code_ptr;
|
|
+ tcg_out32(s, (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1)
|
|
+ | ((TARGET_LONG_BITS == 64) << 21)
|
|
+ | (1 << 29) | (1 << 19)));
|
|
+ /* delay slot */
|
|
+ tcg_out_ldst_rr(s, datalo, addr_reg, TCG_REG_O1, qemu_st_opc[sizeop]);
|
|
+
|
|
+ /* TLB Miss. */
|
|
+
|
|
+ n = 0;
|
|
+ tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[n++], TCG_AREG0);
|
|
+ if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
|
|
+ tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[n++],
|
|
+ args[addrlo_idx + 1]);
|
|
+ }
|
|
+ tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[n++],
|
|
+ args[addrlo_idx]);
|
|
+ if (TCG_TARGET_REG_BITS == 32 && sizeop == 3) {
|
|
+ tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[n++], datahi);
|
|
+ }
|
|
+ tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[n++], datalo);
|
|
|
|
- /* ld [arg1], arg2 */
|
|
- tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) |
|
|
- INSN_RS2(TCG_REG_G0));
|
|
+ /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
|
|
+ global registers */
|
|
+ tcg_out_st(s, TCG_TYPE_REG, TCG_AREG0, TCG_REG_CALL_STACK,
|
|
+ TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
|
|
+ sizeof(long));
|
|
|
|
- /* subcc arg0, arg2, %g0 */
|
|
- tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC);
|
|
-
|
|
- /* will become:
|
|
- be label1
|
|
- or
|
|
- be,pt %xcc label1 */
|
|
- label1_ptr = (uint32_t *)s->code_ptr;
|
|
- tcg_out32(s, 0);
|
|
-
|
|
- /* mov (delay slot) */
|
|
- tcg_out_mov(s, TCG_TYPE_PTR, arg0, addr_reg);
|
|
-
|
|
- /* mov */
|
|
- tcg_out_mov(s, TCG_TYPE_REG, arg1, data_reg);
|
|
-
|
|
- /* mov */
|
|
- tcg_out_movi(s, TCG_TYPE_I32, arg2, mem_index);
|
|
-
|
|
- /* XXX/FIXME: suboptimal */
|
|
- tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3],
|
|
- tcg_target_call_iarg_regs[2]);
|
|
- tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2],
|
|
- tcg_target_call_iarg_regs[1]);
|
|
- tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1],
|
|
- tcg_target_call_iarg_regs[0]);
|
|
- tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
|
|
- TCG_AREG0);
|
|
- /* XXX: move that code at the end of the TB */
|
|
/* qemu_st_helper[s_bits](arg0, arg1, arg2) */
|
|
- tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[s_bits]
|
|
+ tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[sizeop]
|
|
- (tcg_target_ulong)s->code_ptr) >> 2)
|
|
& 0x3fffffff));
|
|
- /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
|
|
- global registers */
|
|
- // delay slot
|
|
- tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
|
|
- TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
|
|
- sizeof(long), HOST_ST_OP);
|
|
- tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
|
|
- TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
|
|
- sizeof(long), HOST_LD_OP);
|
|
-
|
|
- /* will become:
|
|
- ba label2 */
|
|
- label2_ptr = (uint32_t *)s->code_ptr;
|
|
- tcg_out32(s, 0);
|
|
-
|
|
- /* nop (delay slot) */
|
|
- tcg_out_nop(s);
|
|
+ /* delay slot */
|
|
+ tcg_out_movi(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[n], memi);
|
|
|
|
-#if TARGET_LONG_BITS == 32
|
|
- /* be label1 */
|
|
- *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) |
|
|
- INSN_OFF22((unsigned long)s->code_ptr -
|
|
- (unsigned long)label1_ptr));
|
|
-#else
|
|
- /* be,pt %xcc label1 */
|
|
- *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1) |
|
|
- (0x5 << 19) | INSN_OFF19((unsigned long)s->code_ptr -
|
|
- (unsigned long)label1_ptr));
|
|
-#endif
|
|
-
|
|
- /* ld [arg1 + x], arg1 */
|
|
- tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) -
|
|
- offsetof(CPUTLBEntry, addr_write), TARGET_ADDEND_LD_OP);
|
|
+ /* Reload AREG0. */
|
|
+ tcg_out_ld(s, TCG_TYPE_REG, TCG_AREG0, TCG_REG_CALL_STACK,
|
|
+ TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
|
|
+ sizeof(long));
|
|
|
|
-#if TARGET_LONG_BITS == 32
|
|
- /* and addr_reg, x, arg0 */
|
|
- tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
|
|
- tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND);
|
|
- /* add arg0, arg1, arg0 */
|
|
- tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD);
|
|
+ *label_ptr |= INSN_OFF19((unsigned long)s->code_ptr -
|
|
+ (unsigned long)label_ptr);
|
|
#else
|
|
- /* add addr_reg, arg1, arg0 */
|
|
- tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD);
|
|
-#endif
|
|
-
|
|
-#else
|
|
- arg0 = addr_reg;
|
|
-#endif
|
|
-
|
|
- switch(opc) {
|
|
- case 0:
|
|
- /* stb data_reg, [arg0] */
|
|
- tcg_out_ldst(s, data_reg, arg0, 0, STB);
|
|
- break;
|
|
- case 1:
|
|
-#ifdef TARGET_WORDS_BIGENDIAN
|
|
- /* sth data_reg, [arg0] */
|
|
- tcg_out_ldst(s, data_reg, arg0, 0, STH);
|
|
-#else
|
|
- /* stha data_reg, [arg0] ASI_PRIMARY_LITTLE */
|
|
- tcg_out_ldst_asi(s, data_reg, arg0, 0, STHA, ASI_PRIMARY_LITTLE);
|
|
-#endif
|
|
- break;
|
|
- case 2:
|
|
-#ifdef TARGET_WORDS_BIGENDIAN
|
|
- /* stw data_reg, [arg0] */
|
|
- tcg_out_ldst(s, data_reg, arg0, 0, STW);
|
|
-#else
|
|
- /* stwa data_reg, [arg0] ASI_PRIMARY_LITTLE */
|
|
- tcg_out_ldst_asi(s, data_reg, arg0, 0, STWA, ASI_PRIMARY_LITTLE);
|
|
-#endif
|
|
- break;
|
|
- case 3:
|
|
-#ifdef TARGET_WORDS_BIGENDIAN
|
|
- /* stx data_reg, [arg0] */
|
|
- tcg_out_ldst(s, data_reg, arg0, 0, STX);
|
|
-#else
|
|
- /* stxa data_reg, [arg0] ASI_PRIMARY_LITTLE */
|
|
- tcg_out_ldst_asi(s, data_reg, arg0, 0, STXA, ASI_PRIMARY_LITTLE);
|
|
-#endif
|
|
- break;
|
|
- default:
|
|
- tcg_abort();
|
|
+ addr_reg = args[addrlo_idx];
|
|
+ if (TCG_TARGET_REG_BITS == 64 && TARGET_LONG_BITS == 32) {
|
|
+ tcg_out_arithi(s, TCG_REG_I5, addr_reg, 0, SHIFT_SRL);
|
|
+ addr_reg = TCG_REG_I5;
|
|
}
|
|
-
|
|
-#if defined(CONFIG_SOFTMMU)
|
|
- /* label2: */
|
|
- *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
|
|
- INSN_OFF22((unsigned long)s->code_ptr -
|
|
- (unsigned long)label2_ptr));
|
|
-#endif
|
|
+ if (TCG_TARGET_REG_BITS == 32 && sizeop == 3) {
|
|
+ /* Reconstruct the full 64-bit value in %g1, using %o2 as temp. */
|
|
+ /* ??? Redefine the temps from %i4/%i5 so that we have a o/g temp. */
|
|
+ tcg_out_arithi(s, TCG_REG_G1, datalo, 0, SHIFT_SRL);
|
|
+ tcg_out_arithi(s, TCG_REG_O2, datahi, 32, SHIFT_SLLX);
|
|
+ tcg_out_arith(s, TCG_REG_G1, TCG_REG_G1, TCG_REG_O2, ARITH_OR);
|
|
+ datalo = TCG_REG_G1;
|
|
+ }
|
|
+ tcg_out_ldst_rr(s, datalo, addr_reg, TCG_REG_G0, qemu_st_opc[sizeop]);
|
|
+#endif /* CONFIG_SOFTMMU */
|
|
}
|
|
|
|
static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
|
|
@@ -1175,12 +1073,12 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
|
|
/* Store AREG0 in stack to avoid ugly glibc bugs that mangle
|
|
global registers */
|
|
// delay slot
|
|
- tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
|
|
- TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
|
|
- sizeof(long), HOST_ST_OP);
|
|
- tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
|
|
- TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
|
|
- sizeof(long), HOST_LD_OP);
|
|
+ tcg_out_st(s, TCG_TYPE_REG, TCG_AREG0, TCG_REG_CALL_STACK,
|
|
+ TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
|
|
+ sizeof(long));
|
|
+ tcg_out_ld(s, TCG_TYPE_REG, TCG_AREG0, TCG_REG_CALL_STACK,
|
|
+ TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
|
|
+ sizeof(long));
|
|
break;
|
|
case INDEX_op_jmp:
|
|
case INDEX_op_br:
|
|
@@ -1348,6 +1246,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
|
|
tcg_out_qemu_ld(s, args, 2 | 4);
|
|
break;
|
|
#endif
|
|
+ case INDEX_op_qemu_ld64:
|
|
+ tcg_out_qemu_ld(s, args, 3);
|
|
+ break;
|
|
case INDEX_op_qemu_st8:
|
|
tcg_out_qemu_st(s, args, 0);
|
|
break;
|
|
@@ -1357,6 +1258,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
|
|
case INDEX_op_qemu_st32:
|
|
tcg_out_qemu_st(s, args, 2);
|
|
break;
|
|
+ case INDEX_op_qemu_st64:
|
|
+ tcg_out_qemu_st(s, args, 3);
|
|
+ break;
|
|
|
|
#if TCG_TARGET_REG_BITS == 64
|
|
case INDEX_op_movi_i64:
|
|
@@ -1421,13 +1325,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
|
|
args[2], const_args[2]);
|
|
break;
|
|
|
|
- case INDEX_op_qemu_ld64:
|
|
- tcg_out_qemu_ld(s, args, 3);
|
|
- break;
|
|
- case INDEX_op_qemu_st64:
|
|
- tcg_out_qemu_st(s, args, 3);
|
|
- break;
|
|
-
|
|
#endif
|
|
gen_arith:
|
|
tcg_out_arithc(s, args[0], args[1], args[2], const_args[2], c);
|
|
@@ -1492,20 +1389,6 @@ static const TCGTargetOpDef sparc_op_defs[] = {
|
|
{ INDEX_op_mulu2_i32, { "r", "r", "r", "rJ" } },
|
|
#endif
|
|
|
|
- { INDEX_op_qemu_ld8u, { "r", "L" } },
|
|
- { INDEX_op_qemu_ld8s, { "r", "L" } },
|
|
- { INDEX_op_qemu_ld16u, { "r", "L" } },
|
|
- { INDEX_op_qemu_ld16s, { "r", "L" } },
|
|
- { INDEX_op_qemu_ld32, { "r", "L" } },
|
|
-#if TCG_TARGET_REG_BITS == 64
|
|
- { INDEX_op_qemu_ld32u, { "r", "L" } },
|
|
- { INDEX_op_qemu_ld32s, { "r", "L" } },
|
|
-#endif
|
|
-
|
|
- { INDEX_op_qemu_st8, { "L", "L" } },
|
|
- { INDEX_op_qemu_st16, { "L", "L" } },
|
|
- { INDEX_op_qemu_st32, { "L", "L" } },
|
|
-
|
|
#if TCG_TARGET_REG_BITS == 64
|
|
{ INDEX_op_mov_i64, { "r", "r" } },
|
|
{ INDEX_op_movi_i64, { "r" } },
|
|
@@ -1520,8 +1403,6 @@ static const TCGTargetOpDef sparc_op_defs[] = {
|
|
{ INDEX_op_st16_i64, { "r", "r" } },
|
|
{ INDEX_op_st32_i64, { "r", "r" } },
|
|
{ INDEX_op_st_i64, { "r", "r" } },
|
|
- { INDEX_op_qemu_ld64, { "L", "L" } },
|
|
- { INDEX_op_qemu_st64, { "L", "L" } },
|
|
|
|
{ INDEX_op_add_i64, { "r", "r", "rJ" } },
|
|
{ INDEX_op_mul_i64, { "r", "r", "rJ" } },
|
|
@@ -1548,10 +1429,48 @@ static const TCGTargetOpDef sparc_op_defs[] = {
|
|
|
|
{ INDEX_op_brcond_i64, { "r", "rJ" } },
|
|
{ INDEX_op_setcond_i64, { "r", "r", "rJ" } },
|
|
-#else
|
|
- { INDEX_op_qemu_ld64, { "L", "L", "L" } },
|
|
+#endif
|
|
+
|
|
+#if TCG_TARGET_REG_BITS == 64
|
|
+ { INDEX_op_qemu_ld8u, { "r", "L" } },
|
|
+ { INDEX_op_qemu_ld8s, { "r", "L" } },
|
|
+ { INDEX_op_qemu_ld16u, { "r", "L" } },
|
|
+ { INDEX_op_qemu_ld16s, { "r", "L" } },
|
|
+ { INDEX_op_qemu_ld32, { "r", "L" } },
|
|
+ { INDEX_op_qemu_ld32u, { "r", "L" } },
|
|
+ { INDEX_op_qemu_ld32s, { "r", "L" } },
|
|
+ { INDEX_op_qemu_ld64, { "r", "L" } },
|
|
+
|
|
+ { INDEX_op_qemu_st8, { "L", "L" } },
|
|
+ { INDEX_op_qemu_st16, { "L", "L" } },
|
|
+ { INDEX_op_qemu_st32, { "L", "L" } },
|
|
+ { INDEX_op_qemu_st64, { "L", "L" } },
|
|
+#elif TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
|
|
+ { INDEX_op_qemu_ld8u, { "r", "L" } },
|
|
+ { INDEX_op_qemu_ld8s, { "r", "L" } },
|
|
+ { INDEX_op_qemu_ld16u, { "r", "L" } },
|
|
+ { INDEX_op_qemu_ld16s, { "r", "L" } },
|
|
+ { INDEX_op_qemu_ld32, { "r", "L" } },
|
|
+ { INDEX_op_qemu_ld64, { "r", "r", "L" } },
|
|
+
|
|
+ { INDEX_op_qemu_st8, { "L", "L" } },
|
|
+ { INDEX_op_qemu_st16, { "L", "L" } },
|
|
+ { INDEX_op_qemu_st32, { "L", "L" } },
|
|
{ INDEX_op_qemu_st64, { "L", "L", "L" } },
|
|
+#else
|
|
+ { INDEX_op_qemu_ld8u, { "r", "L", "L" } },
|
|
+ { INDEX_op_qemu_ld8s, { "r", "L", "L" } },
|
|
+ { INDEX_op_qemu_ld16u, { "r", "L", "L" } },
|
|
+ { INDEX_op_qemu_ld16s, { "r", "L", "L" } },
|
|
+ { INDEX_op_qemu_ld32, { "r", "L", "L" } },
|
|
+ { INDEX_op_qemu_ld64, { "L", "L", "L", "L" } },
|
|
+
|
|
+ { INDEX_op_qemu_st8, { "L", "L", "L" } },
|
|
+ { INDEX_op_qemu_st16, { "L", "L", "L" } },
|
|
+ { INDEX_op_qemu_st32, { "L", "L", "L" } },
|
|
+ { INDEX_op_qemu_st64, { "L", "L", "L", "L" } },
|
|
#endif
|
|
+
|
|
{ -1 },
|
|
};
|
|
|
|
--
|
|
1.8.0.2
|
|
|