Fix libvirt + seccomp combo (bz #855162) Fix scsi hotplug crash (bz #879657) Fix QOM refcount crash (bz #881486)
283 lines
8.3 KiB
Diff
283 lines
8.3 KiB
Diff
From 25e9a95d0571c40738daa479467d757eb477739e Mon Sep 17 00:00:00 2001
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From: Blue Swirl <blauwirbel@gmail.com>
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Date: Sun, 2 Sep 2012 06:57:17 +0000
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Subject: [PATCH] target-lm32: switch to AREG0 free mode
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Add an explicit CPUState parameter instead of relying on AREG0
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and switch to AREG0 free mode.
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Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
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---
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configure | 2 +-
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target-lm32/Makefile.objs | 2 --
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target-lm32/helper.h | 20 ++++++++++----------
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target-lm32/op_helper.c | 29 +++++++++++------------------
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target-lm32/translate.c | 28 +++++++++++++---------------
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5 files changed, 35 insertions(+), 46 deletions(-)
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diff --git a/configure b/configure
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index 3ad6f74..1e3ea7f 100755
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--- a/configure
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+++ b/configure
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@@ -3839,7 +3839,7 @@ symlink "$source_path/Makefile.target" "$target_dir/Makefile"
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case "$target_arch2" in
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- alpha | i386 | or32 | s390x | sparc* | x86_64 | xtensa* | ppc*)
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+ alpha | i386 | lm32 | or32 | s390x | sparc* | x86_64 | xtensa* | ppc*)
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echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
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;;
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esac
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diff --git a/target-lm32/Makefile.objs b/target-lm32/Makefile.objs
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index 2e0e093..ca20f21 100644
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--- a/target-lm32/Makefile.objs
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+++ b/target-lm32/Makefile.objs
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@@ -1,4 +1,2 @@
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obj-y += translate.o op_helper.o helper.o cpu.o
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obj-$(CONFIG_SOFTMMU) += machine.o
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-
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-$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
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diff --git a/target-lm32/helper.h b/target-lm32/helper.h
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index 9d335ef..07f5670 100644
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--- a/target-lm32/helper.h
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+++ b/target-lm32/helper.h
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@@ -1,14 +1,14 @@
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#include "def-helper.h"
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-DEF_HELPER_1(raise_exception, void, i32)
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-DEF_HELPER_0(hlt, void)
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-DEF_HELPER_1(wcsr_im, void, i32)
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-DEF_HELPER_1(wcsr_ip, void, i32)
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-DEF_HELPER_1(wcsr_jtx, void, i32)
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-DEF_HELPER_1(wcsr_jrx, void, i32)
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-DEF_HELPER_0(rcsr_im, i32)
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-DEF_HELPER_0(rcsr_ip, i32)
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-DEF_HELPER_0(rcsr_jtx, i32)
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-DEF_HELPER_0(rcsr_jrx, i32)
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+DEF_HELPER_2(raise_exception, void, env, i32)
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+DEF_HELPER_1(hlt, void, env)
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+DEF_HELPER_2(wcsr_im, void, env, i32)
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+DEF_HELPER_2(wcsr_ip, void, env, i32)
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+DEF_HELPER_2(wcsr_jtx, void, env, i32)
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+DEF_HELPER_2(wcsr_jrx, void, env, i32)
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+DEF_HELPER_1(rcsr_im, i32, env)
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+DEF_HELPER_1(rcsr_ip, i32, env)
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+DEF_HELPER_1(rcsr_jtx, i32, env)
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+DEF_HELPER_1(rcsr_jrx, i32, env)
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#include "def-helper.h"
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diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c
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index 51edc1a..7b91d8c 100644
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--- a/target-lm32/op_helper.c
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+++ b/target-lm32/op_helper.c
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@@ -1,6 +1,5 @@
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#include <assert.h>
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#include "cpu.h"
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-#include "dyngen-exec.h"
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#include "helper.h"
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#include "host-utils.h"
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@@ -18,55 +17,55 @@
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#define SHIFT 3
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#include "softmmu_template.h"
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-void helper_raise_exception(uint32_t index)
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+void helper_raise_exception(CPULM32State *env, uint32_t index)
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{
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env->exception_index = index;
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cpu_loop_exit(env);
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}
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-void helper_hlt(void)
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+void helper_hlt(CPULM32State *env)
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{
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env->halted = 1;
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env->exception_index = EXCP_HLT;
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cpu_loop_exit(env);
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}
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-void helper_wcsr_im(uint32_t im)
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+void helper_wcsr_im(CPULM32State *env, uint32_t im)
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{
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lm32_pic_set_im(env->pic_state, im);
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}
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-void helper_wcsr_ip(uint32_t im)
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+void helper_wcsr_ip(CPULM32State *env, uint32_t im)
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{
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lm32_pic_set_ip(env->pic_state, im);
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}
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-void helper_wcsr_jtx(uint32_t jtx)
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+void helper_wcsr_jtx(CPULM32State *env, uint32_t jtx)
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{
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lm32_juart_set_jtx(env->juart_state, jtx);
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}
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-void helper_wcsr_jrx(uint32_t jrx)
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+void helper_wcsr_jrx(CPULM32State *env, uint32_t jrx)
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{
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lm32_juart_set_jrx(env->juart_state, jrx);
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}
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-uint32_t helper_rcsr_im(void)
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+uint32_t helper_rcsr_im(CPULM32State *env)
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{
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return lm32_pic_get_im(env->pic_state);
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}
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-uint32_t helper_rcsr_ip(void)
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+uint32_t helper_rcsr_ip(CPULM32State *env)
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{
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return lm32_pic_get_ip(env->pic_state);
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}
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-uint32_t helper_rcsr_jtx(void)
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+uint32_t helper_rcsr_jtx(CPULM32State *env)
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{
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return lm32_juart_get_jtx(env->juart_state);
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}
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-uint32_t helper_rcsr_jrx(void)
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+uint32_t helper_rcsr_jrx(CPULM32State *env)
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{
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return lm32_juart_get_jrx(env->juart_state);
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}
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@@ -74,17 +73,12 @@ uint32_t helper_rcsr_jrx(void)
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/* Try to fill the TLB and return an exception if error. If retaddr is
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NULL, it means that the function was called in C code (i.e. not
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from generated code or from helper.c) */
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-/* XXX: fix it to restore all registers */
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-void tlb_fill(CPULM32State *env1, target_ulong addr, int is_write, int mmu_idx,
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+void tlb_fill(CPULM32State *env, target_ulong addr, int is_write, int mmu_idx,
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uintptr_t retaddr)
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{
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TranslationBlock *tb;
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- CPULM32State *saved_env;
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int ret;
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- saved_env = env;
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- env = env1;
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-
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ret = cpu_lm32_handle_mmu_fault(env, addr, is_write, mmu_idx);
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if (unlikely(ret)) {
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if (retaddr) {
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@@ -98,7 +92,6 @@ void tlb_fill(CPULM32State *env1, target_ulong addr, int is_write, int mmu_idx,
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}
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cpu_loop_exit(env);
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}
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- env = saved_env;
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}
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#endif
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diff --git a/target-lm32/translate.c b/target-lm32/translate.c
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index 872a2ba..5f6dcba 100644
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--- a/target-lm32/translate.c
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+++ b/target-lm32/translate.c
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@@ -116,7 +116,7 @@ static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
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{
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TCGv_i32 tmp = tcg_const_i32(index);
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- gen_helper_raise_exception(tmp);
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+ gen_helper_raise_exception(cpu_env, tmp);
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tcg_temp_free_i32(tmp);
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}
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@@ -179,7 +179,7 @@ static void dec_and(DisasContext *dc)
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} else {
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if (dc->r0 == 0 && dc->r1 == 0 && dc->r2 == 0) {
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tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
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- gen_helper_hlt();
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+ gen_helper_hlt(cpu_env);
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} else {
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tcg_gen_and_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
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}
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@@ -601,10 +601,10 @@ static void dec_rcsr(DisasContext *dc)
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tcg_gen_mov_tl(cpu_R[dc->r2], cpu_ie);
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break;
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case CSR_IM:
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- gen_helper_rcsr_im(cpu_R[dc->r2]);
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+ gen_helper_rcsr_im(cpu_R[dc->r2], cpu_env);
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break;
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case CSR_IP:
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- gen_helper_rcsr_ip(cpu_R[dc->r2]);
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+ gen_helper_rcsr_ip(cpu_R[dc->r2], cpu_env);
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break;
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case CSR_CC:
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tcg_gen_mov_tl(cpu_R[dc->r2], cpu_cc);
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@@ -622,10 +622,10 @@ static void dec_rcsr(DisasContext *dc)
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tcg_gen_mov_tl(cpu_R[dc->r2], cpu_deba);
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break;
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case CSR_JTX:
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- gen_helper_rcsr_jtx(cpu_R[dc->r2]);
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+ gen_helper_rcsr_jtx(cpu_R[dc->r2], cpu_env);
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break;
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case CSR_JRX:
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- gen_helper_rcsr_jrx(cpu_R[dc->r2]);
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+ gen_helper_rcsr_jrx(cpu_R[dc->r2], cpu_env);
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break;
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case CSR_ICC:
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case CSR_DCC:
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@@ -812,7 +812,7 @@ static void dec_wcsr(DisasContext *dc)
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if (use_icount) {
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gen_io_start();
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}
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- gen_helper_wcsr_im(cpu_R[dc->r1]);
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+ gen_helper_wcsr_im(cpu_env, cpu_R[dc->r1]);
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tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
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if (use_icount) {
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gen_io_end();
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@@ -824,7 +824,7 @@ static void dec_wcsr(DisasContext *dc)
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if (use_icount) {
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gen_io_start();
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}
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- gen_helper_wcsr_ip(cpu_R[dc->r1]);
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+ gen_helper_wcsr_ip(cpu_env, cpu_R[dc->r1]);
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tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
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if (use_icount) {
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gen_io_end();
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@@ -844,10 +844,10 @@ static void dec_wcsr(DisasContext *dc)
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tcg_gen_mov_tl(cpu_deba, cpu_R[dc->r1]);
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break;
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case CSR_JTX:
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- gen_helper_wcsr_jtx(cpu_R[dc->r1]);
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+ gen_helper_wcsr_jtx(cpu_env, cpu_R[dc->r1]);
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break;
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case CSR_JRX:
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- gen_helper_wcsr_jrx(cpu_R[dc->r1]);
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+ gen_helper_wcsr_jrx(cpu_env, cpu_R[dc->r1]);
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break;
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case CSR_DC:
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tcg_gen_mov_tl(cpu_dc, cpu_R[dc->r1]);
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@@ -940,15 +940,13 @@ static const DecoderInfo decinfo[] = {
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dec_cmpne
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};
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-static inline void decode(DisasContext *dc)
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+static inline void decode(DisasContext *dc, uint32_t ir)
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{
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- uint32_t ir;
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-
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if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
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tcg_gen_debug_insn_start(dc->pc);
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}
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- dc->ir = ir = ldl_code(dc->pc);
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+ dc->ir = ir;
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LOG_DIS("%8.8x\t", dc->ir);
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/* try guessing 'empty' instruction memory, although it may be a valid
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@@ -1068,7 +1066,7 @@ static void gen_intermediate_code_internal(CPULM32State *env,
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gen_io_start();
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}
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- decode(dc);
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+ decode(dc, cpu_ldl_code(env, dc->pc));
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dc->pc += 4;
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num_insns++;
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--
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1.8.0.2
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