350 lines
12 KiB
Diff
350 lines
12 KiB
Diff
From 2ed404cacc625272fb7017476634b77002ee880b Mon Sep 17 00:00:00 2001
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From: Gerd Hoffmann <kraxel@redhat.com>
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Date: Tue, 28 Aug 2012 13:38:01 +0200
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Subject: [PATCH] xhci: update port handling
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This patch changes the way xhci ports are linked to USBPorts. The fixed
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1:1 relationship between xhci ports and USBPorts is gone. Now each
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USBPort represents a physical plug which has usually two xhci ports
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assigned: one usb2 and ond usb3 port. usb devices show up at one or the
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other, depending on whenever they support superspeed or not.
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This patch also makes the number of usb2 and usb3 ports runtime
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configurable by adding 'p2' and 'p3' properties. It is allowed to
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have different numbers of usb2 and usb3 ports. Specifying p2=4,p3=2
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will give you an xhci adapter which supports all speeds on physical
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ports 1+2 and usb2 only on ports 3+4.
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---
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hw/usb/hcd-xhci.c | 137 ++++++++++++++++++++++++++++++++++++++----------------
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1 file changed, 97 insertions(+), 40 deletions(-)
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diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
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index 11cb3bc..642e8e5 100644
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--- a/hw/usb/hcd-xhci.c
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+++ b/hw/usb/hcd-xhci.c
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@@ -36,10 +36,10 @@
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#define FIXME() do { fprintf(stderr, "FIXME %s:%d\n", \
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__func__, __LINE__); abort(); } while (0)
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-#define USB2_PORTS 4
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-#define USB3_PORTS 4
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+#define MAXPORTS_2 8
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+#define MAXPORTS_3 8
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-#define MAXPORTS (USB2_PORTS+USB3_PORTS)
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+#define MAXPORTS (MAXPORTS_2+MAXPORTS_3)
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#define MAXSLOTS MAXPORTS
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#define MAXINTRS 1 /* MAXPORTS */
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@@ -300,8 +300,10 @@ typedef struct XHCIRing {
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} XHCIRing;
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typedef struct XHCIPort {
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- USBPort port;
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uint32_t portsc;
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+ uint32_t portnr;
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+ USBPort *uport;
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+ uint32_t speedmask;
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} XHCIPort;
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struct XHCIState;
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@@ -379,9 +381,13 @@ struct XHCIState {
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qemu_irq irq;
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MemoryRegion mem;
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const char *name;
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- uint32_t msi;
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unsigned int devaddr;
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+ /* properties */
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+ uint32_t numports_2;
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+ uint32_t numports_3;
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+ uint32_t msi;
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+
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/* Operational Registers */
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uint32_t usbcmd;
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uint32_t usbsts;
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@@ -392,8 +398,10 @@ struct XHCIState {
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uint32_t dcbaap_high;
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uint32_t config;
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+ USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)];
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XHCIPort ports[MAXPORTS];
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XHCISlot slots[MAXSLOTS];
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+ uint32_t numports;
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/* Runtime Registers */
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uint32_t iman;
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@@ -578,6 +586,28 @@ static inline dma_addr_t xhci_mask64(uint64_t addr)
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}
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}
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+static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
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+{
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+ int index;
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+
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+ if (!uport->dev) {
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+ return NULL;
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+ }
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+ switch (uport->dev->speed) {
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+ case USB_SPEED_LOW:
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+ case USB_SPEED_FULL:
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+ case USB_SPEED_HIGH:
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+ index = uport->index;
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+ break;
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+ case USB_SPEED_SUPER:
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+ index = uport->index + xhci->numports_2;
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+ break;
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+ default:
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+ return NULL;
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+ }
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+ return &xhci->ports[index];
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+}
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+
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static void xhci_irq_update(XHCIState *xhci)
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{
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int level = 0;
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@@ -1126,7 +1156,7 @@ static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid,
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ep |= 0x80;
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}
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- dev = xhci->ports[xhci->slots[slotid-1].port-1].port.dev;
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+ dev = xhci->ports[xhci->slots[slotid-1].port-1].uport->dev;
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if (!dev) {
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return CC_USB_TRANSACTION_ERROR;
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}
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@@ -1313,7 +1343,7 @@ static USBDevice *xhci_find_device(XHCIPort *port, uint8_t addr)
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if (!(port->portsc & PORTSC_PED)) {
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return NULL;
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}
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- return usb_find_device(&port->port, addr);
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+ return usb_find_device(port->uport, addr);
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}
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static int xhci_setup_packet(XHCITransfer *xfer)
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@@ -1734,9 +1764,9 @@ static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
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ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
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port = (slot_ctx[1]>>16) & 0xFF;
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- dev = xhci->ports[port-1].port.dev;
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+ dev = xhci->ports[port-1].uport->dev;
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- if (port < 1 || port > MAXPORTS) {
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+ if (port < 1 || port > xhci->numports) {
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fprintf(stderr, "xhci: bad port %d\n", port);
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return CC_TRB_ERROR;
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} else if (!dev) {
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@@ -1985,7 +2015,7 @@ static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *tr
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static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
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{
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dma_addr_t ctx;
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- uint8_t bw_ctx[MAXPORTS+1];
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+ uint8_t bw_ctx[xhci->numports+1];
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DPRINTF("xhci_get_port_bandwidth()\n");
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@@ -1995,7 +2025,7 @@ static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
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/* TODO: actually implement real values here */
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bw_ctx[0] = 0;
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- memset(&bw_ctx[1], 80, MAXPORTS); /* 80% */
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+ memset(&bw_ctx[1], 80, xhci->numports); /* 80% */
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pci_dma_write(&xhci->pci_dev, ctx, bw_ctx, sizeof(bw_ctx));
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return CC_SUCCESS;
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@@ -2165,12 +2195,11 @@ static void xhci_process_commands(XHCIState *xhci)
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static void xhci_update_port(XHCIState *xhci, XHCIPort *port, int is_detach)
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{
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- int nr = port->port.index + 1;
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-
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port->portsc = PORTSC_PP;
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- if (port->port.dev && port->port.dev->attached && !is_detach) {
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+ if (port->uport->dev && port->uport->dev->attached && !is_detach &&
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+ (1 << port->uport->dev->speed) & port->speedmask) {
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port->portsc |= PORTSC_CCS;
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- switch (port->port.dev->speed) {
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+ switch (port->uport->dev->speed) {
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case USB_SPEED_LOW:
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port->portsc |= PORTSC_SPEED_LOW;
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break;
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@@ -2180,14 +2209,18 @@ static void xhci_update_port(XHCIState *xhci, XHCIPort *port, int is_detach)
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case USB_SPEED_HIGH:
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port->portsc |= PORTSC_SPEED_HIGH;
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break;
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+ case USB_SPEED_SUPER:
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+ port->portsc |= PORTSC_SPEED_SUPER;
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+ break;
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}
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}
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if (xhci_running(xhci)) {
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port->portsc |= PORTSC_CSC;
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- XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, nr << 24};
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+ XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS,
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+ port->portnr << 24};
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xhci_event(xhci, &ev);
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- DPRINTF("xhci: port change event for port %d\n", nr);
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+ DPRINTF("xhci: port change event for port %d\n", port->portnr);
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}
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}
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@@ -2215,7 +2248,7 @@ static void xhci_reset(DeviceState *dev)
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xhci_disable_slot(xhci, i+1);
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}
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- for (i = 0; i < MAXPORTS; i++) {
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+ for (i = 0; i < xhci->numports; i++) {
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xhci_update_port(xhci, xhci->ports + i, 0);
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}
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@@ -2246,7 +2279,8 @@ static uint32_t xhci_cap_read(XHCIState *xhci, uint32_t reg)
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ret = 0x01000000 | LEN_CAP;
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break;
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case 0x04: /* HCSPARAMS 1 */
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- ret = (MAXPORTS<<24) | (MAXINTRS<<8) | MAXSLOTS;
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+ ret = ((xhci->numports_2+xhci->numports_3)<<24)
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+ | (MAXINTRS<<8) | MAXSLOTS;
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break;
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case 0x08: /* HCSPARAMS 2 */
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ret = 0x0000000f;
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@@ -2276,7 +2310,7 @@ static uint32_t xhci_cap_read(XHCIState *xhci, uint32_t reg)
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ret = 0x20425355; /* "USB " */
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break;
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case 0x28: /* Supported Protocol:08 */
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- ret = 0x00000001 | (USB2_PORTS<<8);
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+ ret = 0x00000001 | (xhci->numports_2<<8);
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break;
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case 0x2c: /* Supported Protocol:0c */
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ret = 0x00000000; /* reserved */
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@@ -2288,7 +2322,7 @@ static uint32_t xhci_cap_read(XHCIState *xhci, uint32_t reg)
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ret = 0x20425355; /* "USB " */
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break;
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case 0x38: /* Supported Protocol:08 */
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- ret = 0x00000000 | (USB2_PORTS+1) | (USB3_PORTS<<8);
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+ ret = 0x00000000 | (xhci->numports_2+1) | (xhci->numports_3<<8);
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break;
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case 0x3c: /* Supported Protocol:0c */
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ret = 0x00000000; /* reserved */
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@@ -2307,7 +2341,7 @@ static uint32_t xhci_port_read(XHCIState *xhci, uint32_t reg)
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uint32_t port = reg >> 4;
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uint32_t ret;
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- if (port >= MAXPORTS) {
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+ if (port >= xhci->numports) {
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fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port);
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ret = 0;
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goto out;
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@@ -2340,7 +2374,7 @@ static void xhci_port_write(XHCIState *xhci, uint32_t reg, uint32_t val)
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trace_usb_xhci_port_write(port, reg & 0x0f, val);
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- if (port >= MAXPORTS) {
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+ if (port >= xhci->numports) {
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fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port);
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return;
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}
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@@ -2362,7 +2396,7 @@ static void xhci_port_write(XHCIState *xhci, uint32_t reg, uint32_t val)
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/* write-1-to-start bits */
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if (val & PORTSC_PR) {
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DPRINTF("xhci: port %d reset\n", port);
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- usb_device_reset(xhci->ports[port].port.dev);
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+ usb_device_reset(xhci->ports[port].uport->dev);
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portsc |= PORTSC_PRC | PORTSC_PED;
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}
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xhci->ports[port].portsc = portsc;
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@@ -2659,7 +2693,7 @@ static const MemoryRegionOps xhci_mem_ops = {
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static void xhci_attach(USBPort *usbport)
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{
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XHCIState *xhci = usbport->opaque;
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- XHCIPort *port = &xhci->ports[usbport->index];
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+ XHCIPort *port = xhci_lookup_port(xhci, usbport);
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xhci_update_port(xhci, port, 0);
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}
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@@ -2667,7 +2701,7 @@ static void xhci_attach(USBPort *usbport)
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static void xhci_detach(USBPort *usbport)
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{
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XHCIState *xhci = usbport->opaque;
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- XHCIPort *port = &xhci->ports[usbport->index];
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+ XHCIPort *port = xhci_lookup_port(xhci, usbport);
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xhci_update_port(xhci, port, 1);
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}
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@@ -2675,9 +2709,9 @@ static void xhci_detach(USBPort *usbport)
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static void xhci_wakeup(USBPort *usbport)
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{
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XHCIState *xhci = usbport->opaque;
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- XHCIPort *port = &xhci->ports[usbport->index];
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- int nr = port->port.index + 1;
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- XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, nr << 24};
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+ XHCIPort *port = xhci_lookup_port(xhci, usbport);
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+ XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS,
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+ port->portnr << 24};
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uint32_t pls;
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pls = (port->portsc >> PORTSC_PLS_SHIFT) & PORTSC_PLS_MASK;
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@@ -2759,22 +2793,43 @@ static USBBusOps xhci_bus_ops = {
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static void usb_xhci_init(XHCIState *xhci, DeviceState *dev)
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{
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- int i;
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+ XHCIPort *port;
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+ int i, usbports, speedmask;
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xhci->usbsts = USBSTS_HCH;
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+ if (xhci->numports_2 > MAXPORTS_2) {
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+ xhci->numports_2 = MAXPORTS_2;
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+ }
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+ if (xhci->numports_3 > MAXPORTS_3) {
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+ xhci->numports_3 = MAXPORTS_3;
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+ }
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+ usbports = MAX(xhci->numports_2, xhci->numports_3);
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+ xhci->numports = xhci->numports_2 + xhci->numports_3;
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+
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usb_bus_new(&xhci->bus, &xhci_bus_ops, &xhci->pci_dev.qdev);
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- for (i = 0; i < MAXPORTS; i++) {
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- memset(&xhci->ports[i], 0, sizeof(xhci->ports[i]));
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- usb_register_port(&xhci->bus, &xhci->ports[i].port, xhci, i,
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- &xhci_port_ops,
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- USB_SPEED_MASK_LOW |
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- USB_SPEED_MASK_FULL |
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- USB_SPEED_MASK_HIGH);
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- }
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- for (i = 0; i < MAXSLOTS; i++) {
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- xhci->slots[i].enabled = 0;
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+ for (i = 0; i < usbports; i++) {
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+ speedmask = 0;
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+ if (i < xhci->numports_2) {
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+ port = &xhci->ports[i];
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+ port->portnr = i + 1;
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+ port->uport = &xhci->uports[i];
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+ port->speedmask =
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+ USB_SPEED_MASK_LOW |
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+ USB_SPEED_MASK_FULL |
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+ USB_SPEED_MASK_HIGH;
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+ speedmask |= port->speedmask;
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+ }
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+ if (i < xhci->numports_3) {
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+ port = &xhci->ports[i + xhci->numports_2];
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+ port->portnr = i + 1 + xhci->numports_2;
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+ port->uport = &xhci->uports[i];
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+ port->speedmask = USB_SPEED_MASK_SUPER;
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+ speedmask |= port->speedmask;
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+ }
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+ usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i,
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+ &xhci_port_ops, speedmask);
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}
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}
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@@ -2830,6 +2885,8 @@ static const VMStateDescription vmstate_xhci = {
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static Property xhci_properties[] = {
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DEFINE_PROP_UINT32("msi", XHCIState, msi, 0),
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+ DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4),
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+ DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4),
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DEFINE_PROP_END_OF_LIST(),
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};
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