f375e62ad9
Fix libvirt + seccomp combo (bz #855162) Fix scsi hotplug crash (bz #879657) Fix QOM refcount crash (bz #881486)
78 lines
2.7 KiB
Diff
78 lines
2.7 KiB
Diff
From 7c3e573b364a65d4abce5266c376f4e77624b039 Mon Sep 17 00:00:00 2001
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From: Aurelien Jarno <aurelien@aurel32.net>
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Date: Fri, 21 Sep 2012 18:20:26 +0200
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Subject: [PATCH] tcg/mips: implement deposit op on MIPS32R2
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deposit operations can be optimized on MIPS32 Release 2 using the INS
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instruction.
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Reviewed-by: Richard Henderson <rth@twiddle.net>
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
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---
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tcg/mips/tcg-target.c | 8 ++++++++
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tcg/mips/tcg-target.h | 3 ++-
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2 files changed, 10 insertions(+), 1 deletion(-)
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diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
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index 592e42a..b2e1056 100644
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--- a/tcg/mips/tcg-target.c
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+++ b/tcg/mips/tcg-target.c
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@@ -328,6 +328,7 @@ enum {
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OPC_BGEZ = OPC_REGIMM | (0x01 << 16),
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OPC_SPECIAL3 = 0x1f << 26,
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+ OPC_INS = OPC_SPECIAL3 | 0x004,
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OPC_WSBH = OPC_SPECIAL3 | 0x0a0,
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OPC_SEB = OPC_SPECIAL3 | 0x420,
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OPC_SEH = OPC_SPECIAL3 | 0x620,
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@@ -1455,6 +1456,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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tcg_out_ext16s(s, args[0], args[1]);
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break;
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+ case INDEX_op_deposit_i32:
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+ tcg_out_opc_imm(s, OPC_INS, args[0], args[2],
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+ ((args[3] + args[4] - 1) << 11) | (args[3] << 6));
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+ break;
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+
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case INDEX_op_brcond_i32:
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tcg_out_brcond(s, args[2], args[0], args[1], args[3]);
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break;
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@@ -1550,6 +1556,8 @@ static const TCGTargetOpDef mips_op_defs[] = {
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{ INDEX_op_ext8s_i32, { "r", "rZ" } },
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{ INDEX_op_ext16s_i32, { "r", "rZ" } },
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+ { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
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+
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{ INDEX_op_brcond_i32, { "rZ", "rZ" } },
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{ INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
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{ INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },
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diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
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index 470314c..897a737 100644
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--- a/tcg/mips/tcg-target.h
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+++ b/tcg/mips/tcg-target.h
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@@ -86,7 +86,6 @@ typedef enum {
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#define TCG_TARGET_HAS_orc_i32 0
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#define TCG_TARGET_HAS_eqv_i32 0
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#define TCG_TARGET_HAS_nand_i32 0
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-#define TCG_TARGET_HAS_deposit_i32 0
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#define TCG_TARGET_HAS_movcond_i32 0
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/* optional instructions only implemented on MIPS32R2 */
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@@ -94,10 +93,12 @@ typedef enum {
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#define TCG_TARGET_HAS_bswap16_i32 1
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#define TCG_TARGET_HAS_bswap32_i32 1
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#define TCG_TARGET_HAS_rot_i32 1
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+#define TCG_TARGET_HAS_deposit_i32 1
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#else
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#define TCG_TARGET_HAS_bswap16_i32 0
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#define TCG_TARGET_HAS_bswap32_i32 0
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#define TCG_TARGET_HAS_rot_i32 0
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+#define TCG_TARGET_HAS_deposit_i32 0
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#endif
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/* optional instructions automatically implemented */
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--
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1.8.0.2
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