f375e62ad9
Fix libvirt + seccomp combo (bz #855162) Fix scsi hotplug crash (bz #879657) Fix QOM refcount crash (bz #881486)
66 lines
2.6 KiB
Diff
66 lines
2.6 KiB
Diff
From 061d22ad76512e8ec10af89eda1dcc7c185360d2 Mon Sep 17 00:00:00 2001
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From: Aurelien Jarno <aurelien@aurel32.net>
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Date: Fri, 21 Sep 2012 18:20:25 +0200
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Subject: [PATCH] tcg-mips: fix wrong usage of 'Z' constraint
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The 'Z' constraint has been introduced to map the zero register. However
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when the op also accept a constant, there is no point to accept the zero
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register in addition.
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Reviewed-by: Richard Henderson <rth@twiddle.net>
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
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---
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tcg/mips/tcg-target.c | 16 ++++++++--------
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1 file changed, 8 insertions(+), 8 deletions(-)
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diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
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index 74db83d..9293745 100644
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--- a/tcg/mips/tcg-target.c
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+++ b/tcg/mips/tcg-target.c
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@@ -1453,24 +1453,24 @@ static const TCGTargetOpDef mips_op_defs[] = {
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{ INDEX_op_st16_i32, { "rZ", "r" } },
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{ INDEX_op_st_i32, { "rZ", "r" } },
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- { INDEX_op_add_i32, { "r", "rZ", "rJZ" } },
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+ { INDEX_op_add_i32, { "r", "rZ", "rJ" } },
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{ INDEX_op_mul_i32, { "r", "rZ", "rZ" } },
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{ INDEX_op_mulu2_i32, { "r", "r", "rZ", "rZ" } },
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{ INDEX_op_div_i32, { "r", "rZ", "rZ" } },
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{ INDEX_op_divu_i32, { "r", "rZ", "rZ" } },
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{ INDEX_op_rem_i32, { "r", "rZ", "rZ" } },
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{ INDEX_op_remu_i32, { "r", "rZ", "rZ" } },
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- { INDEX_op_sub_i32, { "r", "rZ", "rJZ" } },
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+ { INDEX_op_sub_i32, { "r", "rZ", "rJ" } },
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- { INDEX_op_and_i32, { "r", "rZ", "rIZ" } },
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+ { INDEX_op_and_i32, { "r", "rZ", "rI" } },
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{ INDEX_op_nor_i32, { "r", "rZ", "rZ" } },
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{ INDEX_op_not_i32, { "r", "rZ" } },
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{ INDEX_op_or_i32, { "r", "rZ", "rIZ" } },
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{ INDEX_op_xor_i32, { "r", "rZ", "rIZ" } },
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- { INDEX_op_shl_i32, { "r", "rZ", "riZ" } },
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- { INDEX_op_shr_i32, { "r", "rZ", "riZ" } },
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- { INDEX_op_sar_i32, { "r", "rZ", "riZ" } },
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+ { INDEX_op_shl_i32, { "r", "rZ", "ri" } },
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+ { INDEX_op_shr_i32, { "r", "rZ", "ri" } },
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+ { INDEX_op_sar_i32, { "r", "rZ", "ri" } },
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{ INDEX_op_ext8s_i32, { "r", "rZ" } },
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{ INDEX_op_ext16s_i32, { "r", "rZ" } },
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@@ -1479,8 +1479,8 @@ static const TCGTargetOpDef mips_op_defs[] = {
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{ INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
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{ INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },
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- { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rJZ", "rJZ" } },
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- { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rJZ", "rJZ" } },
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+ { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } },
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+ { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } },
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{ INDEX_op_brcond2_i32, { "rZ", "rZ", "rZ", "rZ" } },
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#if TARGET_LONG_BITS == 32
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--
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1.8.0.2
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