f375e62ad9
Fix libvirt + seccomp combo (bz #855162) Fix scsi hotplug crash (bz #879657) Fix QOM refcount crash (bz #881486)
250 lines
10 KiB
Diff
250 lines
10 KiB
Diff
From c13ecfea174994d3f7f7d392f0faaed6d40efd9e Mon Sep 17 00:00:00 2001
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From: Richard Henderson <rth@twiddle.net>
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Date: Tue, 18 Sep 2012 19:59:48 -0700
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Subject: [PATCH] tcg-hppa: Fix broken load/store helpers
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The CONFIG_TCG_PASS_AREG0 code for calling ld/st helpers
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was not respecting the ABI requirement for 64-bit values
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being aligned in registers.
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Mirror the ARM port in use of helper functions to marshal
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arguments into the correct registers.
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Signed-off-by: Richard Henderson <rth@twiddle.net>
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
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---
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tcg/hppa/tcg-target.c | 136 +++++++++++++++++++++++++++-----------------------
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1 file changed, 74 insertions(+), 62 deletions(-)
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diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c
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index a76569d..5385d45 100644
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--- a/tcg/hppa/tcg-target.c
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+++ b/tcg/hppa/tcg-target.c
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@@ -976,10 +976,11 @@ static int tcg_out_tlb_read(TCGContext *s, int r0, int r1, int addrlo,
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R20, r1, offset);
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}
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- /* Compute the value that ought to appear in the TLB for a hit, namely, the page
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- of the address. We include the low N bits of the address to catch unaligned
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- accesses and force them onto the slow path. Do this computation after having
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- issued the load from the TLB slot to give the load time to complete. */
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+ /* Compute the value that ought to appear in the TLB for a hit, namely,
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+ the page of the address. We include the low N bits of the address
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+ to catch unaligned accesses and force them onto the slow path. Do
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+ this computation after having issued the load from the TLB slot to
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+ give the load time to complete. */
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tcg_out_andi(s, r0, addrlo, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
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/* If not equal, jump to lab_miss. */
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@@ -992,6 +993,36 @@ static int tcg_out_tlb_read(TCGContext *s, int r0, int r1, int addrlo,
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return ret;
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}
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+
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+static int tcg_out_arg_reg32(TCGContext *s, int argno, TCGArg v, bool vconst)
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+{
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+ if (argno < 4) {
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+ if (vconst) {
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+ tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[argno], v);
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+ } else {
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+ tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[argno], v);
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+ }
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+ } else {
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+ if (vconst && v != 0) {
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+ tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R20, v);
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+ v = TCG_REG_R20;
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+ }
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+ tcg_out_st(s, TCG_TYPE_I32, v, TCG_REG_CALL_STACK,
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+ TCG_TARGET_CALL_STACK_OFFSET - ((argno - 3) * 4));
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+ }
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+ return argno + 1;
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+}
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+
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+static int tcg_out_arg_reg64(TCGContext *s, int argno, TCGArg vl, TCGArg vh)
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+{
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+ /* 64-bit arguments must go in even reg pairs and stack slots. */
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+ if (argno & 1) {
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+ argno++;
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+ }
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+ argno = tcg_out_arg_reg32(s, argno, vl, false);
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+ argno = tcg_out_arg_reg32(s, argno, vh, false);
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+ return argno;
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+}
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#endif
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static void tcg_out_qemu_ld_direct(TCGContext *s, int datalo_reg, int datahi_reg,
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@@ -1072,39 +1103,36 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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/* Note that addrhi_reg is only used for 64-bit guests. */
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int addrhi_reg = (TARGET_LONG_BITS == 64 ? *args++ : TCG_REG_R0);
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int mem_index = *args;
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- int lab1, lab2, argreg, offset;
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+ int lab1, lab2, argno, offset;
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lab1 = gen_new_label();
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lab2 = gen_new_label();
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offset = offsetof(CPUArchState, tlb_table[mem_index][0].addr_read);
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- offset = tcg_out_tlb_read(s, TCG_REG_R26, TCG_REG_R25, addrlo_reg, addrhi_reg,
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- opc & 3, lab1, offset);
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+ offset = tcg_out_tlb_read(s, TCG_REG_R26, TCG_REG_R25, addrlo_reg,
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+ addrhi_reg, opc & 3, lab1, offset);
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/* TLB Hit. */
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- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R20, (offset ? TCG_REG_R1 : TCG_REG_R25),
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+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R20,
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+ (offset ? TCG_REG_R1 : TCG_REG_R25),
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offsetof(CPUArchState, tlb_table[mem_index][0].addend) - offset);
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- tcg_out_qemu_ld_direct(s, datalo_reg, datahi_reg, addrlo_reg, TCG_REG_R20, opc);
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+ tcg_out_qemu_ld_direct(s, datalo_reg, datahi_reg, addrlo_reg,
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+ TCG_REG_R20, opc);
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tcg_out_branch(s, lab2, 1);
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/* TLB Miss. */
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/* label1: */
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tcg_out_label(s, lab1, s->code_ptr);
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- argreg = TCG_REG_R26;
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- tcg_out_mov(s, TCG_TYPE_I32, argreg--, addrlo_reg);
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+ argno = 0;
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+ argno = tcg_out_arg_reg32(s, argno, TCG_AREG0, false);
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if (TARGET_LONG_BITS == 64) {
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- tcg_out_mov(s, TCG_TYPE_I32, argreg--, addrhi_reg);
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+ argno = tcg_out_arg_reg64(s, argno, addrlo_reg, addrhi_reg);
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+ } else {
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+ argno = tcg_out_arg_reg32(s, argno, addrlo_reg, false);
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}
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- tcg_out_movi(s, TCG_TYPE_I32, argreg, mem_index);
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-
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- /* XXX/FIXME: suboptimal */
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- tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2],
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- tcg_target_call_iarg_regs[1]);
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- tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1],
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- tcg_target_call_iarg_regs[0]);
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- tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
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- TCG_AREG0);
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+ argno = tcg_out_arg_reg32(s, argno, mem_index, true);
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+
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tcg_out_call(s, qemu_ld_helpers[opc & 3]);
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switch (opc) {
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@@ -1140,8 +1168,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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#endif
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}
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-static void tcg_out_qemu_st_direct(TCGContext *s, int datalo_reg, int datahi_reg,
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- int addr_reg, int opc)
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+static void tcg_out_qemu_st_direct(TCGContext *s, int datalo_reg,
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+ int datahi_reg, int addr_reg, int opc)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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const int bswap = 0;
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@@ -1194,17 +1222,18 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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/* Note that addrhi_reg is only used for 64-bit guests. */
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int addrhi_reg = (TARGET_LONG_BITS == 64 ? *args++ : TCG_REG_R0);
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int mem_index = *args;
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- int lab1, lab2, argreg, offset;
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+ int lab1, lab2, argno, next, offset;
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lab1 = gen_new_label();
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lab2 = gen_new_label();
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offset = offsetof(CPUArchState, tlb_table[mem_index][0].addr_write);
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- offset = tcg_out_tlb_read(s, TCG_REG_R26, TCG_REG_R25, addrlo_reg, addrhi_reg,
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- opc, lab1, offset);
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+ offset = tcg_out_tlb_read(s, TCG_REG_R26, TCG_REG_R25, addrlo_reg,
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+ addrhi_reg, opc, lab1, offset);
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/* TLB Hit. */
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- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R20, (offset ? TCG_REG_R1 : TCG_REG_R25),
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+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R20,
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+ (offset ? TCG_REG_R1 : TCG_REG_R25),
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offsetof(CPUArchState, tlb_table[mem_index][0].addend) - offset);
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/* There are no indexed stores, so we must do this addition explitly.
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@@ -1217,63 +1246,46 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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/* label1: */
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tcg_out_label(s, lab1, s->code_ptr);
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- argreg = TCG_REG_R26;
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- tcg_out_mov(s, TCG_TYPE_I32, argreg--, addrlo_reg);
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+ argno = 0;
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+ argno = tcg_out_arg_reg32(s, argno, TCG_AREG0, false);
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if (TARGET_LONG_BITS == 64) {
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- tcg_out_mov(s, TCG_TYPE_I32, argreg--, addrhi_reg);
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+ argno = tcg_out_arg_reg64(s, argno, addrlo_reg, addrhi_reg);
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+ } else {
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+ argno = tcg_out_arg_reg32(s, argno, addrlo_reg, false);
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}
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+ next = (argno < 4 ? tcg_target_call_iarg_regs[argno] : TCG_REG_R20);
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switch(opc) {
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case 0:
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- tcg_out_andi(s, argreg--, datalo_reg, 0xff);
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- tcg_out_movi(s, TCG_TYPE_I32, argreg, mem_index);
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+ tcg_out_andi(s, next, datalo_reg, 0xff);
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+ argno = tcg_out_arg_reg32(s, argno, next, false);
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break;
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case 1:
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- tcg_out_andi(s, argreg--, datalo_reg, 0xffff);
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- tcg_out_movi(s, TCG_TYPE_I32, argreg, mem_index);
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+ tcg_out_andi(s, next, datalo_reg, 0xffff);
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+ argno = tcg_out_arg_reg32(s, argno, next, false);
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break;
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case 2:
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- tcg_out_mov(s, TCG_TYPE_I32, argreg--, datalo_reg);
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- tcg_out_movi(s, TCG_TYPE_I32, argreg, mem_index);
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+ argno = tcg_out_arg_reg32(s, argno, datalo_reg, false);
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break;
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case 3:
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- /* Because of the alignment required by the 64-bit data argument,
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- we will always use R23/R24. Also, we will always run out of
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- argument registers for storing mem_index, so that will have
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- to go on the stack. */
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- if (mem_index == 0) {
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- argreg = TCG_REG_R0;
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- } else {
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- argreg = TCG_REG_R20;
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- tcg_out_movi(s, TCG_TYPE_I32, argreg, mem_index);
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- }
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- tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R23, datahi_reg);
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- tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R24, datalo_reg);
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- tcg_out_st(s, TCG_TYPE_I32, argreg, TCG_REG_CALL_STACK,
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- TCG_TARGET_CALL_STACK_OFFSET - 4);
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+ argno = tcg_out_arg_reg64(s, argno, datalo_reg, datahi_reg);
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break;
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default:
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tcg_abort();
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}
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+ argno = tcg_out_arg_reg32(s, argno, mem_index, true);
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- /* XXX/FIXME: suboptimal */
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- tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3],
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- tcg_target_call_iarg_regs[2]);
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- tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2],
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- tcg_target_call_iarg_regs[1]);
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- tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1],
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- tcg_target_call_iarg_regs[0]);
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- tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
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- TCG_AREG0);
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tcg_out_call(s, qemu_st_helpers[opc]);
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/* label2: */
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tcg_out_label(s, lab2, s->code_ptr);
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#else
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- /* There are no indexed stores, so if GUEST_BASE is set we must do the add
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- explicitly. Careful to avoid R20, which is used for the bswaps to follow. */
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+ /* There are no indexed stores, so if GUEST_BASE is set we must do
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+ the add explicitly. Careful to avoid R20, which is used for the
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+ bswaps to follow. */
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if (GUEST_BASE != 0) {
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- tcg_out_arith(s, TCG_REG_R31, addrlo_reg, TCG_GUEST_BASE_REG, INSN_ADDL);
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+ tcg_out_arith(s, TCG_REG_R31, addrlo_reg,
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+ TCG_GUEST_BASE_REG, INSN_ADDL);
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addrlo_reg = TCG_REG_R31;
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}
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tcg_out_qemu_st_direct(s, datalo_reg, datahi_reg, addrlo_reg, opc);
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--
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1.8.0.2
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