f375e62ad9
Fix libvirt + seccomp combo (bz #855162) Fix scsi hotplug crash (bz #879657) Fix QOM refcount crash (bz #881486)
119 lines
4.3 KiB
Diff
119 lines
4.3 KiB
Diff
From 7a6273e2995b6c439441316467ab19bd6a48f03f Mon Sep 17 00:00:00 2001
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From: Richard Henderson <rth@twiddle.net>
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Date: Fri, 21 Sep 2012 10:13:36 -0700
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Subject: [PATCH] tcg-i386: Implement movcond
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Signed-off-by: Richard Henderson <rth@twiddle.net>
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Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
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---
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tcg/i386/tcg-target.c | 29 +++++++++++++++++++++++++++++
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tcg/i386/tcg-target.h | 7 ++++++-
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2 files changed, 35 insertions(+), 1 deletion(-)
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diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
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index 3017858..aa1fa9f 100644
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--- a/tcg/i386/tcg-target.c
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+++ b/tcg/i386/tcg-target.c
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@@ -249,6 +249,7 @@ static inline int tcg_target_const_match(tcg_target_long val,
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#define OPC_ADD_GvEv (OPC_ARITH_GvEv | (ARITH_ADD << 3))
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#define OPC_BSWAP (0xc8 | P_EXT)
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#define OPC_CALL_Jz (0xe8)
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+#define OPC_CMOVCC (0x40 | P_EXT) /* ... plus condition code */
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#define OPC_CMP_GvEv (OPC_ARITH_GvEv | (ARITH_CMP << 3))
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#define OPC_DEC_r32 (0x48)
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#define OPC_IMUL_GvEv (0xaf | P_EXT)
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@@ -936,6 +937,24 @@ static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
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}
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#endif
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+static void tcg_out_movcond32(TCGContext *s, TCGCond cond, TCGArg dest,
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+ TCGArg c1, TCGArg c2, int const_c2,
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+ TCGArg v1)
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+{
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+ tcg_out_cmp(s, c1, c2, const_c2, 0);
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+ tcg_out_modrm(s, OPC_CMOVCC | tcg_cond_to_jcc[cond], dest, v1);
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+}
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+
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+#if TCG_TARGET_REG_BITS == 64
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+static void tcg_out_movcond64(TCGContext *s, TCGCond cond, TCGArg dest,
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+ TCGArg c1, TCGArg c2, int const_c2,
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+ TCGArg v1)
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+{
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+ tcg_out_cmp(s, c1, c2, const_c2, P_REXW);
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+ tcg_out_modrm(s, OPC_CMOVCC | tcg_cond_to_jcc[cond] | P_REXW, dest, v1);
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+}
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+#endif
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+
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static void tcg_out_branch(TCGContext *s, int call, tcg_target_long dest)
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{
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tcg_target_long disp = dest - (tcg_target_long)s->code_ptr - 5;
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@@ -1668,6 +1687,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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tcg_out_setcond32(s, args[3], args[0], args[1],
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args[2], const_args[2]);
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break;
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+ case INDEX_op_movcond_i32:
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+ tcg_out_movcond32(s, args[5], args[0], args[1],
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+ args[2], const_args[2], args[3]);
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+ break;
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OP_32_64(bswap16):
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tcg_out_rolw_8(s, args[0]);
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@@ -1796,6 +1819,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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tcg_out_setcond64(s, args[3], args[0], args[1],
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args[2], const_args[2]);
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break;
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+ case INDEX_op_movcond_i64:
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+ tcg_out_movcond64(s, args[5], args[0], args[1],
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+ args[2], const_args[2], args[3]);
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+ break;
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case INDEX_op_bswap64_i64:
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tcg_out_bswap64(s, args[0]);
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@@ -1880,6 +1907,7 @@ static const TCGTargetOpDef x86_op_defs[] = {
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{ INDEX_op_setcond_i32, { "q", "r", "ri" } },
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{ INDEX_op_deposit_i32, { "Q", "0", "Q" } },
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+ { INDEX_op_movcond_i32, { "r", "r", "ri", "r", "0" } },
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#if TCG_TARGET_REG_BITS == 32
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{ INDEX_op_mulu2_i32, { "a", "d", "a", "r" } },
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@@ -1934,6 +1962,7 @@ static const TCGTargetOpDef x86_op_defs[] = {
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{ INDEX_op_ext32u_i64, { "r", "r" } },
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{ INDEX_op_deposit_i64, { "Q", "0", "Q" } },
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+ { INDEX_op_movcond_i64, { "r", "r", "re", "r", "0" } },
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#endif
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#if TCG_TARGET_REG_BITS == 64
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diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
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index 504f953..b356d76 100644
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--- a/tcg/i386/tcg-target.h
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+++ b/tcg/i386/tcg-target.h
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@@ -86,7 +86,12 @@ typedef enum {
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#define TCG_TARGET_HAS_nand_i32 0
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#define TCG_TARGET_HAS_nor_i32 0
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#define TCG_TARGET_HAS_deposit_i32 1
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+#if defined(__x86_64__) || defined(__i686__)
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+/* Use cmov only if the compiler is already doing so. */
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+#define TCG_TARGET_HAS_movcond_i32 1
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+#else
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#define TCG_TARGET_HAS_movcond_i32 0
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+#endif
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#if TCG_TARGET_REG_BITS == 64
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#define TCG_TARGET_HAS_div2_i64 1
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@@ -108,7 +113,7 @@ typedef enum {
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#define TCG_TARGET_HAS_nand_i64 0
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#define TCG_TARGET_HAS_nor_i64 0
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#define TCG_TARGET_HAS_deposit_i64 1
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-#define TCG_TARGET_HAS_movcond_i64 0
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+#define TCG_TARGET_HAS_movcond_i64 1
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#endif
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#define TCG_TARGET_deposit_i32_valid(ofs, len) \
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--
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1.8.0.2
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