36 lines
1.2 KiB
Diff
36 lines
1.2 KiB
Diff
From b1fffeed071302ff3a7f69a680ec0aa930bc403e Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?=E9=99=B3=E9=9F=8B=E4=BB=BB=20=28Wei-Ren=20Chen=29?=
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<chenwj@iis.sinica.edu.tw>
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Date: Wed, 14 Nov 2012 10:49:55 +0800
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Subject: [PATCH] target-mips: fix wrong microMIPS opcode encoding
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While reading microMIPS decoding, I found a possible wrong opcode
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encoding. According to [1] page 166, the bits 13..12 for MULTU is
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0x01 rather than 0x00. Please review, thanks.
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[1] MIPS Architecture for Programmers VolumeIV-e: The MIPS DSP
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Application-Specific Extension to the microMIPS32 Architecture
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Signed-off-by: Chen Wei-Ren <chenwj@iis.sinica.edu.tw>
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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(cherry picked from commit 6801038bc52d61f81ac8a25fbe392f1bad982887)
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Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
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---
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target-mips/translate.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/target-mips/translate.c b/target-mips/translate.c
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index 4e04e97..49907bb 100644
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--- a/target-mips/translate.c
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+++ b/target-mips/translate.c
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@@ -9486,7 +9486,7 @@ enum {
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/* bits 13..12 for 0x32 */
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MULT_ACC = 0x0,
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- MULTU_ACC = 0x0,
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+ MULTU_ACC = 0x1,
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/* bits 15..12 for 0x2c */
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SEB = 0x2,
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