Enable librbd and libfdt

Conflicts:
	qemu.spec

0001-target-xtensa-convert-host-errno-values-to-guest.patch

@@ -178,6 +178,3 @@ index 6d001c2..e745bef 100644
          break;
      }
  }
--- 
-1.7.12.1
-

0002-target-cris-Fix-buffer-overflow.patch

@@ -30,6 +30,3 @@ index 1ad9ec7..ad31877 100644
  		for (i = 0; i < 16; i++) {
  			cpu_fprintf(f, "s%2.2d=%8.8x ",
  				    i, env->sregs[srs][i]);
--- 
-1.7.12.1
-

0003-target-xtensa-fix-missing-errno-codes-for-mingw32.patch

@@ -59,6 +59,3 @@ index e745bef..52be07a 100644
      };
  
      if (host_errno == 0) {
--- 
-1.7.12.1
-

0004-target-sparc-fix-fcmp-s-d-q-instructions-wrt-excepti.patch

@@ -128,6 +128,3 @@ index 9c64ef8..f4b62a5 100644
              env->fsr |= FSR_FCC1 << FS;                                 \
              break;                                                      \
          default:                                                        \
--- 
-1.7.12.1
-

0005-target-s390x-fix-style.patch

@@ -1598,6 +1598,3 @@ index abc35dd..195e93e 100644
      } else {
          env->regs[r1] = ret;
      }
--- 
-1.7.12.1
-

0006-target-s390x-split-FPU-ops.patch

@@ -1751,6 +1751,3 @@ index 1c1baf5..c370df3 100644
          tcg_temp_free_i32(tmp32);
          break;
      case 0xd: /* DEB    R1,D2(X2,B2)       [RXE] */
--- 
-1.7.12.1
-

0007-target-s390x-split-condition-code-helpers.patch

@@ -1153,6 +1153,3 @@ index 270bf14..eced890 100644
  /* invalidate pte */
  void HELPER(ipte)(uint64_t pte_addr, uint64_t vaddr)
  {
--- 
-1.7.12.1
-

0008-target-s390x-split-integer-helpers.patch

@@ -439,6 +439,3 @@ index eced890..3b8b997 100644
  void HELPER(unpk)(uint32_t len, uint64_t dest, uint64_t src)
  {
      int len_dest = len >> 4;
--- 
-1.7.12.1
-

0009-target-s390x-split-memory-access-helpers.patch

@@ -2419,6 +2419,3 @@ index 3b8b997..bb8dbf5 100644
 -}
 -
  #endif
--- 
-1.7.12.1
-

0010-target-s390x-rename-op_helper.c-to-misc_helper.c.patch

@@ -919,6 +919,3 @@ index bb8dbf5..0000000
 -    return cc;
 -}
 -#endif
--- 
-1.7.12.1
-

0011-target-s390x-avoid-AREG0-for-FPU-helpers.patch

@@ -1213,6 +1213,3 @@ index c370df3..b1f2071 100644
          set_cc_static(s);
          tcg_temp_free_i32(tmp32_1);
          tcg_temp_free_i32(tmp32_2);
--- 
-1.7.12.1
-

0012-target-s390x-avoid-AREG0-for-integer-helpers.patch

@@ -197,6 +197,3 @@ index b1f2071..2a61e92 100644
          set_cc_static(s);
          tcg_temp_free_i32(tmp32_1);
          tcg_temp_free_i32(tmp32_2);
--- 
-1.7.12.1
-

0013-target-s390x-avoid-AREG0-for-condition-code-helpers.patch

@@ -185,6 +185,3 @@ index 2a61e92..1d87272 100644
          tcg_temp_free_i64(tmp);
          tcg_temp_free_i64(tmp2);
          tcg_temp_free_i64(tmp3);
--- 
-1.7.12.1
-

0014-target-s390x-avoid-AREG0-for-misc-helpers.patch

@@ -406,6 +406,3 @@ index 1d87272..0c61e63 100644
          set_cc_static(s);
          tcg_temp_free_i64(tmp);
          tcg_temp_free_i64(tmp2);
--- 
-1.7.12.1
-

0015-target-s390x-switch-to-AREG0-free-mode.patch

@@ -1579,6 +1579,3 @@ index 0c61e63..66119cd 100644
          }
          set_cc_static(s);
          tcg_temp_free_i64(tmp);
--- 
-1.7.12.1
-

0016-tcg-s390-fix-ld-st-with-CONFIG_TCG_PASS_AREG0.patch

@@ -59,6 +59,3 @@ index 04662c1..99b5339 100644
                      TCG_AREG0);
  #endif
          tgen_calli(s, (tcg_target_ulong)qemu_ld_helpers[s_bits]);
--- 
-1.7.12.1
-

0017-target-arm-Fix-potential-buffer-overflow.patch

@@ -42,6 +42,3 @@ index dceaa95..e27df96 100644
          return EXCP_UDEF;
      }
      env->cp15.c6_region[ri->crm] = value;
--- 
-1.7.12.1
-

0018-tcg-optimize-split-expression-simplification.patch

@@ -52,6 +52,3 @@ index 9c65474..63f970d 100644
          CASE_OP_32_64(or):
          CASE_OP_32_64(and):
              if (args[1] == args[2]) {
--- 
-1.7.12.1
-

0019-tcg-optimize-simplify-or-xor-r-a-0-cases.patch

@@ -25,6 +25,3 @@ index 63f970d..0db849e 100644
              if (temps[args[1]].state == TCG_TEMP_CONST) {
                  /* Proceed with possible constant folding. */
                  break;
--- 
-1.7.12.1
-

0020-tcg-optimize-simplify-and-r-a-0-cases.patch

@@ -24,6 +24,3 @@ index 0db849e..c12cb2b 100644
          CASE_OP_32_64(mul):
              if ((temps[args[2]].state == TCG_TEMP_CONST
                  && temps[args[2]].val == 0)) {
--- 
-1.7.12.1
-

0021-tcg-optimize-simplify-shift-rot-r-0-a-movi-r-0-cases.patch

@@ -43,6 +43,3 @@ index c12cb2b..1698ba3 100644
          /* Simplify expression for "op r, a, 0 => mov r, a" cases */
          switch (op) {
          CASE_OP_32_64(add):
--- 
-1.7.12.1
-

0022-tcg-optimize-swap-brcond-setcond-arguments-when-poss.patch

@@ -44,6 +44,3 @@ index 1698ba3..7debc8a 100644
          default:
              break;
          }
--- 
-1.7.12.1
-

0023-tcg-optimize-add-constant-folding-for-setcond.patch

@@ -109,6 +109,3 @@ index 7debc8a..1cb1f36 100644
          case INDEX_op_call:
              nb_call_args = (args[0] >> 16) + (args[0] & 0xffff);
              if (!(args[nb_call_args + 1] & (TCG_CALL_CONST | TCG_CALL_PURE))) {
--- 
-1.7.12.1
-

0024-tcg-optimize-add-constant-folding-for-brcond.patch

@@ -55,6 +55,3 @@ index 1cb1f36..156e8d9 100644
              memset(temps, 0, nb_temps * sizeof(struct tcg_temp_info));
              for (i = 0; i < def->nb_args; i++) {
                  *gen_args = *args;
--- 
-1.7.12.1
-

0025-tcg-optimize-fix-if-else-break-coding-style.patch

@@ -139,6 +139,3 @@ index 156e8d9..fba0ed9 100644
          case INDEX_op_call:
              nb_call_args = (args[0] >> 16) + (args[0] & 0xffff);
              if (!(args[nb_call_args + 1] & (TCG_CALL_CONST | TCG_CALL_PURE))) {
--- 
-1.7.12.1
-

0026-target-s390x-avoid-cpu_single_env.patch

@@ -1332,6 +1332,3 @@ index 66119cd..3214783 100644
  
          num_insns++;
          if (env->singlestep_enabled) {
--- 
-1.7.12.1
-

0027-target-lm32-switch-to-AREG0-free-mode.patch

@@ -277,6 +277,3 @@ index 872a2ba..5f6dcba 100644
          dc->pc += 4;
          num_insns++;
  
--- 
-1.7.12.1
-

0028-target-m68k-switch-to-AREG0-free-mode.patch

@@ -497,6 +497,3 @@ index 9fc1e31..10bb303 100644
      } else {
          switch(dc->is_jmp) {
          case DISAS_NEXT:
--- 
-1.7.12.1
-

0029-target-m68k-avoid-using-cpu_single_env.patch

@@ -896,6 +896,3 @@ index 10bb303..fb707f2 100644
  }
  
  /* generate intermediate code for basic block 'tb'.  */
--- 
-1.7.12.1
-

0030-target-unicore32-switch-to-AREG0-free-mode.patch

@@ -432,6 +432,3 @@ index 188bf8c..b786a6b 100644
      s->pc += 4;
  
      /* UniCore instructions class:
--- 
-1.7.12.1
-

0031-target-arm-convert-void-helpers.patch

@@ -176,6 +176,3 @@ index edef79a..6f651d9 100644
              break;
          case DISAS_SWI:
              gen_exception(EXCP_SWI);
--- 
-1.7.12.1
-

0032-target-arm-convert-remaining-helpers.patch

@@ -816,6 +816,3 @@ index 6f651d9..9ae3b26 100644
              rd = 16;
              break;
          case 0xc: /* orr */
--- 
-1.7.12.1
-

0033-target-arm-final-conversion-to-AREG0-free-mode.patch

@@ -174,6 +174,3 @@ index 9ae3b26..f4b447a 100644
      s->pc += 2;
  
      switch (insn >> 12) {
--- 
-1.7.12.1
-

0034-target-microblaze-switch-to-AREG0-free-mode.patch

@@ -710,6 +710,3 @@ index 7470149..9c7d77f 100644
          tcg_temp_free_i32(tmp);
      } else {
          switch(dc->is_jmp) {
--- 
-1.7.12.1
-

0035-target-cris-Avoid-AREG0-for-helpers.patch

@@ -518,6 +518,3 @@ index 3629629..9a39c6a 100644
                             cpu_R[dc->src], cpu_PR[PR_CCS]);
                  break;
              case CRISV10_REG_DSTEP:
--- 
-1.7.12.1
-

0036-target-cris-Switch-to-AREG0-free-mode.patch

@@ -1533,6 +1533,3 @@ index 9a39c6a..d2cca89 100644
              break;
      }
  
--- 
-1.7.12.1
-

0037-target-sh4-switch-to-AREG0-free-mode.patch

@@ -1055,6 +1055,3 @@ index 6532ad2..d05c74c 100644
      } else {
  	switch (ctx.bstate) {
          case BS_STOP:
--- 
-1.7.12.1
-

0038-target-mips-switch-to-AREG0-free-mode.patch

@@ -6331,6 +6331,3 @@ index b293419..7ab769f 100644
      } else {
          switch (ctx.bstate) {
          case BS_STOP:
--- 
-1.7.12.1
-

0039-Remove-unused-CONFIG_TCG_PASS_AREG0-and-dead-code.patch

@@ -1678,6 +1678,3 @@ index b9ea9dd..ef9b172 100644
  #if defined(DEBUG_SIGNAL)
      qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
                  pc, address, is_write, *(unsigned long *)old_set);
--- 
-1.7.12.1
-

0040-tcg-i386-allow-constants-in-load-store-ops.patch

@@ -109,6 +109,3 @@ index 34c2df8..3017858 100644
  
      { INDEX_op_add_i64, { "r", "0", "re" } },
      { INDEX_op_mul_i64, { "r", "0", "re" } },
--- 
-1.7.12.1
-

0041-tcg-mark-set_label-with-TCG_OPF_BB_END-flag.patch

@@ -48,6 +48,3 @@ index 8386b70..c002a88 100644
          case INDEX_op_debug_insn_start:
              args -= def->nb_args;
              break;
--- 
-1.7.12.1
-

0042-revert-TCG-fix-copy-propagation.patch

@@ -80,6 +80,3 @@ index d710694..8fbbc81 100644
  #if defined(CONFIG_DEBUG_TCG)
  /* If you call tcg_clear_temp_count() at the start of a section of
   * code which is not supposed to leak any TCG temporaries, then
--- 
-1.7.12.1
-

0043-target-mips-Set-opn-in-gen_ldst_multiple.patch

@@ -50,6 +50,3 @@ index 7ab769f..c31f91c 100644
      MIPS_DEBUG("%s, %x, %d(%s)", opn, reglist, offset, regnames[base]);
      tcg_temp_free(t0);
      tcg_temp_free(t1);
--- 
-1.7.12.1
-

0044-target-mips-Fix-MIPS_DEBUG.patch

@@ -283,6 +283,3 @@ index c31f91c..4937f6b 100644
           break;
      case OPC_J ... OPC_JAL: /* Jump */
           offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
--- 
-1.7.12.1
-

0045-target-mips-Always-evaluate-debugging-macro-argument.patch

@@ -65,6 +65,3 @@ index 4937f6b..aba7935 100644
  
  /* General purpose registers moves. */
  static inline void gen_load_gpr (TCGv t, int reg)
--- 
-1.7.12.1
-

0046-tcg-optimize-fix-end-of-basic-block-detection.patch

@@ -57,6 +57,3 @@ index 10d9773..9da333c 100644
              }
              for (i = 0; i < def->nb_args; i++) {
                  gen_args[i] = args[i];
--- 
-1.7.12.1
-

0047-target-xtensa-fix-extui-shift-amount.patch

@@ -52,6 +52,3 @@ index 1900bd5..7a1c528 100644
                  tcg_temp_free(tmp);
              }
              break;
--- 
-1.7.12.1
-

0048-target-xtensa-don-t-emit-extra-tcg_gen_goto_tb.patch

@@ -30,6 +30,3 @@ index 7a1c528..b6643eb 100644
      dc->pc = dc->next_pc;
  
      return;
--- 
-1.7.12.1
-

0049-tcg-Introduce-movcond.patch

@@ -328,6 +328,3 @@ index 30a0f21..6d89495 100644
  #endif /* TCG_TARGET_REG_BITS == 64 */
  
  /* Offset to user memory in user mode. */
--- 
-1.7.12.1
-

0050-target-alpha-Use-movcond.patch

@@ -155,6 +155,3 @@ index 12de6a3..4a9011a 100644
  }
  
  #define QUAL_RM_N       0x080   /* Round mode nearest even */
--- 
-1.7.12.1
-

0051-tcg-i386-Implement-movcond.patch

@@ -113,6 +113,3 @@ index 504f953..b356d76 100644
  #endif
  
  #define TCG_TARGET_deposit_i32_valid(ofs, len) \
--- 
-1.7.12.1
-

0052-tcg-Optimize-movcond-for-constant-comparisons.patch

@@ -68,6 +68,3 @@ index 9da333c..26038a6 100644
          case INDEX_op_call:
              nb_call_args = (args[0] >> 16) + (args[0] & 0xffff);
              if (!(args[nb_call_args + 1] & (TCG_CALL_CONST | TCG_CALL_PURE))) {
--- 
-1.7.12.1
-

0053-tcg-Optimize-two-address-commutative-operations.patch

@@ -52,6 +52,3 @@ index 26038a6..1be7631 100644
          default:
              break;
          }
--- 
-1.7.12.1
-

0054-gdbstub-sh4-fix-build-with-USE_SOFTFLOAT_STRUCT_TYPE.patch

@@ -187,6 +187,3 @@ index 5d37dd9..a91709f 100644
      default: return 0;
      }
  
--- 
-1.7.12.1
-

0055-tcg-Fix-USE_DIRECT_JUMP.patch

@@ -30,6 +30,3 @@ index f454107..609ed86 100644
      uint16_t *tb_next_offset;
      uint16_t *tb_jmp_offset; /* != NULL if USE_DIRECT_JUMP */
  
--- 
-1.7.12.1
-

0056-tcg-hppa-Fix-brcond2-and-setcond2.patch

@@ -103,6 +103,3 @@ index 8b81b70..a76569d 100644
      }
  
      tcg_out_mov(s, TCG_TYPE_I32, ret, scratch);
--- 
-1.7.12.1
-

0057-tcg-hppa-Fix-broken-load-store-helpers.patch

@@ -244,6 +244,3 @@ index a76569d..5385d45 100644
          addrlo_reg = TCG_REG_R31;
      }
      tcg_out_qemu_st_direct(s, datalo_reg, datahi_reg, addrlo_reg, opc);
--- 
-1.7.12.1
-

0058-tcg-mips-fix-wrong-usage-of-Z-constraint.patch

@@ -60,6 +60,3 @@ index 74db83d..9293745 100644
      { INDEX_op_brcond2_i32, { "rZ", "rZ", "rZ", "rZ" } },
  
  #if TARGET_LONG_BITS == 32
--- 
-1.7.12.1
-

0059-tcg-mips-kill-warnings-in-user-mode.patch

@@ -161,6 +161,3 @@ index 9293745..a09c0d6 100644
  
  #if defined(CONFIG_SOFTMMU)
      tcg_out_opc_sa(s, OPC_SRL, TCG_REG_A0, addr_regl, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
--- 
-1.7.12.1
-

0060-tcg-mips-use-TCGArg-or-TCGReg-instead-of-int.patch

@@ -241,6 +241,3 @@ index a09c0d6..8b38f98 100644
  # endif
  #endif
      data_regl = *args++;
--- 
-1.7.12.1
-

0061-tcg-mips-don-t-use-global-pointer.patch

@@ -32,6 +32,3 @@ index 8b38f98..0ea6a76 100644
  
      tcg_add_target_add_op_defs(mips_op_defs);
      tcg_set_frame(s, TCG_AREG0, offsetof(CPUArchState, temp_buf),
--- 
-1.7.12.1
-

0062-tcg-mips-use-stack-for-TCG-temps.patch

@@ -42,6 +42,3 @@ index 0ea6a76..c05169f 100644
 -    tcg_set_frame(s, TCG_AREG0, offsetof(CPUArchState, temp_buf),
 -                  CPU_TEMP_BUF_NLONGS * sizeof(long));
  }
--- 
-1.7.12.1
-

0063-tcg-mips-optimize-brcond-arg-0.patch

@@ -94,6 +94,3 @@ index c05169f..6aa4527 100644
          break;
      case TCG_COND_GTU:
          tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, arg2, arg1);
--- 
-1.7.12.1
-

0064-tcg-mips-optimize-bswap-16-16s-32-on-MIPS32R2.patch

@@ -156,6 +156,3 @@ index 9c68a32..c5c13f7 100644
  /* optional instructions automatically implemented */
  #define TCG_TARGET_HAS_neg_i32          0 /* sub  rd, zero, rt   */
  #define TCG_TARGET_HAS_ext8u_i32        0 /* andi rt, rs, 0xff   */
--- 
-1.7.12.1
-

0065-tcg-mips-implement-rotl-rotr-ops-on-MIPS32R2.patch

@@ -87,6 +87,3 @@ index c5c13f7..470314c 100644
  #endif
  
  /* optional instructions automatically implemented */
--- 
-1.7.12.1
-

0066-tcg-mips-implement-deposit-op-on-MIPS32R2.patch

@@ -72,6 +72,3 @@ index 470314c..897a737 100644
  #endif
  
  /* optional instructions automatically implemented */
--- 
-1.7.12.1
-

0067-tcg-mips-implement-movcond-op-on-MIPS32R2.patch

@@ -135,6 +135,3 @@ index 897a737..d147e70 100644
  
  /* optional instructions only implemented on MIPS32R2 */
  #ifdef _MIPS_ARCH_MIPS32R2
--- 
-1.7.12.1
-

0068-tcg-optimize-remove-TCG_TEMP_ANY.patch

@@ -57,6 +57,3 @@ index 1be7631..308b7f9 100644
      }
  }
  
--- 
-1.7.12.1
-

0069-tcg-optimize-check-types-in-copy-propagation.patch

@@ -73,6 +73,3 @@ index 308b7f9..da8dffe 100644
                  gen_args += 2;
                  args += 2;
                  break;
--- 
-1.7.12.1
-

0070-tcg-optimize-rework-copy-progagation.patch

@@ -372,6 +372,3 @@ index da8dffe..1904b39 100644
                  }
              }
              for (i = 0; i < def->nb_args; i++) {
--- 
-1.7.12.1
-

0071-tcg-optimize-do-copy-propagation-for-all-operations.patch

@@ -37,6 +37,3 @@ index 1904b39..aeb2225 100644
              for (i = def->nb_oargs; i < def->nb_oargs + def->nb_iargs; i++) {
                  if (temps[args[i]].state == TCG_TEMP_COPY) {
                      args[i] = find_better_copy(s, args[i]);
--- 
-1.7.12.1
-

0072-tcg-optimize-optimize-op-r-a-a-mov-r-a.patch

@@ -26,6 +26,3 @@ index aeb2225..b9a7da9 100644
                  if (temps_are_copies(args[0], args[1])) {
                      gen_opc_buf[op_index] = INDEX_op_nop;
                  } else {
--- 
-1.7.12.1
-

0073-tcg-optimize-optimize-op-r-a-a-movi-r-0.patch

@@ -41,6 +41,3 @@ index b9a7da9..ceea644 100644
          /* Propagate constants through copy operations and do constant
             folding.  Constants will be substituted to arguments by register
             allocator where needed and possible.  Also detect copies. */
--- 
-1.7.12.1
-

0074-tcg-optimize-further-optimize-brcond-movcond-setcond.patch

@@ -187,6 +187,3 @@ index ceea644..abe016a 100644
                  if (temps_are_copies(args[0], args[4-tmp])) {
                      gen_opc_buf[op_index] = INDEX_op_nop;
                  } else if (temps[args[4-tmp]].state == TCG_TEMP_CONST) {
--- 
-1.7.12.1
-

0075-tcg-optimize-prefer-the-op-a-a-b-form-for-commutativ.patch

@@ -33,6 +33,3 @@ index abe016a..c8ae50b 100644
                  tmp = args[1];
                  args[1] = args[2];
                  args[2] = tmp;
--- 
-1.7.12.1
-

0076-tcg-remove-ifdef-endif-around-TCGOpcode-tests.patch

@@ -63,6 +63,3 @@ index 24ce830..93421cd 100644
              tcg_reg_alloc_movi(s, args);
              break;
          case INDEX_op_debug_insn_start:
--- 
-1.7.12.1
-

0077-tcg-optimize-add-constant-folding-for-deposit.patch

@@ -41,6 +41,3 @@ index c8ae50b..35532a1 100644
          CASE_OP_32_64(setcond):
              tmp = do_constant_folding_cond(op, args[1], args[2], args[3]);
              if (tmp != 2) {
--- 
-1.7.12.1
-

0078-tcg-README-document-tcg_gen_goto_tb-restrictions.patch

@@ -28,6 +28,3 @@ index d03ae05..33783ee 100644
  
  * qemu_ld8u t0, t1, flags
  qemu_ld8s t0, t1, flags
--- 
-1.7.12.1
-

0079-w64-Fix-TCG-helper-functions-with-5-arguments.patch

@@ -52,6 +52,3 @@ index b356d76..ace63ba 100644
  
  /* optional instructions */
  #define TCG_TARGET_HAS_div2_i32         1
--- 
-1.7.12.1
-

0080-tcg-ppc32-Implement-movcond32.patch

@@ -132,6 +132,3 @@ index 177eea1..3259d89 100644
  
  #define TCG_AREG0 TCG_REG_R27
  
--- 
-1.7.12.1
-

0081-tcg-sparc-Hack-in-qemu_ld-st64-for-32-bit.patch

@@ -25,6 +25,3 @@ index baed3b4..608fc46 100644
  #endif
      { -1 },
  };
--- 
-1.7.12.1
-

0082-tcg-sparc-Fix-ADDX-opcode.patch

@@ -22,6 +22,3 @@ index 608fc46..0a19313 100644
  #define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c))
  #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
  #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
--- 
-1.7.12.1
-

0083-tcg-sparc-Don-t-MAP_FIXED-on-top-of-the-program.patch

@@ -40,6 +40,3 @@ index 5834766..871a68a 100644
          if (code_gen_buffer_size > (512 * 1024 * 1024)) {
              code_gen_buffer_size = (512 * 1024 * 1024);
          }
--- 
-1.7.12.1
-

0084-tcg-sparc-Assume-v9-cpu-always-i.e.-force-v8plus-in-.patch

@@ -281,6 +281,3 @@ index 93421cd..16c4e1d 100644
      s->current_frame_offset = (s->current_frame_offset +
                                 (tcg_target_long)sizeof(tcg_target_long) - 1) &
          ~(sizeof(tcg_target_long) - 1);
--- 
-1.7.12.1
-

0085-tcg-sparc-Fix-qemu_ld-st-to-handle-32-bit-host.patch

@@ -962,6 +962,3 @@ index 23c2fda..d89c19b 100644
      { -1 },
  };
  
--- 
-1.7.12.1
-

0086-tcg-sparc-Support-GUEST_BASE.patch

@@ -108,6 +108,3 @@ index adca1d2..99e9f57 100644
  #ifdef CONFIG_SOLARIS
  #define TCG_AREG0 TCG_REG_G2
  #elif HOST_LONG_BITS == 64
--- 
-1.7.12.1
-

0087-tcg-sparc-Change-AREG0-in-generated-code-to-i0.patch

@@ -46,6 +46,3 @@ index 99e9f57..ee154d0 100644
  
  static inline void flush_icache_range(tcg_target_ulong start,
                                        tcg_target_ulong stop)
--- 
-1.7.12.1
-

0088-tcg-sparc-Clean-up-cruft-stemming-from-attempts-to-u.patch

@@ -198,6 +198,3 @@ index ee154d0..6314ffb 100644
  #endif
  
  #if TCG_TARGET_REG_BITS == 64
--- 
-1.7.12.1
-

0089-tcg-sparc-Mask-shift-immediates-to-avoid-illegal-ins.patch

@@ -57,6 +57,3 @@ index e625aa3..be5c170 100644
      case INDEX_op_mul_i64:
          c = ARITH_MULX;
          goto gen_arith;
--- 
-1.7.12.1
-

0090-tcg-sparc-Use-defines-for-temporaries.patch

@@ -270,6 +270,3 @@ index be5c170..d401f8e 100644
      tcg_add_target_add_op_defs(sparc_op_defs);
  }
  
--- 
-1.7.12.1
-

0091-tcg-sparc-Add-g-o-registers-to-alloc_order.patch

@@ -39,6 +39,3 @@ index d401f8e..03c385a 100644
  };
  
  static const int tcg_target_call_iarg_regs[6] = {
--- 
-1.7.12.1
-

0092-tcg-sparc-Fix-and-enable-direct-TB-chaining.patch

@@ -74,6 +74,3 @@ index 03c385a..1db0c9d 100644
 +    *ptr = CALL | (disp & 0x3fffffff);
 +    flush_icache_range(jmp_addr, jmp_addr + 4);
 +}
--- 
-1.7.12.1
-

0093-tcg-sparc-Preserve-branch-destinations-during-retran.patch

@@ -55,6 +55,3 @@ index 1db0c9d..876da4f 100644
  }
  #endif
  
--- 
-1.7.12.1
-

0094-target-alpha-Initialize-env-cpu_model_str.patch

@@ -28,6 +28,3 @@ index 4a9011a..3f9aee1 100644
  
      qemu_init_vcpu(env);
      return env;
--- 
-1.7.12.1
-

0095-tcg-mips-fix-MIPS32-R2-detection.patch

@@ -88,6 +88,3 @@ index d147e70..7020d65 100644
  #define TCG_TARGET_HAS_bswap16_i32      1
  #define TCG_TARGET_HAS_bswap32_i32      1
  #define TCG_TARGET_HAS_rot_i32          1
--- 
-1.7.12.1
-

0096-tcg-Adjust-descriptions-of-cond-opcodes.patch

@@ -62,6 +62,3 @@ index 33783ee..27846f1 100644
  
  Similar to setcond, except that the 64-bit values T1 and T2 are
  formed from two 32-bit arguments.  The result is a 32-bit value.
--- 
-1.7.12.1
-

0097-tcg-i386-fix-build-with-march-i686.patch

@@ -29,6 +29,3 @@ index 85c6b81..616ef23 100644
  
  #if TCG_TARGET_REG_BITS == 32
      { INDEX_op_mulu2_i32, { "a", "d", "a", "r" } },
--- 
-1.7.12.1
-

0098-tcg-Fix-MAX_OPC_PARAM_IARGS.patch

@@ -47,6 +47,3 @@ index 1f81da7..6516da0 100644
  #define MAX_OPC_PARAM_OARGS 1
  #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
  
--- 
-1.7.12.1
-

0099-tci-Fix-for-AREG0-free-mode.patch

@@ -114,6 +114,3 @@ index ce8a988..a4f7b78 100644
              tci_write_reg(TCG_REG_R0, tmp64);
  #endif
              break;
--- 
-1.7.12.1
-

0100-spice-abort-on-invalid-streaming-cmdline-params.patch

@@ -36,6 +36,3 @@ index 4fc48f8..bb4f585 100644
  
  static const char *compression_names[] = {
      [ SPICE_IMAGE_COMPRESS_OFF ]      = "off",
--- 
-1.7.12.1
-