Fix build with latest dtc (bz #1003187 )

Fix initial /dev/kvm permissions (bz #993491)
Don't install conflicting binfmt handler on arm (bz #974804 )
2013-09-03 15:03:25 -04:00 · 2013-06-19 10:29:10 -04:00 · 2013-06-11 15:45:31 -04:00 · 2013-04-20 20:14:03 -04:00 · 2013-04-08 23:42:51 +02:00 · 2013-04-03 11:29:31 +02:00
388 changed files with 5567 additions and 2175 deletions
--- a/0001-target-xtensa-convert-host-errno-values-to-guest.patch
+++ b/0001-target-xtensa-convert-host-errno-values-to-guest.patch
@ -1,4 +1,4 @@
-From 707f294ca28977968fb85bf36f10c6b37b16f557 Mon Sep 17 00:00:00 2001
+From 638f396d14fbd84884e17333838f3515bbb9a789 Mon Sep 17 00:00:00 2001
 From: Max Filippov <jcmvbkbc@gmail.com>
 Date: Wed, 29 Aug 2012 23:54:25 +0400
 Subject: [PATCH] target-xtensa: convert host errno values to guest
@ -178,6 +178,3 @@ index 6d001c2..e745bef 100644
         break;
     }
 }
-- 
-1.7.12.1
-
--- a/0002-target-cris-Fix-buffer-overflow.patch
+++ b/0002-target-cris-Fix-buffer-overflow.patch
@ -1,4 +1,4 @@
-From 8057ac10e8cba3acb89c11c94f04967306e55a9f Mon Sep 17 00:00:00 2001
+From 787514a7c1b9a3a23eebe70c76d76ed4e45031c3 Mon Sep 17 00:00:00 2001
 From: Stefan Weil <sw@weilnetz.de>
 Date: Fri, 7 Sep 2012 22:36:08 +0200
 Subject: [PATCH] target-cris: Fix buffer overflow
@ -30,6 +30,3 @@ index 1ad9ec7..ad31877 100644
 		for (i = 0; i < 16; i++) {
 			cpu_fprintf(f, "s%2.2d=%8.8x ",
 				    i, env->sregs[srs][i]);
-- 
-1.7.12.1
-
--- a/0003-target-xtensa-fix-missing-errno-codes-for-mingw32.patch
+++ b/0003-target-xtensa-fix-missing-errno-codes-for-mingw32.patch
@ -1,4 +1,4 @@
-From 33e25a4a6c6dc7632b15ee50637d33b4c3cf729e Mon Sep 17 00:00:00 2001
+From 86eaada772e86d7049155ef84385b9e553c40dc4 Mon Sep 17 00:00:00 2001
 From: Max Filippov <jcmvbkbc@gmail.com>
 Date: Thu, 6 Sep 2012 04:36:46 +0400
 Subject: [PATCH] target-xtensa: fix missing errno codes for mingw32
@ -59,6 +59,3 @@ index e745bef..52be07a 100644
     };
 
     if (host_errno == 0) {
-- 
-1.7.12.1
-
--- a/0004-target-sparc-fix-fcmp-s-d-q-instructions-wrt-excepti.patch
+++ b/0004-target-sparc-fix-fcmp-s-d-q-instructions-wrt-excepti.patch
@ -1,4 +1,4 @@
-From 5e955b895d4a92cdc49c7b4e76284483d49aa4b8 Mon Sep 17 00:00:00 2001
+From 304944bc4ff1b2d30d605d7af9d44286e0b17116 Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Fri, 7 Sep 2012 17:13:28 +0200
 Subject: [PATCH] target-sparc: fix fcmp{s,d,q} instructions wrt exception
@ -128,6 +128,3 @@ index 9c64ef8..f4b62a5 100644
             env->fsr |= FSR_FCC1 << FS;                                 \
             break;                                                      \
         default:                                                        \
-- 
-1.7.12.1
-
--- a/0005-target-s390x-fix-style.patch
+++ b/0005-target-s390x-fix-style.patch
@ -1,4 +1,4 @@
-From 985b8342244b5f76ed1df75eb8757d6feff30316 Mon Sep 17 00:00:00 2001
+From 35ea87c77d34e73fd685d5ba43b4de0d1c7456a1 Mon Sep 17 00:00:00 2001
 From: Blue Swirl <blauwirbel@gmail.com>
 Date: Sun, 2 Sep 2012 07:33:30 +0000
 Subject: [PATCH] target-s390x: fix style
@ -1598,6 +1598,3 @@ index abc35dd..195e93e 100644
     } else {
         env->regs[r1] = ret;
     }
-- 
-1.7.12.1
-
--- a/0006-target-s390x-split-FPU-ops.patch
+++ b/0006-target-s390x-split-FPU-ops.patch
@ -1,4 +1,4 @@
-From 3eb9b25ae5d2bcc024646c5a04f28899661ab14c Mon Sep 17 00:00:00 2001
+From d11cb977c11d498c9ee1db3192b9d8ec0227d591 Mon Sep 17 00:00:00 2001
 From: Blue Swirl <blauwirbel@gmail.com>
 Date: Sun, 2 Sep 2012 07:33:31 +0000
 Subject: [PATCH] target-s390x: split FPU ops
@ -1751,6 +1751,3 @@ index 1c1baf5..c370df3 100644
         tcg_temp_free_i32(tmp32);
         break;
     case 0xd: /* DEB    R1,D2(X2,B2)       [RXE] */
-- 
-1.7.12.1
-
--- a/0007-target-s390x-split-condition-code-helpers.patch
+++ b/0007-target-s390x-split-condition-code-helpers.patch
@ -1,4 +1,4 @@
-From f642126aece222f6ff87d26c29f00e1b6c47e10a Mon Sep 17 00:00:00 2001
+From 371c834f34f4cfc0a1678b76de26625bff459f41 Mon Sep 17 00:00:00 2001
 From: Blue Swirl <blauwirbel@gmail.com>
 Date: Sun, 2 Sep 2012 07:33:32 +0000
 Subject: [PATCH] target-s390x: split condition code helpers
@ -1153,6 +1153,3 @@ index 270bf14..eced890 100644
 /* invalidate pte */
 void HELPER(ipte)(uint64_t pte_addr, uint64_t vaddr)
 {
-- 
-1.7.12.1
-
--- a/0008-target-s390x-split-integer-helpers.patch
+++ b/0008-target-s390x-split-integer-helpers.patch
@ -1,4 +1,4 @@
-From e9f67c1f326a995ff0000a08a223435386867d8f Mon Sep 17 00:00:00 2001
+From 3c9b728bd92f8f11ab694705ce2a0782d476dcbc Mon Sep 17 00:00:00 2001
 From: Blue Swirl <blauwirbel@gmail.com>
 Date: Sun, 2 Sep 2012 07:33:33 +0000
 Subject: [PATCH] target-s390x: split integer helpers
@ -439,6 +439,3 @@ index eced890..3b8b997 100644
 void HELPER(unpk)(uint32_t len, uint64_t dest, uint64_t src)
 {
     int len_dest = len >> 4;
-- 
-1.7.12.1
-
--- a/0009-target-s390x-split-memory-access-helpers.patch
+++ b/0009-target-s390x-split-memory-access-helpers.patch
@ -1,4 +1,4 @@
-From a44aee2570031bfcf99098d278c53ab39a582ba6 Mon Sep 17 00:00:00 2001
+From 2704a6f7a5a307d3ad68c0d731810c7252018f73 Mon Sep 17 00:00:00 2001
 From: Blue Swirl <blauwirbel@gmail.com>
 Date: Sun, 2 Sep 2012 07:33:34 +0000
 Subject: [PATCH] target-s390x: split memory access helpers
@ -2419,6 +2419,3 @@ index 3b8b997..bb8dbf5 100644
 -}
 -
 #endif
-- 
-1.7.12.1
-
--- a/0010-target-s390x-rename-op_helper.c-to-misc_helper.c.patch
+++ b/0010-target-s390x-rename-op_helper.c-to-misc_helper.c.patch
@ -1,4 +1,4 @@
-From 56018228deac6e704a7ec8befd9e9dc69f2fe73f Mon Sep 17 00:00:00 2001
+From fccbde6caa50942bad6442529d00b894dd3fa6e6 Mon Sep 17 00:00:00 2001
 From: Blue Swirl <blauwirbel@gmail.com>
 Date: Sun, 2 Sep 2012 07:33:35 +0000
 Subject: [PATCH] target-s390x: rename op_helper.c to misc_helper.c
@ -919,6 +919,3 @@ index bb8dbf5..0000000
 -    return cc;
 -}
 -#endif
-- 
-1.7.12.1
-
--- a/0011-target-s390x-avoid-AREG0-for-FPU-helpers.patch
+++ b/0011-target-s390x-avoid-AREG0-for-FPU-helpers.patch
@ -1,4 +1,4 @@
-From 5d38110b1e23c963302f13f5917001a9298445a7 Mon Sep 17 00:00:00 2001
+From a1b159fae48cf3b5c021160d28e66f37043be2c9 Mon Sep 17 00:00:00 2001
 From: Blue Swirl <blauwirbel@gmail.com>
 Date: Sun, 2 Sep 2012 07:33:36 +0000
 Subject: [PATCH] target-s390x: avoid AREG0 for FPU helpers
@ -1213,6 +1213,3 @@ index c370df3..b1f2071 100644
         set_cc_static(s);
         tcg_temp_free_i32(tmp32_1);
         tcg_temp_free_i32(tmp32_2);
-- 
-1.7.12.1
-
--- a/0012-target-s390x-avoid-AREG0-for-integer-helpers.patch
+++ b/0012-target-s390x-avoid-AREG0-for-integer-helpers.patch
@ -1,4 +1,4 @@
-From d44b8c2cacaa50e7420f0dfaf42c344bcf134431 Mon Sep 17 00:00:00 2001
+From b81c73d5f5fcf2ed6446ecf887351fa60129359b Mon Sep 17 00:00:00 2001
 From: Blue Swirl <blauwirbel@gmail.com>
 Date: Sun, 2 Sep 2012 07:33:37 +0000
 Subject: [PATCH] target-s390x: avoid AREG0 for integer helpers
@ -197,6 +197,3 @@ index b1f2071..2a61e92 100644
         set_cc_static(s);
         tcg_temp_free_i32(tmp32_1);
         tcg_temp_free_i32(tmp32_2);
-- 
-1.7.12.1
-
--- a/0013-target-s390x-avoid-AREG0-for-condition-code-helpers.patch
+++ b/0013-target-s390x-avoid-AREG0-for-condition-code-helpers.patch
@ -1,4 +1,4 @@
-From ead7a100e907eddd0ba9f3cebb5f84c1afb120b8 Mon Sep 17 00:00:00 2001
+From 569db8db7081ba480e60b5fc55f457793959e4f5 Mon Sep 17 00:00:00 2001
 From: Blue Swirl <blauwirbel@gmail.com>
 Date: Sun, 2 Sep 2012 07:33:38 +0000
 Subject: [PATCH] target-s390x: avoid AREG0 for condition code helpers
@ -185,6 +185,3 @@ index 2a61e92..1d87272 100644
         tcg_temp_free_i64(tmp);
         tcg_temp_free_i64(tmp2);
         tcg_temp_free_i64(tmp3);
-- 
-1.7.12.1
-
--- a/0014-target-s390x-avoid-AREG0-for-misc-helpers.patch
+++ b/0014-target-s390x-avoid-AREG0-for-misc-helpers.patch
@ -1,4 +1,4 @@
-From 208547c7afbe6ee8a9a1f81095e67a6cbe4a37ec Mon Sep 17 00:00:00 2001
+From f3b32fc553bc248c4c33716c568445e7be8c5afe Mon Sep 17 00:00:00 2001
 From: Blue Swirl <blauwirbel@gmail.com>
 Date: Sun, 2 Sep 2012 07:33:39 +0000
 Subject: [PATCH] target-s390x: avoid AREG0 for misc helpers
@ -406,6 +406,3 @@ index 1d87272..0c61e63 100644
         set_cc_static(s);
         tcg_temp_free_i64(tmp);
         tcg_temp_free_i64(tmp2);
-- 
-1.7.12.1
-
--- a/0015-target-s390x-switch-to-AREG0-free-mode.patch
+++ b/0015-target-s390x-switch-to-AREG0-free-mode.patch
@ -1,4 +1,4 @@
-From 77fb132a1dc3780a57d8a1e889b366f0492963a5 Mon Sep 17 00:00:00 2001
+From a43797bb116b4945100bc95897afc91c79bcaf5a Mon Sep 17 00:00:00 2001
 From: Blue Swirl <blauwirbel@gmail.com>
 Date: Sun, 2 Sep 2012 07:33:40 +0000
 Subject: [PATCH] target-s390x: switch to AREG0 free mode
@ -1579,6 +1579,3 @@ index 0c61e63..66119cd 100644
         }
         set_cc_static(s);
         tcg_temp_free_i64(tmp);
-- 
-1.7.12.1
-
--- a/0016-tcg-s390-fix-ld-st-with-CONFIG_TCG_PASS_AREG0.patch
+++ b/0016-tcg-s390-fix-ld-st-with-CONFIG_TCG_PASS_AREG0.patch
@ -1,4 +1,4 @@
-From 0b95df52ecad351c916108e9f3a9d1bc3327b495 Mon Sep 17 00:00:00 2001
+From a520e49d09447cc6dbf5925d3e0d1c0fad304b07 Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Sat, 8 Sep 2012 03:45:43 +0000
 Subject: [PATCH] tcg/s390: fix ld/st with CONFIG_TCG_PASS_AREG0
@ -59,6 +59,3 @@ index 04662c1..99b5339 100644
                     TCG_AREG0);
 #endif
         tgen_calli(s, (tcg_target_ulong)qemu_ld_helpers[s_bits]);
-- 
-1.7.12.1
-
--- a/0017-target-arm-Fix-potential-buffer-overflow.patch
+++ b/0017-target-arm-Fix-potential-buffer-overflow.patch
@ -1,4 +1,4 @@
-From e7c3f6b4365f3162f8e25d58f76410aca28719a2 Mon Sep 17 00:00:00 2001
+From d3bcdbc63927557fa949194b0a977873794b701b Mon Sep 17 00:00:00 2001
 From: Stefan Weil <sw@weilnetz.de>
 Date: Tue, 4 Sep 2012 07:35:57 +0200
 Subject: [PATCH] target-arm: Fix potential buffer overflow
@ -42,6 +42,3 @@ index dceaa95..e27df96 100644
         return EXCP_UDEF;
     }
     env->cp15.c6_region[ri->crm] = value;
-- 
-1.7.12.1
-
--- a/0018-tcg-optimize-split-expression-simplification.patch
+++ b/0018-tcg-optimize-split-expression-simplification.patch
@ -1,4 +1,4 @@
-From 16f29b266435c7eaffc5081c6bba4651d56a8ce8 Mon Sep 17 00:00:00 2001
+From 57b9c229c5347d305018d79ef00bbb6b13f83741 Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Thu, 6 Sep 2012 16:47:13 +0200
 Subject: [PATCH] tcg/optimize: split expression simplification
@ -52,6 +52,3 @@ index 9c65474..63f970d 100644
         CASE_OP_32_64(or):
         CASE_OP_32_64(and):
             if (args[1] == args[2]) {
-- 
-1.7.12.1
-
--- a/0019-tcg-optimize-simplify-or-xor-r-a-0-cases.patch
+++ b/0019-tcg-optimize-simplify-or-xor-r-a-0-cases.patch
@ -1,4 +1,4 @@
-From f69f9bd1a7a095ee153eea5422651780aef178b0 Mon Sep 17 00:00:00 2001
+From fe3f54361dd26369e5efb5c6f41d7fc2a817af22 Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Thu, 6 Sep 2012 16:47:14 +0200
 Subject: [PATCH] tcg/optimize: simplify or/xor r, a, 0 cases
@ -25,6 +25,3 @@ index 63f970d..0db849e 100644
             if (temps[args[1]].state == TCG_TEMP_CONST) {
                 /* Proceed with possible constant folding. */
                 break;
-- 
-1.7.12.1
-
--- a/0020-tcg-optimize-simplify-and-r-a-0-cases.patch
+++ b/0020-tcg-optimize-simplify-and-r-a-0-cases.patch
@ -1,4 +1,4 @@
-From f08c59ce7dee67a95cf06d9588b4312e7d071788 Mon Sep 17 00:00:00 2001
+From 36326ed415fa251fb7dd2d8bfec1e02ffc8609f2 Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Thu, 6 Sep 2012 16:47:14 +0200
 Subject: [PATCH] tcg/optimize: simplify and r, a, 0 cases
@ -24,6 +24,3 @@ index 0db849e..c12cb2b 100644
         CASE_OP_32_64(mul):
             if ((temps[args[2]].state == TCG_TEMP_CONST
                 && temps[args[2]].val == 0)) {
-- 
-1.7.12.1
-
--- a/0021-tcg-optimize-simplify-shift-rot-r-0-a-movi-r-0-cases.patch
+++ b/0021-tcg-optimize-simplify-shift-rot-r-0-a-movi-r-0-cases.patch
@ -1,4 +1,4 @@
-From bbed332c7ad12e9885d3f457f366fa0b29445dcd Mon Sep 17 00:00:00 2001
+From 3bb8a381b43404d4cdb535da11cdf7195db3f9b2 Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Thu, 6 Sep 2012 16:47:14 +0200
 Subject: [PATCH] tcg/optimize: simplify shift/rot r, 0, a => movi r, 0 cases
@ -43,6 +43,3 @@ index c12cb2b..1698ba3 100644
         /* Simplify expression for "op r, a, 0 => mov r, a" cases */
         switch (op) {
         CASE_OP_32_64(add):
-- 
-1.7.12.1
-
--- a/0022-tcg-optimize-swap-brcond-setcond-arguments-when-poss.patch
+++ b/0022-tcg-optimize-swap-brcond-setcond-arguments-when-poss.patch
@ -1,4 +1,4 @@
-From 1127ad0d084f0cef11b5658b3dbbf8505d8d3af0 Mon Sep 17 00:00:00 2001
+From 17bc74a53ebc1a49bcd1f556f35eebfd65a64b12 Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Thu, 6 Sep 2012 16:47:14 +0200
 Subject: [PATCH] tcg/optimize: swap brcond/setcond arguments when possible
@ -44,6 +44,3 @@ index 1698ba3..7debc8a 100644
         default:
             break;
         }
-- 
-1.7.12.1
-
--- a/0023-tcg-optimize-add-constant-folding-for-setcond.patch
+++ b/0023-tcg-optimize-add-constant-folding-for-setcond.patch
@ -1,4 +1,4 @@
-From 1bbb9ac3e775b55d0d5c57c209f47e742a9be810 Mon Sep 17 00:00:00 2001
+From 83478c497090698dd1f46c6b5a6425e7ac4d9a6b Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Thu, 6 Sep 2012 16:47:14 +0200
 Subject: [PATCH] tcg/optimize: add constant folding for setcond
@ -109,6 +109,3 @@ index 7debc8a..1cb1f36 100644
         case INDEX_op_call:
             nb_call_args = (args[0] >> 16) + (args[0] & 0xffff);
             if (!(args[nb_call_args + 1] & (TCG_CALL_CONST | TCG_CALL_PURE))) {
-- 
-1.7.12.1
-
--- a/0024-tcg-optimize-add-constant-folding-for-brcond.patch
+++ b/0024-tcg-optimize-add-constant-folding-for-brcond.patch
@ -1,4 +1,4 @@
-From 98dc31743b94d5719c02c589e7cd652e95570b25 Mon Sep 17 00:00:00 2001
+From 4c199af6e9f2bc6242d971ed5d3052be6c18a98c Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Thu, 6 Sep 2012 16:47:14 +0200
 Subject: [PATCH] tcg/optimize: add constant folding for brcond
@ -55,6 +55,3 @@ index 1cb1f36..156e8d9 100644
             memset(temps, 0, nb_temps * sizeof(struct tcg_temp_info));
             for (i = 0; i < def->nb_args; i++) {
                 *gen_args = *args;
-- 
-1.7.12.1
-
--- a/0025-tcg-optimize-fix-if-else-break-coding-style.patch
+++ b/0025-tcg-optimize-fix-if-else-break-coding-style.patch
@ -1,4 +1,4 @@
-From b7dc881b44c3698a0a81d226d6012d3c5833fd29 Mon Sep 17 00:00:00 2001
+From e887688b8e39a2abad0707b080f3282306c1c8bf Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Fri, 7 Sep 2012 12:24:32 +0200
 Subject: [PATCH] tcg/optimize: fix if/else/break coding style
@ -139,6 +139,3 @@ index 156e8d9..fba0ed9 100644
         case INDEX_op_call:
             nb_call_args = (args[0] >> 16) + (args[0] & 0xffff);
             if (!(args[nb_call_args + 1] & (TCG_CALL_CONST | TCG_CALL_PURE))) {
-- 
-1.7.12.1
-
--- a/0026-target-s390x-avoid-cpu_single_env.patch
+++ b/0026-target-s390x-avoid-cpu_single_env.patch
@ -1,4 +1,4 @@
-From d8503917ec9ba86829387f05db7da2eb6fa8123f Mon Sep 17 00:00:00 2001
+From bbe3ec30ffba86f1154ac3c2128aa2b366f0ad44 Mon Sep 17 00:00:00 2001
 From: Blue Swirl <blauwirbel@gmail.com>
 Date: Sat, 8 Sep 2012 11:15:37 +0000
 Subject: [PATCH] target-s390x: avoid cpu_single_env
@ -1332,6 +1332,3 @@ index 66119cd..3214783 100644
 
         num_insns++;
         if (env->singlestep_enabled) {
-- 
-1.7.12.1
-
--- a/0027-target-lm32-switch-to-AREG0-free-mode.patch
+++ b/0027-target-lm32-switch-to-AREG0-free-mode.patch
@ -1,4 +1,4 @@
-From 25e9a95d0571c40738daa479467d757eb477739e Mon Sep 17 00:00:00 2001
+From 8d2c36442129f5b9f2d6f11b296bce31aa7466f0 Mon Sep 17 00:00:00 2001
 From: Blue Swirl <blauwirbel@gmail.com>
 Date: Sun, 2 Sep 2012 06:57:17 +0000
 Subject: [PATCH] target-lm32: switch to AREG0 free mode
@ -277,6 +277,3 @@ index 872a2ba..5f6dcba 100644
         dc->pc += 4;
         num_insns++;
 
-- 
-1.7.12.1
-
--- a/0028-target-m68k-switch-to-AREG0-free-mode.patch
+++ b/0028-target-m68k-switch-to-AREG0-free-mode.patch
@ -1,4 +1,4 @@
-From 2ace9fd11db103aecebf451aff3bc23838248667 Mon Sep 17 00:00:00 2001
+From 6c109ebaaae09fdebadceeb105d37dbd20bd2a31 Mon Sep 17 00:00:00 2001
 From: Blue Swirl <blauwirbel@gmail.com>
 Date: Sun, 2 Sep 2012 07:27:38 +0000
 Subject: [PATCH] target-m68k: switch to AREG0 free mode
@ -497,6 +497,3 @@ index 9fc1e31..10bb303 100644
     } else {
         switch(dc->is_jmp) {
         case DISAS_NEXT:
-- 
-1.7.12.1
-
--- a/0029-target-m68k-avoid-using-cpu_single_env.patch
+++ b/0029-target-m68k-avoid-using-cpu_single_env.patch
@ -1,4 +1,4 @@
-From 5560cd783146734a60c446f43227044cbb580edd Mon Sep 17 00:00:00 2001
+From c6969b702235fabad86d637b0b058da477f660fe Mon Sep 17 00:00:00 2001
 From: Blue Swirl <blauwirbel@gmail.com>
 Date: Sat, 8 Sep 2012 10:48:20 +0000
 Subject: [PATCH] target-m68k: avoid using cpu_single_env
@ -896,6 +896,3 @@ index 10bb303..fb707f2 100644
 }
 
 /* generate intermediate code for basic block 'tb'.  */
-- 
-1.7.12.1
-
--- a/0030-target-unicore32-switch-to-AREG0-free-mode.patch
+++ b/0030-target-unicore32-switch-to-AREG0-free-mode.patch
@ -1,4 +1,4 @@
-From 23ff6fa6a883d210aab33e09d0bb9470df5083fc Mon Sep 17 00:00:00 2001
+From 5968c571f5a53f6d8e20089649071bfebb12583e Mon Sep 17 00:00:00 2001
 From: Blue Swirl <blauwirbel@gmail.com>
 Date: Sun, 2 Sep 2012 07:42:33 +0000
 Subject: [PATCH] target-unicore32: switch to AREG0 free mode
@ -432,6 +432,3 @@ index 188bf8c..b786a6b 100644
     s->pc += 4;
 
     /* UniCore instructions class:
-- 
-1.7.12.1
-
--- a/0031-target-arm-convert-void-helpers.patch
+++ b/0031-target-arm-convert-void-helpers.patch
@ -1,4 +1,4 @@
-From 140048c58e4ceb4f3bac87d7154d2731bb2bcd5d Mon Sep 17 00:00:00 2001
+From 1a2ac85a3f356719ae7b7577f855ce3eafc33b9a Mon Sep 17 00:00:00 2001
 From: Blue Swirl <blauwirbel@gmail.com>
 Date: Tue, 4 Sep 2012 20:08:34 +0000
 Subject: [PATCH] target-arm: convert void helpers
@ -176,6 +176,3 @@ index edef79a..6f651d9 100644
             break;
         case DISAS_SWI:
             gen_exception(EXCP_SWI);
-- 
-1.7.12.1
-
--- a/0032-target-arm-convert-remaining-helpers.patch
+++ b/0032-target-arm-convert-remaining-helpers.patch
@ -1,4 +1,4 @@
-From 18e713cf6b5ae2e7c48bb412c959c10322bef5e5 Mon Sep 17 00:00:00 2001
+From 61624377f16e1d69787000fd527c2219dd0ec326 Mon Sep 17 00:00:00 2001
 From: Blue Swirl <blauwirbel@gmail.com>
 Date: Tue, 4 Sep 2012 20:19:15 +0000
 Subject: [PATCH] target-arm: convert remaining helpers
@ -816,6 +816,3 @@ index 6f651d9..9ae3b26 100644
             rd = 16;
             break;
         case 0xc: /* orr */
-- 
-1.7.12.1
-
--- a/0033-target-arm-final-conversion-to-AREG0-free-mode.patch
+++ b/0033-target-arm-final-conversion-to-AREG0-free-mode.patch
@ -1,4 +1,4 @@
-From 28b8f097f9fb107882aa51bd25ba87619beb033e Mon Sep 17 00:00:00 2001
+From 3948c2f4f3ed4758e464380d4c27a0dc9f0cafcd Mon Sep 17 00:00:00 2001
 From: Blue Swirl <blauwirbel@gmail.com>
 Date: Tue, 4 Sep 2012 20:25:59 +0000
 Subject: [PATCH] target-arm: final conversion to AREG0 free mode
@ -174,6 +174,3 @@ index 9ae3b26..f4b447a 100644
     s->pc += 2;
 
     switch (insn >> 12) {
-- 
-1.7.12.1
-
--- a/0034-target-microblaze-switch-to-AREG0-free-mode.patch
+++ b/0034-target-microblaze-switch-to-AREG0-free-mode.patch
@ -1,4 +1,4 @@
-From 449d4f2cfbdd2b5fd00e3e82c78bf580bd81551d Mon Sep 17 00:00:00 2001
+From a28b2838b7797bddd649ebabb54655c893b3369d Mon Sep 17 00:00:00 2001
 From: Blue Swirl <blauwirbel@gmail.com>
 Date: Sun, 2 Sep 2012 08:39:22 +0000
 Subject: [PATCH] target-microblaze: switch to AREG0 free mode
@ -710,6 +710,3 @@ index 7470149..9c7d77f 100644
         tcg_temp_free_i32(tmp);
     } else {
         switch(dc->is_jmp) {
-- 
-1.7.12.1
-
--- a/0035-target-cris-Avoid-AREG0-for-helpers.patch
+++ b/0035-target-cris-Avoid-AREG0-for-helpers.patch
@ -1,4 +1,4 @@
-From 1e3916b0cbfd39cb3fc8996423d5574068583145 Mon Sep 17 00:00:00 2001
+From 90193bff4bc1aaec99135eed2d0d64d1a0c3fb59 Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Thu, 30 Aug 2012 16:56:39 +0200
 Subject: [PATCH] target-cris: Avoid AREG0 for helpers
@ -518,6 +518,3 @@ index 3629629..9a39c6a 100644
                            cpu_R[dc->src], cpu_PR[PR_CCS]);
                 break;
             case CRISV10_REG_DSTEP:
-- 
-1.7.12.1
-
--- a/0036-target-cris-Switch-to-AREG0-free-mode.patch
+++ b/0036-target-cris-Switch-to-AREG0-free-mode.patch
@ -1,4 +1,4 @@
-From 327937b3765d53776e42ffd3990e0b551c98b0e6 Mon Sep 17 00:00:00 2001
+From ea9fdb224e11a377f733c98286a4b4af341f716b Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Fri, 7 Sep 2012 16:13:27 +0200
 Subject: [PATCH] target-cris: Switch to AREG0 free mode
@ -1533,6 +1533,3 @@ index 9a39c6a..d2cca89 100644
             break;
     }
 
-- 
-1.7.12.1
-
--- a/0037-target-sh4-switch-to-AREG0-free-mode.patch
+++ b/0037-target-sh4-switch-to-AREG0-free-mode.patch
@ -1,4 +1,4 @@
-From 22bb4c416286bbfc340f65e5c7f286d96a731cc7 Mon Sep 17 00:00:00 2001
+From 4549596721636b62b8d58c36db7b4488f3f16a0e Mon Sep 17 00:00:00 2001
 From: Blue Swirl <blauwirbel@gmail.com>
 Date: Sun, 2 Sep 2012 10:37:06 +0000
 Subject: [PATCH] target-sh4: switch to AREG0 free mode
@ -1055,6 +1055,3 @@ index 6532ad2..d05c74c 100644
     } else {
 	switch (ctx.bstate) {
         case BS_STOP:
-- 
-1.7.12.1
-
--- a/0038-target-mips-switch-to-AREG0-free-mode.patch
+++ b/0038-target-mips-switch-to-AREG0-free-mode.patch
@ -1,4 +1,4 @@
-From 8ad14b12fbe7555da2b2f0f1f28e07b8a34b686c Mon Sep 17 00:00:00 2001
+From f73f93108dcec69c32f14b6adee56b42b0ca955a Mon Sep 17 00:00:00 2001
 From: Blue Swirl <blauwirbel@gmail.com>
 Date: Sun, 2 Sep 2012 14:52:59 +0000
 Subject: [PATCH] target-mips: switch to AREG0 free mode
@ -6331,6 +6331,3 @@ index b293419..7ab769f 100644
     } else {
         switch (ctx.bstate) {
         case BS_STOP:
-- 
-1.7.12.1
-
--- a/0039-Remove-unused-CONFIG_TCG_PASS_AREG0-and-dead-code.patch
+++ b/0039-Remove-unused-CONFIG_TCG_PASS_AREG0-and-dead-code.patch
@ -1,4 +1,4 @@
-From 3ec8ca067ea6617b5bd4423d0b40c894b39a4924 Mon Sep 17 00:00:00 2001
+From bca0704da7e5430b1a09a956dec8027fe2c2ca95 Mon Sep 17 00:00:00 2001
 From: Blue Swirl <blauwirbel@gmail.com>
 Date: Sun, 2 Sep 2012 15:28:56 +0000
 Subject: [PATCH] Remove unused CONFIG_TCG_PASS_AREG0 and dead code
@ -1678,6 +1678,3 @@ index b9ea9dd..ef9b172 100644
 #if defined(DEBUG_SIGNAL)
     qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
                 pc, address, is_write, *(unsigned long *)old_set);
-- 
-1.7.12.1
-
--- a/0040-tcg-i386-allow-constants-in-load-store-ops.patch
+++ b/0040-tcg-i386-allow-constants-in-load-store-ops.patch
@ -1,4 +1,4 @@
-From 83b25655bcd988054a2bb2a0a38dc662d4901b08 Mon Sep 17 00:00:00 2001
+From 1c8cfef602f6c17a618a6c00f8ac919204e51a97 Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Mon, 10 Sep 2012 13:56:24 +0200
 Subject: [PATCH] tcg/i386: allow constants in load/store ops
@ -109,6 +109,3 @@ index 34c2df8..3017858 100644
 
     { INDEX_op_add_i64, { "r", "0", "re" } },
     { INDEX_op_mul_i64, { "r", "0", "re" } },
-- 
-1.7.12.1
-
--- a/0041-tcg-mark-set_label-with-TCG_OPF_BB_END-flag.patch
+++ b/0041-tcg-mark-set_label-with-TCG_OPF_BB_END-flag.patch
@ -1,4 +1,4 @@
-From 1610a0e56c0be3e4bfd3034e5323188b1d05badd Mon Sep 17 00:00:00 2001
+From 6b755c1518101434d9fe736c8de7df18052111a1 Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Mon, 10 Sep 2012 14:23:49 +0200
 Subject: [PATCH] tcg: mark set_label with TCG_OPF_BB_END flag
@ -48,6 +48,3 @@ index 8386b70..c002a88 100644
         case INDEX_op_debug_insn_start:
             args -= def->nb_args;
             break;
-- 
-1.7.12.1
-
--- a/0042-revert-TCG-fix-copy-propagation.patch
+++ b/0042-revert-TCG-fix-copy-propagation.patch
@ -1,4 +1,4 @@
-From 2b8d0049e88c17749ccb978509d3f8fda180d35f Mon Sep 17 00:00:00 2001
+From 30a6eee8b0018ac7698bcd4e4821b8b8d8498ba1 Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Mon, 10 Sep 2012 13:14:12 +0200
 Subject: [PATCH] revert "TCG: fix copy propagation"
@ -80,6 +80,3 @@ index d710694..8fbbc81 100644
 #if defined(CONFIG_DEBUG_TCG)
 /* If you call tcg_clear_temp_count() at the start of a section of
  * code which is not supposed to leak any TCG temporaries, then
-- 
-1.7.12.1
-
--- a/0043-target-mips-Set-opn-in-gen_ldst_multiple.patch
+++ b/0043-target-mips-Set-opn-in-gen_ldst_multiple.patch
@ -1,4 +1,4 @@
-From 3380afc68a701604e51fa22637ef48d93514d678 Mon Sep 17 00:00:00 2001
+From 74a3fc19bbb2e5f0b398bb6d66d0a6890d543f38 Mon Sep 17 00:00:00 2001
 From: Richard Henderson <rth@twiddle.net>
 Date: Tue, 18 Sep 2012 21:55:32 -0700
 Subject: [PATCH] target-mips: Set opn in gen_ldst_multiple.
@ -50,6 +50,3 @@ index 7ab769f..c31f91c 100644
     MIPS_DEBUG("%s, %x, %d(%s)", opn, reglist, offset, regnames[base]);
     tcg_temp_free(t0);
     tcg_temp_free(t1);
-- 
-1.7.12.1
-
--- a/0044-target-mips-Fix-MIPS_DEBUG.patch
+++ b/0044-target-mips-Fix-MIPS_DEBUG.patch
@ -1,4 +1,4 @@
-From 5dd8e9207a39d8fe41eaa110edfdba5e37064562 Mon Sep 17 00:00:00 2001
+From 804a1aff270166581a300eec416ca618105255d5 Mon Sep 17 00:00:00 2001
 From: Richard Henderson <rth@twiddle.net>
 Date: Tue, 18 Sep 2012 21:55:33 -0700
 Subject: [PATCH] target-mips: Fix MIPS_DEBUG.
@ -283,6 +283,3 @@ index c31f91c..4937f6b 100644
          break;
     case OPC_J ... OPC_JAL: /* Jump */
          offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
-- 
-1.7.12.1
-
--- a/0045-target-mips-Always-evaluate-debugging-macro-argument.patch
+++ b/0045-target-mips-Always-evaluate-debugging-macro-argument.patch
@ -1,4 +1,4 @@
-From e6f923b4e3e71661343f6d2eecd7f102022e5635 Mon Sep 17 00:00:00 2001
+From 889e59c1ba3024b1f27d263366a174797952186b Mon Sep 17 00:00:00 2001
 From: Richard Henderson <rth@twiddle.net>
 Date: Tue, 18 Sep 2012 21:55:34 -0700
 Subject: [PATCH] target-mips: Always evaluate debugging macro arguments
@ -65,6 +65,3 @@ index 4937f6b..aba7935 100644
 
 /* General purpose registers moves. */
 static inline void gen_load_gpr (TCGv t, int reg)
-- 
-1.7.12.1
-
--- a/0046-tcg-optimize-fix-end-of-basic-block-detection.patch
+++ b/0046-tcg-optimize-fix-end-of-basic-block-detection.patch
@ -1,4 +1,4 @@
-From 4ce7a1e0aaecb220016af9b4f390b76f7fffcce8 Mon Sep 17 00:00:00 2001
+From 3066878819419c80c650e8f18aee284c36c6cc6e Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Wed, 19 Sep 2012 21:40:30 +0200
 Subject: [PATCH] tcg/optimize: fix end of basic block detection
@ -57,6 +57,3 @@ index 10d9773..9da333c 100644
             }
             for (i = 0; i < def->nb_args; i++) {
                 gen_args[i] = args[i];
-- 
-1.7.12.1
-
--- a/0047-target-xtensa-fix-extui-shift-amount.patch
+++ b/0047-target-xtensa-fix-extui-shift-amount.patch
@ -1,4 +1,4 @@
-From 1c596a9498830485a1b2f4a4445643a149179b99 Mon Sep 17 00:00:00 2001
+From 7f4b231ccc54dd10dec3722771bf71ce60677b8e Mon Sep 17 00:00:00 2001
 From: Max Filippov <jcmvbkbc@gmail.com>
 Date: Fri, 21 Sep 2012 02:59:49 +0400
 Subject: [PATCH] target-xtensa: fix extui shift amount
@ -52,6 +52,3 @@ index 1900bd5..7a1c528 100644
                 tcg_temp_free(tmp);
             }
             break;
-- 
-1.7.12.1
-
--- a/0048-target-xtensa-don-t-emit-extra-tcg_gen_goto_tb.patch
+++ b/0048-target-xtensa-don-t-emit-extra-tcg_gen_goto_tb.patch
@ -1,4 +1,4 @@
-From ba9c2acb955f0453ae80077a791a4d1c27b5d6e6 Mon Sep 17 00:00:00 2001
+From fc976b44ecc603bfd16a1d03fb17d894a0bf0acd Mon Sep 17 00:00:00 2001
 From: Max Filippov <jcmvbkbc@gmail.com>
 Date: Fri, 21 Sep 2012 02:59:50 +0400
 Subject: [PATCH] target-xtensa: don't emit extra tcg_gen_goto_tb
@ -30,6 +30,3 @@ index 7a1c528..b6643eb 100644
     dc->pc = dc->next_pc;
 
     return;
-- 
-1.7.12.1
-
--- a/0049-tcg-Introduce-movcond.patch
+++ b/0049-tcg-Introduce-movcond.patch
@ -1,4 +1,4 @@
-From a977d2c7f02eb2ed7fc879979d6f5525c017a881 Mon Sep 17 00:00:00 2001
+From 27a9e1f8447f773082825c3f81b4091cf3ffcd3f Mon Sep 17 00:00:00 2001
 From: Richard Henderson <rth@twiddle.net>
 Date: Fri, 21 Sep 2012 10:13:34 -0700
 Subject: [PATCH] tcg: Introduce movcond
@ -328,6 +328,3 @@ index 30a0f21..6d89495 100644
 #endif /* TCG_TARGET_REG_BITS == 64 */
 
 /* Offset to user memory in user mode. */
-- 
-1.7.12.1
-
--- a/0050-target-alpha-Use-movcond.patch
+++ b/0050-target-alpha-Use-movcond.patch
@ -1,4 +1,4 @@
-From 4bf321d3f494134fe2e03c9cbc042e28ec3a1045 Mon Sep 17 00:00:00 2001
+From 014ef59ba637f1013478653a48fc7d0b43545fcc Mon Sep 17 00:00:00 2001
 From: Richard Henderson <rth@twiddle.net>
 Date: Fri, 21 Sep 2012 10:13:35 -0700
 Subject: [PATCH] target-alpha: Use movcond
@ -155,6 +155,3 @@ index 12de6a3..4a9011a 100644
 }
 
 #define QUAL_RM_N       0x080   /* Round mode nearest even */
-- 
-1.7.12.1
-
--- a/0051-tcg-i386-Implement-movcond.patch
+++ b/0051-tcg-i386-Implement-movcond.patch
@ -1,4 +1,4 @@
-From 7a6273e2995b6c439441316467ab19bd6a48f03f Mon Sep 17 00:00:00 2001
+From 81d87e0831a57e38d11396277515a140c90ae49b Mon Sep 17 00:00:00 2001
 From: Richard Henderson <rth@twiddle.net>
 Date: Fri, 21 Sep 2012 10:13:36 -0700
 Subject: [PATCH] tcg-i386: Implement movcond
@ -113,6 +113,3 @@ index 504f953..b356d76 100644
 #endif
 
 #define TCG_TARGET_deposit_i32_valid(ofs, len) \
-- 
-1.7.12.1
-
--- a/0052-tcg-Optimize-movcond-for-constant-comparisons.patch
+++ b/0052-tcg-Optimize-movcond-for-constant-comparisons.patch
@ -1,4 +1,4 @@
-From c489b380d3f827be91b5f8b80b88585fb4014fbb Mon Sep 17 00:00:00 2001
+From d99f939cec0a15e0ba77e485b6e65f0f56f40c65 Mon Sep 17 00:00:00 2001
 From: Richard Henderson <rth@twiddle.net>
 Date: Fri, 21 Sep 2012 10:13:37 -0700
 Subject: [PATCH] tcg: Optimize movcond for constant comparisons
@ -68,6 +68,3 @@ index 9da333c..26038a6 100644
         case INDEX_op_call:
             nb_call_args = (args[0] >> 16) + (args[0] & 0xffff);
             if (!(args[nb_call_args + 1] & (TCG_CALL_CONST | TCG_CALL_PURE))) {
-- 
-1.7.12.1
-
--- a/0053-tcg-Optimize-two-address-commutative-operations.patch
+++ b/0053-tcg-Optimize-two-address-commutative-operations.patch
@ -1,4 +1,4 @@
-From af2bf6bcc6614622c87d28e9d763b57408c17500 Mon Sep 17 00:00:00 2001
+From a7db99b334acc889b570c27bcee38eb29cb3a90c Mon Sep 17 00:00:00 2001
 From: Richard Henderson <rth@twiddle.net>
 Date: Fri, 21 Sep 2012 10:13:38 -0700
 Subject: [PATCH] tcg: Optimize two-address commutative operations
@ -52,6 +52,3 @@ index 26038a6..1be7631 100644
         default:
             break;
         }
-- 
-1.7.12.1
-
--- a/0054-gdbstub-sh4-fix-build-with-USE_SOFTFLOAT_STRUCT_TYPE.patch
+++ b/0054-gdbstub-sh4-fix-build-with-USE_SOFTFLOAT_STRUCT_TYPE.patch
@ -1,4 +1,4 @@
-From b6407e30c30268cdeddec6e2b115f419647cc07f Mon Sep 17 00:00:00 2001
+From fb10603b1f812733e5b2eeb57d9a5bc5d3147239 Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Sun, 16 Sep 2012 13:12:21 +0200
 Subject: [PATCH] gdbstub/sh4: fix build with USE_SOFTFLOAT_STRUCT_TYPES
@ -187,6 +187,3 @@ index 5d37dd9..a91709f 100644
     default: return 0;
     }
 
-- 
-1.7.12.1
-
--- a/0055-tcg-Fix-USE_DIRECT_JUMP.patch
+++ b/0055-tcg-Fix-USE_DIRECT_JUMP.patch
@ -1,4 +1,4 @@
-From 03ddebf0c48dc78070c846b7cfdc2665fe7df854 Mon Sep 17 00:00:00 2001
+From f42ad07a5bbc83bd4d34138870aa29a9b51b44ce Mon Sep 17 00:00:00 2001
 From: Richard Henderson <rth@twiddle.net>
 Date: Mon, 17 Sep 2012 08:28:52 -0700
 Subject: [PATCH] tcg: Fix !USE_DIRECT_JUMP
@ -30,6 +30,3 @@ index f454107..609ed86 100644
     uint16_t *tb_next_offset;
     uint16_t *tb_jmp_offset; /* != NULL if USE_DIRECT_JUMP */
 
-- 
-1.7.12.1
-
--- a/0056-tcg-hppa-Fix-brcond2-and-setcond2.patch
+++ b/0056-tcg-hppa-Fix-brcond2-and-setcond2.patch
@ -1,4 +1,4 @@
-From 3616400bc0065f7114172ad7801d9d88332ef981 Mon Sep 17 00:00:00 2001
+From c224e5d6a34648099208748624a40620a1e17a86 Mon Sep 17 00:00:00 2001
 From: Richard Henderson <rth@twiddle.net>
 Date: Tue, 18 Sep 2012 19:59:47 -0700
 Subject: [PATCH] tcg-hppa: Fix brcond2 and setcond2
@ -103,6 +103,3 @@ index 8b81b70..a76569d 100644
     }
 
     tcg_out_mov(s, TCG_TYPE_I32, ret, scratch);
-- 
-1.7.12.1
-
--- a/0057-tcg-hppa-Fix-broken-load-store-helpers.patch
+++ b/0057-tcg-hppa-Fix-broken-load-store-helpers.patch
@ -1,4 +1,4 @@
-From c13ecfea174994d3f7f7d392f0faaed6d40efd9e Mon Sep 17 00:00:00 2001
+From cf4c5bb56040a9944bb9565492f761e888a7bcef Mon Sep 17 00:00:00 2001
 From: Richard Henderson <rth@twiddle.net>
 Date: Tue, 18 Sep 2012 19:59:48 -0700
 Subject: [PATCH] tcg-hppa: Fix broken load/store helpers
@ -244,6 +244,3 @@ index a76569d..5385d45 100644
         addrlo_reg = TCG_REG_R31;
     }
     tcg_out_qemu_st_direct(s, datalo_reg, datahi_reg, addrlo_reg, opc);
-- 
-1.7.12.1
-
--- a/0058-tcg-mips-fix-wrong-usage-of-Z-constraint.patch
+++ b/0058-tcg-mips-fix-wrong-usage-of-Z-constraint.patch
@ -1,4 +1,4 @@
-From 061d22ad76512e8ec10af89eda1dcc7c185360d2 Mon Sep 17 00:00:00 2001
+From 271d71e9ebfec527e61b6e793599cb3112aa6227 Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Fri, 21 Sep 2012 18:20:25 +0200
 Subject: [PATCH] tcg-mips: fix wrong usage of 'Z' constraint
@ -60,6 +60,3 @@ index 74db83d..9293745 100644
     { INDEX_op_brcond2_i32, { "rZ", "rZ", "rZ", "rZ" } },
 
 #if TARGET_LONG_BITS == 32
-- 
-1.7.12.1
-
--- a/0059-tcg-mips-kill-warnings-in-user-mode.patch
+++ b/0059-tcg-mips-kill-warnings-in-user-mode.patch
@ -1,4 +1,4 @@
-From e63a3c6c70c9933320c6d8b23c3ea4cf4724d316 Mon Sep 17 00:00:00 2001
+From 1d3b64528e9506f19c2675806a0383a5a99e1058 Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Fri, 21 Sep 2012 18:20:25 +0200
 Subject: [PATCH] tcg/mips: kill warnings in user mode
@ -161,6 +161,3 @@ index 9293745..a09c0d6 100644
 
 #if defined(CONFIG_SOFTMMU)
     tcg_out_opc_sa(s, OPC_SRL, TCG_REG_A0, addr_regl, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
-- 
-1.7.12.1
-
--- a/0060-tcg-mips-use-TCGArg-or-TCGReg-instead-of-int.patch
+++ b/0060-tcg-mips-use-TCGArg-or-TCGReg-instead-of-int.patch
@ -1,4 +1,4 @@
-From 7b817977fbb87ee2e34018d92b64907197974a75 Mon Sep 17 00:00:00 2001
+From 2417514a55d2f449c3eb1d244f3d232327528917 Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Fri, 21 Sep 2012 18:20:26 +0200
 Subject: [PATCH] tcg/mips: use TCGArg or TCGReg instead of int
@ -241,6 +241,3 @@ index a09c0d6..8b38f98 100644
 # endif
 #endif
     data_regl = *args++;
-- 
-1.7.12.1
-
--- a/0061-tcg-mips-don-t-use-global-pointer.patch
+++ b/0061-tcg-mips-don-t-use-global-pointer.patch
@ -1,4 +1,4 @@
-From 9a4f545e4526f946613548a427fcab4c2a089ac0 Mon Sep 17 00:00:00 2001
+From 4818ab7f1cad3d14e933f3bf5781ba3d5d1373a7 Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Fri, 21 Sep 2012 18:20:26 +0200
 Subject: [PATCH] tcg/mips: don't use global pointer
@ -32,6 +32,3 @@ index 8b38f98..0ea6a76 100644
 
     tcg_add_target_add_op_defs(mips_op_defs);
     tcg_set_frame(s, TCG_AREG0, offsetof(CPUArchState, temp_buf),
-- 
-1.7.12.1
-
--- a/0062-tcg-mips-use-stack-for-TCG-temps.patch
+++ b/0062-tcg-mips-use-stack-for-TCG-temps.patch
@ -1,4 +1,4 @@
-From c914ae50df4dc2f2ab589c87c0cd2ce2f14d9639 Mon Sep 17 00:00:00 2001
+From 66ffd70bdc4f758aaef51fb066d73866e92f593c Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Fri, 21 Sep 2012 18:20:26 +0200
 Subject: [PATCH] tcg/mips: use stack for TCG temps
@ -42,6 +42,3 @@ index 0ea6a76..c05169f 100644
 -    tcg_set_frame(s, TCG_AREG0, offsetof(CPUArchState, temp_buf),
 -                  CPU_TEMP_BUF_NLONGS * sizeof(long));
 }
-- 
-1.7.12.1
-
--- a/0063-tcg-mips-optimize-brcond-arg-0.patch
+++ b/0063-tcg-mips-optimize-brcond-arg-0.patch
@ -1,4 +1,4 @@
-From e30cf829e9d8200364b53b9189c76d2155a32876 Mon Sep 17 00:00:00 2001
+From 81f0620bea5b080308d97c699d9289bf3610b3e7 Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Fri, 21 Sep 2012 18:20:26 +0200
 Subject: [PATCH] tcg/mips: optimize brcond arg, 0
@ -94,6 +94,3 @@ index c05169f..6aa4527 100644
         break;
     case TCG_COND_GTU:
         tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, arg2, arg1);
-- 
-1.7.12.1
-
--- a/0064-tcg-mips-optimize-bswap-16-16s-32-on-MIPS32R2.patch
+++ b/0064-tcg-mips-optimize-bswap-16-16s-32-on-MIPS32R2.patch
@ -1,4 +1,4 @@
-From 879794c3d3974b1206bbc52011c8f2525709f396 Mon Sep 17 00:00:00 2001
+From cf8d505e41f49e2c568cd98b36b3ab9a06d30119 Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Fri, 21 Sep 2012 18:20:26 +0200
 Subject: [PATCH] tcg/mips: optimize bswap{16,16s,32} on MIPS32R2
@ -156,6 +156,3 @@ index 9c68a32..c5c13f7 100644
 /* optional instructions automatically implemented */
 #define TCG_TARGET_HAS_neg_i32          0 /* sub  rd, zero, rt   */
 #define TCG_TARGET_HAS_ext8u_i32        0 /* andi rt, rs, 0xff   */
-- 
-1.7.12.1
-
--- a/0065-tcg-mips-implement-rotl-rotr-ops-on-MIPS32R2.patch
+++ b/0065-tcg-mips-implement-rotl-rotr-ops-on-MIPS32R2.patch
@ -1,4 +1,4 @@
-From d19858a5515cd15dabf88b8f180754c1c3f3eb76 Mon Sep 17 00:00:00 2001
+From 2b72ceb3526bbfd08e9874ba895f965f41306fcc Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Fri, 21 Sep 2012 18:20:26 +0200
 Subject: [PATCH] tcg/mips: implement rotl/rotr ops on MIPS32R2
@ -87,6 +87,3 @@ index c5c13f7..470314c 100644
 #endif
 
 /* optional instructions automatically implemented */
-- 
-1.7.12.1
-
--- a/0066-tcg-mips-implement-deposit-op-on-MIPS32R2.patch
+++ b/0066-tcg-mips-implement-deposit-op-on-MIPS32R2.patch
@ -1,4 +1,4 @@
-From 7c3e573b364a65d4abce5266c376f4e77624b039 Mon Sep 17 00:00:00 2001
+From 7338fddbe058c6d68f93b3ceea881508629bbf6b Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Fri, 21 Sep 2012 18:20:26 +0200
 Subject: [PATCH] tcg/mips: implement deposit op on MIPS32R2
@ -72,6 +72,3 @@ index 470314c..897a737 100644
 #endif
 
 /* optional instructions automatically implemented */
-- 
-1.7.12.1
-
--- a/0067-tcg-mips-implement-movcond-op-on-MIPS32R2.patch
+++ b/0067-tcg-mips-implement-movcond-op-on-MIPS32R2.patch
@ -1,4 +1,4 @@
-From 552720cea4c1ca99dd1919cb8a80b6b8f3b13cda Mon Sep 17 00:00:00 2001
+From ec9ab7b8c0ee2517c286937339269743bcab33db Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Fri, 21 Sep 2012 18:20:26 +0200
 Subject: [PATCH] tcg/mips: implement movcond op on MIPS32R2
@ -135,6 +135,3 @@ index 897a737..d147e70 100644
 
 /* optional instructions only implemented on MIPS32R2 */
 #ifdef _MIPS_ARCH_MIPS32R2
-- 
-1.7.12.1
-
--- a/0068-tcg-optimize-remove-TCG_TEMP_ANY.patch
+++ b/0068-tcg-optimize-remove-TCG_TEMP_ANY.patch
@ -1,4 +1,4 @@
-From 848750a4acf9ea5c473be596d41720e702d770f0 Mon Sep 17 00:00:00 2001
+From 9b6076100dff3544167cde8a28de17f31e3db05b Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Mon, 10 Sep 2012 23:51:42 +0200
 Subject: [PATCH] tcg/optimize: remove TCG_TEMP_ANY
@ -57,6 +57,3 @@ index 1be7631..308b7f9 100644
     }
 }
 
-- 
-1.7.12.1
-
--- a/0069-tcg-optimize-check-types-in-copy-propagation.patch
+++ b/0069-tcg-optimize-check-types-in-copy-propagation.patch
@ -1,4 +1,4 @@
-From 71f0bcf065ddd00d5659e846ddfdffb9a06ee896 Mon Sep 17 00:00:00 2001
+From 6a2e2cec5504f331c49b60c70e2a31f8d39a3215 Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Tue, 11 Sep 2012 12:26:23 +0200
 Subject: [PATCH] tcg/optimize: check types in copy propagation
@ -73,6 +73,3 @@ index 308b7f9..da8dffe 100644
                 gen_args += 2;
                 args += 2;
                 break;
-- 
-1.7.12.1
-
--- a/0070-tcg-optimize-rework-copy-progagation.patch
+++ b/0070-tcg-optimize-rework-copy-progagation.patch
@ -1,4 +1,4 @@
-From bf408071104de13f79a0c3c8cac892f440462e7c Mon Sep 17 00:00:00 2001
+From 072c17810a3ebf5865e7a8df745325149bce35b9 Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Tue, 11 Sep 2012 12:31:21 +0200
 Subject: [PATCH] tcg/optimize: rework copy progagation
@ -372,6 +372,3 @@ index da8dffe..1904b39 100644
                 }
             }
             for (i = 0; i < def->nb_args; i++) {
-- 
-1.7.12.1
-
--- a/0071-tcg-optimize-do-copy-propagation-for-all-operations.patch
+++ b/0071-tcg-optimize-do-copy-propagation-for-all-operations.patch
@ -1,4 +1,4 @@
-From 7c1a67bb734f364ea0643b549e030f04d4eed798 Mon Sep 17 00:00:00 2001
+From ecb4e3759e0cbd46852b84e604627725325fd244 Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Tue, 11 Sep 2012 16:18:49 +0200
 Subject: [PATCH] tcg/optimize: do copy propagation for all operations
@ -37,6 +37,3 @@ index 1904b39..aeb2225 100644
             for (i = def->nb_oargs; i < def->nb_oargs + def->nb_iargs; i++) {
                 if (temps[args[i]].state == TCG_TEMP_COPY) {
                     args[i] = find_better_copy(s, args[i]);
-- 
-1.7.12.1
-
--- a/0072-tcg-optimize-optimize-op-r-a-a-mov-r-a.patch
+++ b/0072-tcg-optimize-optimize-op-r-a-a-mov-r-a.patch
@ -1,4 +1,4 @@
-From e38329760e40a354e37d11c7f5d8c86cdb90736c Mon Sep 17 00:00:00 2001
+From c9adee9d660a658308e70b591b5c061ef5ccb40b Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Tue, 18 Sep 2012 19:11:32 +0200
 Subject: [PATCH] tcg/optimize: optimize "op r, a, a => mov r, a"
@ -26,6 +26,3 @@ index aeb2225..b9a7da9 100644
                 if (temps_are_copies(args[0], args[1])) {
                     gen_opc_buf[op_index] = INDEX_op_nop;
                 } else {
-- 
-1.7.12.1
-
--- a/0073-tcg-optimize-optimize-op-r-a-a-movi-r-0.patch
+++ b/0073-tcg-optimize-optimize-op-r-a-a-movi-r-0.patch
@ -1,4 +1,4 @@
-From 363479b4d4f729959eafb1209d48ad75e928c00a Mon Sep 17 00:00:00 2001
+From 49c949e3690b555659eee93bca7290f81b5b5315 Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Tue, 18 Sep 2012 19:12:36 +0200
 Subject: [PATCH] tcg/optimize: optimize "op r, a, a => movi r, 0"
@ -41,6 +41,3 @@ index b9a7da9..ceea644 100644
         /* Propagate constants through copy operations and do constant
            folding.  Constants will be substituted to arguments by register
            allocator where needed and possible.  Also detect copies. */
-- 
-1.7.12.1
-
--- a/0074-tcg-optimize-further-optimize-brcond-movcond-setcond.patch
+++ b/0074-tcg-optimize-further-optimize-brcond-movcond-setcond.patch
@ -1,4 +1,4 @@
-From 8d5f3ca9ccace2374fd73d46fad56decc02e0a44 Mon Sep 17 00:00:00 2001
+From 4d7aec66112296144802c4743a7076548349728c Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Tue, 18 Sep 2012 19:37:00 +0200
 Subject: [PATCH] tcg/optimize: further optimize brcond/movcond/setcond
@ -187,6 +187,3 @@ index ceea644..abe016a 100644
                 if (temps_are_copies(args[0], args[4-tmp])) {
                     gen_opc_buf[op_index] = INDEX_op_nop;
                 } else if (temps[args[4-tmp]].state == TCG_TEMP_CONST) {
-- 
-1.7.12.1
-
--- a/0075-tcg-optimize-prefer-the-op-a-a-b-form-for-commutativ.patch
+++ b/0075-tcg-optimize-prefer-the-op-a-a-b-form-for-commutativ.patch
@ -1,4 +1,4 @@
-From a0b71ad6a3f8aeb8b5ea6d112a7afeadc7c004a4 Mon Sep 17 00:00:00 2001
+From 229e24c570a934074df2ad1f7df991dc0ae6ad25 Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Wed, 19 Sep 2012 22:00:22 +0200
 Subject: [PATCH] tcg/optimize: prefer the "op a, a, b" form for commutative
@ -33,6 +33,3 @@ index abe016a..c8ae50b 100644
                 tmp = args[1];
                 args[1] = args[2];
                 args[2] = tmp;
-- 
-1.7.12.1
-
--- a/0076-tcg-remove-ifdef-endif-around-TCGOpcode-tests.patch
+++ b/0076-tcg-remove-ifdef-endif-around-TCGOpcode-tests.patch
@ -1,4 +1,4 @@
-From 3942910a66f682b98ac53ac2d2fba65b9c75eefd Mon Sep 17 00:00:00 2001
+From a16013b44c05b95548b5d340cb9b66a43a7fd4f1 Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Fri, 21 Sep 2012 10:02:45 +0200
 Subject: [PATCH] tcg: remove #ifdef #endif around TCGOpcode tests
@ -63,6 +63,3 @@ index 24ce830..93421cd 100644
             tcg_reg_alloc_movi(s, args);
             break;
         case INDEX_op_debug_insn_start:
-- 
-1.7.12.1
-
--- a/0077-tcg-optimize-add-constant-folding-for-deposit.patch
+++ b/0077-tcg-optimize-add-constant-folding-for-deposit.patch
@ -1,4 +1,4 @@
-From 04edfbcf025b5588e0f3b86c74356a4339745f35 Mon Sep 17 00:00:00 2001
+From ba3e0a3391bf6523de1332fc1b5dc5c480649584 Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Fri, 21 Sep 2012 11:07:29 +0200
 Subject: [PATCH] tcg/optimize: add constant folding for deposit
@ -41,6 +41,3 @@ index c8ae50b..35532a1 100644
         CASE_OP_32_64(setcond):
             tmp = do_constant_folding_cond(op, args[1], args[2], args[3]);
             if (tmp != 2) {
-- 
-1.7.12.1
-
--- a/0078-tcg-README-document-tcg_gen_goto_tb-restrictions.patch
+++ b/0078-tcg-README-document-tcg_gen_goto_tb-restrictions.patch
@ -1,4 +1,4 @@
-From 08de143bdd34e906c3e89443cb6b24665f7c088d Mon Sep 17 00:00:00 2001
+From 13529cc74ba53fb032172a58dfb04ea4d6e64891 Mon Sep 17 00:00:00 2001
 From: Max Filippov <jcmvbkbc@gmail.com>
 Date: Fri, 21 Sep 2012 04:18:07 +0400
 Subject: [PATCH] tcg/README: document tcg_gen_goto_tb restrictions
@ -28,6 +28,3 @@ index d03ae05..33783ee 100644
 
 * qemu_ld8u t0, t1, flags
 qemu_ld8s t0, t1, flags
-- 
-1.7.12.1
-
--- a/0079-w64-Fix-TCG-helper-functions-with-5-arguments.patch
+++ b/0079-w64-Fix-TCG-helper-functions-with-5-arguments.patch
@ -1,4 +1,4 @@
-From e35e8b9bb446ff2693962151b8c80c5c88294959 Mon Sep 17 00:00:00 2001
+From 11ab09ddb7d4d33e7c3f7d366119f367e0d2f04d Mon Sep 17 00:00:00 2001
 From: Stefan Weil <sw@weilnetz.de>
 Date: Thu, 13 Sep 2012 19:37:43 +0200
 Subject: [PATCH] w64: Fix TCG helper functions with 5 arguments
@ -52,6 +52,3 @@ index b356d76..ace63ba 100644
 
 /* optional instructions */
 #define TCG_TARGET_HAS_div2_i32         1
-- 
-1.7.12.1
-
--- a/0080-tcg-ppc32-Implement-movcond32.patch
+++ b/0080-tcg-ppc32-Implement-movcond32.patch
@ -1,4 +1,4 @@
-From d65d20819ac52207befffa9a7aa858cc7de9cbaf Mon Sep 17 00:00:00 2001
+From 8a1f291dc117467c868336a707463256de70ddf0 Mon Sep 17 00:00:00 2001
 From: malc <av1474@comtv.ru>
 Date: Sat, 22 Sep 2012 19:14:33 +0400
 Subject: [PATCH] tcg/ppc32: Implement movcond32
@ -132,6 +132,3 @@ index 177eea1..3259d89 100644
 
 #define TCG_AREG0 TCG_REG_R27
 
-- 
-1.7.12.1
-
--- a/0081-tcg-sparc-Hack-in-qemu_ld-st64-for-32-bit.patch
+++ b/0081-tcg-sparc-Hack-in-qemu_ld-st64-for-32-bit.patch
@ -1,4 +1,4 @@
-From da65fa6c51ef1c999ffc75a162e95285d4cb915b Mon Sep 17 00:00:00 2001
+From bdd02f4c48394d0753e765132f7e15ee1136c75f Mon Sep 17 00:00:00 2001
 From: Richard Henderson <rth@twiddle.net>
 Date: Sat, 24 Mar 2012 21:30:20 +0100
 Subject: [PATCH] tcg-sparc: Hack in qemu_ld/st64 for 32-bit.
@ -25,6 +25,3 @@ index baed3b4..608fc46 100644
 #endif
     { -1 },
 };
-- 
-1.7.12.1
-
--- a/0082-tcg-sparc-Fix-ADDX-opcode.patch
+++ b/0082-tcg-sparc-Fix-ADDX-opcode.patch
@ -1,4 +1,4 @@
-From b92aceeb9604c74e4a66db8ea5dd399d892e94bc Mon Sep 17 00:00:00 2001
+From 161ff662927ad0c29a65963c4de57dc704e79e9c Mon Sep 17 00:00:00 2001
 From: Richard Henderson <rth@twiddle.net>
 Date: Fri, 23 Mar 2012 23:57:12 +0100
 Subject: [PATCH] tcg-sparc: Fix ADDX opcode.
@ -22,6 +22,3 @@ index 608fc46..0a19313 100644
 #define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c))
 #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
 #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
-- 
-1.7.12.1
-
--- a/0083-tcg-sparc-Don-t-MAP_FIXED-on-top-of-the-program.patch
+++ b/0083-tcg-sparc-Don-t-MAP_FIXED-on-top-of-the-program.patch
@ -1,4 +1,4 @@
-From 59aadb4f5b15eff968ed00ad29816ac19bef507d Mon Sep 17 00:00:00 2001
+From 3399e5800a1ae2e41adb24c3741852c4a3ff7726 Mon Sep 17 00:00:00 2001
 From: Richard Henderson <rth@twiddle.net>
 Date: Fri, 21 Sep 2012 10:40:48 -0700
 Subject: [PATCH] tcg-sparc: Don't MAP_FIXED on top of the program
@ -40,6 +40,3 @@ index 5834766..871a68a 100644
         if (code_gen_buffer_size > (512 * 1024 * 1024)) {
             code_gen_buffer_size = (512 * 1024 * 1024);
         }
-- 
-1.7.12.1
-
--- a/0084-tcg-sparc-Assume-v9-cpu-always-i.e.-force-v8plus-in-.patch
+++ b/0084-tcg-sparc-Assume-v9-cpu-always-i.e.-force-v8plus-in-.patch
@ -1,4 +1,4 @@
-From cf873edf4227be439a9ffa5abb3da61ff1fd6527 Mon Sep 17 00:00:00 2001
+From 764010fd034a93bd1d266e443097d5e8f4d11b09 Mon Sep 17 00:00:00 2001
 From: Richard Henderson <rth@twiddle.net>
 Date: Fri, 21 Sep 2012 10:34:21 -0700
 Subject: [PATCH] tcg-sparc: Assume v9 cpu always, i.e. force v8plus in 32-bit
@ -281,6 +281,3 @@ index 93421cd..16c4e1d 100644
     s->current_frame_offset = (s->current_frame_offset +
                                (tcg_target_long)sizeof(tcg_target_long) - 1) &
         ~(sizeof(tcg_target_long) - 1);
-- 
-1.7.12.1
-
--- a/0085-tcg-sparc-Fix-qemu_ld-st-to-handle-32-bit-host.patch
+++ b/0085-tcg-sparc-Fix-qemu_ld-st-to-handle-32-bit-host.patch
@ -1,4 +1,4 @@
-From 138dfa905538bf918af390ff365a27de49364578 Mon Sep 17 00:00:00 2001
+From 6301321f2a6fd77cbc2ad7f2881d69fd38160c3e Mon Sep 17 00:00:00 2001
 From: Richard Henderson <rth@twiddle.net>
 Date: Fri, 23 Mar 2012 23:27:39 +0100
 Subject: [PATCH] tcg-sparc: Fix qemu_ld/st to handle 32-bit host.
@ -962,6 +962,3 @@ index 23c2fda..d89c19b 100644
     { -1 },
 };
 
-- 
-1.7.12.1
-
--- a/0086-tcg-sparc-Support-GUEST_BASE.patch
+++ b/0086-tcg-sparc-Support-GUEST_BASE.patch
@ -1,4 +1,4 @@
-From fecc7bd255206876152baab622c61902133066bd Mon Sep 17 00:00:00 2001
+From d541c8bd75be8c6a005ec84ca5bc3e0a9ffee896 Mon Sep 17 00:00:00 2001
 From: Richard Henderson <rth@twiddle.net>
 Date: Sat, 24 Mar 2012 22:11:25 +0100
 Subject: [PATCH] tcg-sparc: Support GUEST_BASE.
@ -108,6 +108,3 @@ index adca1d2..99e9f57 100644
 #ifdef CONFIG_SOLARIS
 #define TCG_AREG0 TCG_REG_G2
 #elif HOST_LONG_BITS == 64
-- 
-1.7.12.1
-
--- a/0087-tcg-sparc-Change-AREG0-in-generated-code-to-i0.patch
+++ b/0087-tcg-sparc-Change-AREG0-in-generated-code-to-i0.patch
@ -1,4 +1,4 @@
-From d526285d4339f02e3be64a7287d1e009dd5bff3d Mon Sep 17 00:00:00 2001
+From 32f94d904dabe209a7d66c28bd7015d4268f8083 Mon Sep 17 00:00:00 2001
 From: Richard Henderson <rth@twiddle.net>
 Date: Sun, 25 Mar 2012 19:52:11 +0200
 Subject: [PATCH] tcg-sparc: Change AREG0 in generated code to %i0.
@ -46,6 +46,3 @@ index 99e9f57..ee154d0 100644
 
 static inline void flush_icache_range(tcg_target_ulong start,
                                       tcg_target_ulong stop)
-- 
-1.7.12.1
-
--- a/0088-tcg-sparc-Clean-up-cruft-stemming-from-attempts-to-u.patch
+++ b/0088-tcg-sparc-Clean-up-cruft-stemming-from-attempts-to-u.patch
@ -1,4 +1,4 @@
-From 5767c23140f2c92b899d9caeaa8e08711cb63868 Mon Sep 17 00:00:00 2001
+From 075fb033238d41d8602186f32bbdb330f1daf11e Mon Sep 17 00:00:00 2001
 From: Richard Henderson <rth@twiddle.net>
 Date: Sun, 25 Mar 2012 21:21:46 +0200
 Subject: [PATCH] tcg-sparc: Clean up cruft stemming from attempts to use
@ -198,6 +198,3 @@ index ee154d0..6314ffb 100644
 #endif
 
 #if TCG_TARGET_REG_BITS == 64
-- 
-1.7.12.1
-
--- a/0089-tcg-sparc-Mask-shift-immediates-to-avoid-illegal-ins.patch
+++ b/0089-tcg-sparc-Mask-shift-immediates-to-avoid-illegal-ins.patch
@ -1,4 +1,4 @@
-From 12e60f780a097837840ab1e7bb7d54b8c15112e8 Mon Sep 17 00:00:00 2001
+From 3a750594f73232c5e47ca0f57d53594208d64033 Mon Sep 17 00:00:00 2001
 From: Richard Henderson <rth@twiddle.net>
 Date: Sun, 25 Mar 2012 21:36:28 +0200
 Subject: [PATCH] tcg-sparc: Mask shift immediates to avoid illegal insns.
@ -57,6 +57,3 @@ index e625aa3..be5c170 100644
     case INDEX_op_mul_i64:
         c = ARITH_MULX;
         goto gen_arith;
-- 
-1.7.12.1
-
--- a/0090-tcg-sparc-Use-defines-for-temporaries.patch
+++ b/0090-tcg-sparc-Use-defines-for-temporaries.patch
@ -1,4 +1,4 @@
-From fc9726f880dea515a2cf98456c5f03a1388e4e14 Mon Sep 17 00:00:00 2001
+From 7933c1ad712ff592b78f75c67df47d83435ea44b Mon Sep 17 00:00:00 2001
 From: Richard Henderson <rth@twiddle.net>
 Date: Sun, 25 Mar 2012 22:04:59 +0200
 Subject: [PATCH] tcg-sparc: Use defines for temporaries.
@ -270,6 +270,3 @@ index be5c170..d401f8e 100644
     tcg_add_target_add_op_defs(sparc_op_defs);
 }
 
-- 
-1.7.12.1
-
--- a/0091-tcg-sparc-Add-g-o-registers-to-alloc_order.patch
+++ b/0091-tcg-sparc-Add-g-o-registers-to-alloc_order.patch
@ -1,4 +1,4 @@
-From ca72cdf648b56d851c4bc9145a1abfcbeeec0579 Mon Sep 17 00:00:00 2001
+From 94073142a960c8933cc44f172d6ec64381c5b6c9 Mon Sep 17 00:00:00 2001
 From: Richard Henderson <rth@twiddle.net>
 Date: Sun, 25 Mar 2012 22:43:17 +0200
 Subject: [PATCH] tcg-sparc: Add %g/%o registers to alloc_order
@ -39,6 +39,3 @@ index d401f8e..03c385a 100644
 };
 
 static const int tcg_target_call_iarg_regs[6] = {
-- 
-1.7.12.1
-
--- a/0092-tcg-sparc-Fix-and-enable-direct-TB-chaining.patch
+++ b/0092-tcg-sparc-Fix-and-enable-direct-TB-chaining.patch
@ -1,4 +1,4 @@
-From 1338a6f18ff9b651c12ee1f7edd1d2b7684bd6aa Mon Sep 17 00:00:00 2001
+From 24b6288b402b1c41aba42aeb5067ac0932e5670d Mon Sep 17 00:00:00 2001
 From: Richard Henderson <rth@twiddle.net>
 Date: Fri, 21 Sep 2012 10:48:51 -0700
 Subject: [PATCH] tcg-sparc: Fix and enable direct TB chaining.
@ -74,6 +74,3 @@ index 03c385a..1db0c9d 100644
 +    *ptr = CALL | (disp & 0x3fffffff);
 +    flush_icache_range(jmp_addr, jmp_addr + 4);
 +}
-- 
-1.7.12.1
-
--- a/0093-tcg-sparc-Preserve-branch-destinations-during-retran.patch
+++ b/0093-tcg-sparc-Preserve-branch-destinations-during-retran.patch
@ -1,4 +1,4 @@
-From 2cbc27913eb9eb7cdc4a41fc6efafccf3db7ebe6 Mon Sep 17 00:00:00 2001
+From 6be44595bf9e3cc9d0cefb3625e9f18fbbf852df Mon Sep 17 00:00:00 2001
 From: Richard Henderson <rth@twiddle.net>
 Date: Fri, 21 Sep 2012 11:00:23 -0700
 Subject: [PATCH] tcg-sparc: Preserve branch destinations during retranslation
@ -55,6 +55,3 @@ index 1db0c9d..876da4f 100644
 }
 #endif
 
-- 
-1.7.12.1
-
--- a/0094-target-alpha-Initialize-env-cpu_model_str.patch
+++ b/0094-target-alpha-Initialize-env-cpu_model_str.patch
@ -1,4 +1,4 @@
-From fcf8cef0c7d8d197e863c1e8b7bcb567fa1fe729 Mon Sep 17 00:00:00 2001
+From 9cec603abce19ed4352afa939f383d22b3a10c65 Mon Sep 17 00:00:00 2001
 From: Richard Henderson <rth@twiddle.net>
 Date: Fri, 21 Sep 2012 14:15:36 +0200
 Subject: [PATCH] target-alpha: Initialize env->cpu_model_str
@ -28,6 +28,3 @@ index 4a9011a..3f9aee1 100644
 
     qemu_init_vcpu(env);
     return env;
-- 
-1.7.12.1
-
--- a/0095-tcg-mips-fix-MIPS32-R2-detection.patch
+++ b/0095-tcg-mips-fix-MIPS32-R2-detection.patch
@ -1,4 +1,4 @@
-From 66588d01b8cb710d746c249a34f31f7f353bc697 Mon Sep 17 00:00:00 2001
+From 6db3527cb219b6efe1931cb004d3b0d908238a1e Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Sat, 22 Sep 2012 23:08:38 +0200
 Subject: [PATCH] tcg/mips: fix MIPS32(R2) detection
@ -88,6 +88,3 @@ index d147e70..7020d65 100644
 #define TCG_TARGET_HAS_bswap16_i32      1
 #define TCG_TARGET_HAS_bswap32_i32      1
 #define TCG_TARGET_HAS_rot_i32          1
-- 
-1.7.12.1
-
--- a/0096-tcg-Adjust-descriptions-of-cond-opcodes.patch
+++ b/0096-tcg-Adjust-descriptions-of-cond-opcodes.patch
@ -1,4 +1,4 @@
-From a2c90b264762d3ddcc9a830653315a6fe9107055 Mon Sep 17 00:00:00 2001
+From ee5d0e1355c3d0abd62d314007e83058b62d1a5f Mon Sep 17 00:00:00 2001
 From: Richard Henderson <rth@twiddle.net>
 Date: Fri, 21 Sep 2012 17:18:09 -0700
 Subject: [PATCH] tcg: Adjust descriptions of *cond opcodes
@ -62,6 +62,3 @@ index 33783ee..27846f1 100644
 
 Similar to setcond, except that the 64-bit values T1 and T2 are
 formed from two 32-bit arguments.  The result is a 32-bit value.
-- 
-1.7.12.1
-
--- a/0097-tcg-i386-fix-build-with-march-i686.patch
+++ b/0097-tcg-i386-fix-build-with-march-i686.patch
@ -1,4 +1,4 @@
-From 5d3868bb343df0c13240521e36d0cc942c7a2d04 Mon Sep 17 00:00:00 2001
+From b6b73085fe939404092998a6653e44643a8fd430 Mon Sep 17 00:00:00 2001
 From: Aurelien Jarno <aurelien@aurel32.net>
 Date: Wed, 26 Sep 2012 00:30:12 +0200
 Subject: [PATCH] tcg/i386: fix build with -march < i686
@ -29,6 +29,3 @@ index 85c6b81..616ef23 100644
 
 #if TCG_TARGET_REG_BITS == 32
     { INDEX_op_mulu2_i32, { "a", "d", "a", "r" } },
-- 
-1.7.12.1
-
--- a/0098-tcg-Fix-MAX_OPC_PARAM_IARGS.patch
+++ b/0098-tcg-Fix-MAX_OPC_PARAM_IARGS.patch
@ -1,4 +1,4 @@
-From 86aeba1e72542270a2ae2570cdfcfa6b9e59eeb8 Mon Sep 17 00:00:00 2001
+From 0db63b6f9d059bf9a1f4841a2c3be92530880e4b Mon Sep 17 00:00:00 2001
 From: Stefan Weil <sw@weilnetz.de>
 Date: Wed, 12 Sep 2012 19:18:55 +0200
 Subject: [PATCH] tcg: Fix MAX_OPC_PARAM_IARGS
@ -47,6 +47,3 @@ index 1f81da7..6516da0 100644
 #define MAX_OPC_PARAM_OARGS 1
 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
 
-- 
-1.7.12.1
-
--- a/0099-tci-Fix-for-AREG0-free-mode.patch
+++ b/0099-tci-Fix-for-AREG0-free-mode.patch
@ -1,4 +1,4 @@
-From 2acbc7d596b022dca4fc147eb89e3d5f297acb1f Mon Sep 17 00:00:00 2001
+From a7e6a74efde077f4e1102cbb563f8b1bca1f8002 Mon Sep 17 00:00:00 2001
 From: Stefan Weil <sw@weilnetz.de>
 Date: Tue, 18 Sep 2012 22:43:38 +0200
 Subject: [PATCH] tci: Fix for AREG0 free mode
@ -114,6 +114,3 @@ index ce8a988..a4f7b78 100644
             tci_write_reg(TCG_REG_R0, tmp64);
 #endif
             break;
-- 
-1.7.12.1
-
--- a/0100-spice-abort-on-invalid-streaming-cmdline-params.patch
+++ b/0100-spice-abort-on-invalid-streaming-cmdline-params.patch
@ -1,4 +1,4 @@
-From 9fa75115d0f300817a372dd8b9460d6b65a30b20 Mon Sep 17 00:00:00 2001
+From 1e7b58a3d7c6bbe0f557c490f28c833b0c98303c Mon Sep 17 00:00:00 2001
 From: Christophe Fergeau <cfergeau@redhat.com>
 Date: Mon, 13 Aug 2012 10:32:32 +0200
 Subject: [PATCH] spice: abort on invalid streaming cmdline params
@ -36,6 +36,3 @@ index 4fc48f8..bb4f585 100644
 
 static const char *compression_names[] = {
     [ SPICE_IMAGE_COMPRESS_OFF ]      = "off",
-- 
-1.7.12.1
-
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Cole Robinson	fa00e1e04c	Fix build with latest dtc (bz #1003187 ) Fix initial /dev/kvm permissions (bz #993491)	2013-09-03 15:03:25 -04:00
Cole Robinson	e6754ddcb6	Don't install conflicting binfmt handler on arm (bz #974804 )	2013-06-19 10:29:10 -04:00
Cole Robinson	635c984c3e	Fix building docs with f19 texinfo CVE-2013-2007: Fix qemu-ga file creation permissions (bz #956082, bz #969455) Fix rtl8139 + windows 7 + large transfers (bz #970240)	2013-06-11 15:45:31 -04:00
Cole Robinson	72f684c1ae	Fix booting 3.8 kernels with qemu-system-arm (bz #922796 ) Fix crash with -vga qxl, sdl, and F19 guest (bz #949126) CVE-2013-1922: qemu-nbd block format auto-detection vulnerability (bz #952574, bz #923219)	2013-04-20 20:14:03 -04:00
Hans de Goede	4a0d0c08f7	Add an extra patch to really fix (bz #890320 )	2013-04-08 23:42:51 +02:00
Hans de Goede	6a0fe9263d	Fix use after free in ehci code (bz #890320 )	2013-04-03 11:29:31 +02:00
Cole Robinson	4a2d47e464	Don't use reserved word 'function' in systemtap files (bz #871286 ) Fixes for iscsi dep Fix -vga vmware crashes (bz #836260) Fix possible crash with VNC and qxl (bz #919777) Fix mellanox card passthrough (bz #907996) Fix QXL migration from F17 to F18 (bz #907916) Fix kvm module permissions after first install (bz #907215)	2013-04-01 21:15:57 -04:00
Paolo Bonzini	9ca03fda94	Added libiscsi-devel BuildRequires	2013-03-11 18:15:47 +01:00
Cole Robinson	9290838132	Fix boot hang if console is not connected (bz #894451 ) Fix segfault with zero length virtio-scsi disk (bz #847549)	2013-02-02 15:47:37 -05:00
Alon Levy	e051f2359e	fix missing error_set symbol in libcacard.so 2:1.2.2-5	2013-01-23 18:03:03 +02:00
Hans de Goede	83889a9bd2	Add "qxl: call dpy_gfx_resize when entering vga mode" patch, fixing an often reported use after free crash (rhbz#873845) - Replace "wip: hw/qxl: inject interrupts in any state" patch with the official upstream fix - Add 5 other spice/qxl crash/bug fixes cherry-picked from upstream	2013-01-21 16:09:24 +01:00
Hans de Goede	99c373db7f	Fix a crash when using -vga qxl without -spice (bz #892075 )	2013-01-18 15:50:38 +01:00
Cole Robinson	4e7a6e993e	CVE-2012-6075: Buffer overflow in e1000 nic (bz #889301 , bz #889304 ) Use systemd spec macros (bz #850285)	2013-01-16 10:28:50 -05:00
Cole Robinson	f375e62ad9	Update to qemu 1.2.2 stable Fix libvirt + seccomp combo (bz #855162) Fix scsi hotplug crash (bz #879657) Fix QOM refcount crash (bz #881486)	2012-12-16 18:27:22 -05:00
Alon Levy	d1c1d00a45	add libcacard, -25	2012-12-03 11:52:36 +02:00