Rebase RISC-V (riscv64) backend patch

Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>

qemu-3.0.0-riscv64-backend.patch

@@ -1,110 +1,5 @@
-From 0805ad337785f0cce29ecf162bad9e1c477051f3 Mon Sep 17 00:00:00 2001
-From: Michael Clark <mjc@sifive.com>
-Date: Sat, 10 Mar 2018 16:34:09 -0800
-Subject: [PATCH] RISC-V: RISC-V TCG backend work in progress
-
-This patch adds an experimental RISC-V TCG backend.
-
-We have been dogfooding the RISC-V QEMU front-end with Fedora
-Linux to develop a RISC-V TCG backend. The RISC-V TCG backend
-can be built inside of the QEMU RISC-V 'virt' machine using
-the Fedora stage 4 disk image:
-
-- https://fedoraproject.org/wiki/Architectures/RISC-V
-
-Below are brief instructions on building riscv64-linux-user
-and x86_64-linux-user QEMU inside a Fedora RISC-V environment
-using either QEMU RISC-V or SiFive's HiFive Unleashed board:
-
-```
-sudo dnf install git python flex bison \
-    zlib-devel glib2-devel pixman-devel
-git clone --recursive https://github.com/riscv/riscv-qemu.git
-cd riscv-qemu
-git checkout wip-riscv-tcg-backend
-./configure --enable-debug-tcg \
-    --target-list=riscv64-linux-user,x86_64-linux-user
-make -j$(nproc)
-```
-
-Testing
-
-There is a user-mode version of riscv-tests that can
-be used for testing RISC-V QEMU linux-user.
-
-- https://github.com/arsv/riscv-qemu-tests
-
-These tests can also be used to test the RISC-V TCG
-back-end via the RISC-V front-end. e.g.
-
-```
-for ext in i m a f d; do
-    for i in $(find rv64${ext} -type f -a -executable); do
-        echo $i
-        ../riscv-qemu/riscv64-linux-user/qemu-riscv64 \
-            --singlestep $i
-    done
-done
-```
-
-At present all of the Base ISA tests pass, although TCG
-performs constant folding so test code can be eliminated
-by the TCG optimizer unless qemu is run with --singlestep.
-
-All of the rv8-bench tests compiled for riscv64 and x86_64
-run (using musl-libc via the musl-riscv-toolchain):
-
-- https://github.com/rv8-io/musl-riscv-toolchain/
-- https://github.com/rv8-io/rv8-bench/
-- https://rv8.io/bench
-
-Caveats:
-
-- No support for Oversize guests (64-bit target 32-bit host)
-  (tcg_out_brcond2 and tcg_out_setcond2 are not implemented)
-- No support for Big-Endian (tcg_out_qemu_ld_direct and
-  tcg_out_qemu_st_direct don't support MO_BSWAP)
-- Full system emulator (softmmu) support requires debugging
-
-Changelog
-
-v2
-
-- Update configure pattern for riscv disassembler
-- Fix jal range in tcg_out_jump_internal
-- Elide 64-bit far jump on rv32
-- Encode far jump lower 12 bits in jalr
-- Use jal for INDEX_op_br
-- Add movi support for 64-bit PC-relative constants
-- Don't emit 64-bit jumps on rv32
-- Fix TCG_CT_CONST_S12 and TCG_CT_CONST_N12 ranges
-- Fix address calculation in tcg_out_ldst
-- Always set guest_base if not softmmu
-- Detect stores in cpu_signal_handler
-- Implement ext8s/ext8u/ext16s/ext16u
-- Implement softmmu support (requires debugging)
-
-v1
-
-- Initial version
----
- accel/tcg/user-exec.c             |   48 ++
- configure                         |   12 +-
- disas.c                           |   10 +-
- include/elf.h                     |   55 ++
- include/exec/poison.h             |    1 +
- linux-user/host/riscv32/hostdep.h |   15 +
- linux-user/host/riscv64/hostdep.h |   15 +
- tcg/riscv/tcg-target.h            |  172 ++++
- tcg/riscv/tcg-target.inc.c        | 1649 +++++++++++++++++++++++++++++++++++++
- 9 files changed, 1973 insertions(+), 4 deletions(-)
- create mode 100644 linux-user/host/riscv32/hostdep.h
- create mode 100644 linux-user/host/riscv64/hostdep.h
- create mode 100644 tcg/riscv/tcg-target.h
- create mode 100644 tcg/riscv/tcg-target.inc.c
-
 diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
-index 26a3ffbba1..66d4703590 100644
+index 26a3ffb..66d4703 100644
 --- a/accel/tcg/user-exec.c
 +++ b/accel/tcg/user-exec.c
 @@ -570,6 +570,54 @@ int cpu_signal_handler(int host_signum, void *pinfo,
@@ -163,10 +58,10 @@ index 26a3ffbba1..66d4703590 100644
  
  #error host CPU specific signal handler needed
 diff --git a/configure b/configure
-index 0a19b033bc..e598cbfa22 100755
+index 2a7796e..f9e4b10 100755
 --- a/configure
 +++ b/configure
-@@ -655,6 +655,12 @@ elif check_define __s390__ ; then
+@@ -700,6 +700,12 @@ elif check_define __s390__ ; then
    else
      cpu="s390"
    fi
@@ -179,7 +74,7 @@ index 0a19b033bc..e598cbfa22 100755
  elif check_define __arm__ ; then
    cpu="arm"
  elif check_define __aarch64__ ; then
-@@ -667,7 +673,7 @@ ARCH=
+@@ -712,7 +718,7 @@ ARCH=
  # Normalise host CPU name and set ARCH.
  # Note that this case should only have supported host CPUs, not guests.
  case "$cpu" in
@@ -187,8 +82,8 @@ index 0a19b033bc..e598cbfa22 100755
 +  ppc|ppc64|s390|s390x|sparc64|x32|riscv32|riscv64)
      cpu="$cpu"
      supported_cpu="yes"
-   ;;
+     eval "cross_cc_${cpu}=\$host_cc"
-@@ -6628,6 +6634,8 @@ elif test "$ARCH" = "x86_64" -o "$ARCH" = "x32" ; then
+@@ -6773,6 +6779,8 @@ elif test "$ARCH" = "x86_64" -o "$ARCH" = "x32" ; then
    QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg/i386 $QEMU_INCLUDES"
  elif test "$ARCH" = "ppc64" ; then
    QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg/ppc $QEMU_INCLUDES"
@@ -197,7 +92,7 @@ index 0a19b033bc..e598cbfa22 100755
  else
    QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg/\$(ARCH) $QEMU_INCLUDES"
  fi
-@@ -7042,7 +7050,7 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
+@@ -7265,7 +7273,7 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
    ppc*)
      disas_config "PPC"
    ;;
@@ -207,7 +102,7 @@ index 0a19b033bc..e598cbfa22 100755
    ;;
    s390*)
 diff --git a/disas.c b/disas.c
-index 5325b7e6be..82a408f272 100644
+index 5325b7e..82a408f 100644
 --- a/disas.c
 +++ b/disas.c
 @@ -522,8 +522,14 @@ void disas(FILE *out, void *code, unsigned long size)
@@ -228,7 +123,7 @@ index 5325b7e6be..82a408f272 100644
      print_insn = print_insn_arm_a64;
      s.info.cap_arch = CS_ARCH_ARM64;
 diff --git a/include/elf.h b/include/elf.h
-index c0dc9bb5fd..06b1cd2b6c 100644
+index 934dbbd..3b8b50b 100644
 --- a/include/elf.h
 +++ b/include/elf.h
 @@ -1285,6 +1285,61 @@ typedef struct {
@@ -294,7 +189,7 @@ index c0dc9bb5fd..06b1cd2b6c 100644
    Elf32_Addr	r_offset;
    Elf32_Word	r_info;
 diff --git a/include/exec/poison.h b/include/exec/poison.h
-index 41cd2eb1d8..79aec29071 100644
+index 41cd2eb..79aec29 100644
 --- a/include/exec/poison.h
 +++ b/include/exec/poison.h
 @@ -79,6 +79,7 @@
@@ -307,7 +202,7 @@ index 41cd2eb1d8..79aec29071 100644
  #pragma GCC poison CONFIG_SPARC_DIS
 diff --git a/linux-user/host/riscv32/hostdep.h b/linux-user/host/riscv32/hostdep.h
 new file mode 100644
-index 0000000000..d63dc57f93
+index 0000000..d63dc57
 --- /dev/null
 +++ b/linux-user/host/riscv32/hostdep.h
 @@ -0,0 +1,15 @@
@@ -328,7 +223,7 @@ index 0000000000..d63dc57f93
 +#endif
 diff --git a/linux-user/host/riscv64/hostdep.h b/linux-user/host/riscv64/hostdep.h
 new file mode 100644
-index 0000000000..4288410ef3
+index 0000000..4288410
 --- /dev/null
 +++ b/linux-user/host/riscv64/hostdep.h
 @@ -0,0 +1,15 @@
@@ -349,7 +244,7 @@ index 0000000000..4288410ef3
 +#endif
 diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
 new file mode 100644
-index 0000000000..8f81d2761a
+index 0000000..8f81d27
 --- /dev/null
 +++ b/tcg/riscv/tcg-target.h
 @@ -0,0 +1,172 @@
@@ -527,7 +422,7 @@ index 0000000000..8f81d2761a
 +#endif
 diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
 new file mode 100644
-index 0000000000..a67c6365e7
+index 0000000..a67c636
 --- /dev/null
 +++ b/tcg/riscv/tcg-target.inc.c
 @@ -0,0 +1,1649 @@

qemu.spec

@@ -105,7 +105,7 @@ Requires: %{name}-ui-sdl = %{epoch}:%{version}-%{release}
 Summary: QEMU is a FAST! processor emulator
 Name: qemu
 Version: 3.0.0
-Release: 1%{?rcrel}.0.riscv64%{?dist}
+Release: 1%{?rcrel}.1.riscv64%{?dist}
 Epoch: 2
 License: GPLv2 and BSD and MIT and CC-BY
 URL: http://www.qemu.org/
@@ -134,7 +134,7 @@ Source21: 95-kvm-ppc64-memlock.conf
 # riscv backend
 # Source: https://github.com/riscv/riscv-qemu/commit/0805ad337785f0cce29ecf162bad9e1c477051f3.patch
 # Development: https://github.com/riscv/riscv-qemu/commits/wip-riscv-tcg-backend
-Patch0: qemu-2.12.0-riscv64-backend.patch
+Patch0: qemu-3.0.0-riscv64-backend.patch
 
 # documentation deps
 BuildRequires: texinfo
@@ -1619,6 +1619,9 @@ getent passwd qemu >/dev/null || \
 
 
 %changelog
+* Tue Sep 11 2018 David Abdurachmanov <david.abdurachmanov@gmail.com> - 2:3.0.0-1.1.riscv64
+- Rebase backend patch
+
 * Mon Sep 10 2018 David Abdurachmanov <david.abdurachmanov@gmail.com> - 2:3.0.0-1.0.riscv64
 - Enable riscv64 as host