Rebase RISC-V (riscv64) backend patch
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
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7108702C938B13C1
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@ -1,110 +1,5 @@
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From 0805ad337785f0cce29ecf162bad9e1c477051f3 Mon Sep 17 00:00:00 2001
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From: Michael Clark <mjc@sifive.com>
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Date: Sat, 10 Mar 2018 16:34:09 -0800
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Subject: [PATCH] RISC-V: RISC-V TCG backend work in progress
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This patch adds an experimental RISC-V TCG backend.
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We have been dogfooding the RISC-V QEMU front-end with Fedora
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Linux to develop a RISC-V TCG backend. The RISC-V TCG backend
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can be built inside of the QEMU RISC-V 'virt' machine using
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the Fedora stage 4 disk image:
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- https://fedoraproject.org/wiki/Architectures/RISC-V
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Below are brief instructions on building riscv64-linux-user
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and x86_64-linux-user QEMU inside a Fedora RISC-V environment
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using either QEMU RISC-V or SiFive's HiFive Unleashed board:
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```
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sudo dnf install git python flex bison \
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zlib-devel glib2-devel pixman-devel
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git clone --recursive https://github.com/riscv/riscv-qemu.git
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cd riscv-qemu
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git checkout wip-riscv-tcg-backend
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./configure --enable-debug-tcg \
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--target-list=riscv64-linux-user,x86_64-linux-user
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make -j$(nproc)
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```
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Testing
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There is a user-mode version of riscv-tests that can
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be used for testing RISC-V QEMU linux-user.
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- https://github.com/arsv/riscv-qemu-tests
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These tests can also be used to test the RISC-V TCG
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back-end via the RISC-V front-end. e.g.
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```
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for ext in i m a f d; do
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for i in $(find rv64${ext} -type f -a -executable); do
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echo $i
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../riscv-qemu/riscv64-linux-user/qemu-riscv64 \
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--singlestep $i
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done
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done
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```
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At present all of the Base ISA tests pass, although TCG
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performs constant folding so test code can be eliminated
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by the TCG optimizer unless qemu is run with --singlestep.
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All of the rv8-bench tests compiled for riscv64 and x86_64
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run (using musl-libc via the musl-riscv-toolchain):
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- https://github.com/rv8-io/musl-riscv-toolchain/
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- https://github.com/rv8-io/rv8-bench/
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- https://rv8.io/bench
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Caveats:
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- No support for Oversize guests (64-bit target 32-bit host)
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(tcg_out_brcond2 and tcg_out_setcond2 are not implemented)
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- No support for Big-Endian (tcg_out_qemu_ld_direct and
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tcg_out_qemu_st_direct don't support MO_BSWAP)
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- Full system emulator (softmmu) support requires debugging
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Changelog
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v2
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- Update configure pattern for riscv disassembler
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- Fix jal range in tcg_out_jump_internal
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- Elide 64-bit far jump on rv32
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- Encode far jump lower 12 bits in jalr
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- Use jal for INDEX_op_br
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- Add movi support for 64-bit PC-relative constants
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- Don't emit 64-bit jumps on rv32
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- Fix TCG_CT_CONST_S12 and TCG_CT_CONST_N12 ranges
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- Fix address calculation in tcg_out_ldst
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- Always set guest_base if not softmmu
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- Detect stores in cpu_signal_handler
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- Implement ext8s/ext8u/ext16s/ext16u
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- Implement softmmu support (requires debugging)
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v1
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- Initial version
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---
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accel/tcg/user-exec.c | 48 ++
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configure | 12 +-
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disas.c | 10 +-
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include/elf.h | 55 ++
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include/exec/poison.h | 1 +
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linux-user/host/riscv32/hostdep.h | 15 +
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linux-user/host/riscv64/hostdep.h | 15 +
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tcg/riscv/tcg-target.h | 172 ++++
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tcg/riscv/tcg-target.inc.c | 1649 +++++++++++++++++++++++++++++++++++++
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9 files changed, 1973 insertions(+), 4 deletions(-)
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create mode 100644 linux-user/host/riscv32/hostdep.h
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create mode 100644 linux-user/host/riscv64/hostdep.h
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create mode 100644 tcg/riscv/tcg-target.h
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create mode 100644 tcg/riscv/tcg-target.inc.c
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diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
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index 26a3ffbba1..66d4703590 100644
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index 26a3ffb..66d4703 100644
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--- a/accel/tcg/user-exec.c
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+++ b/accel/tcg/user-exec.c
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@@ -570,6 +570,54 @@ int cpu_signal_handler(int host_signum, void *pinfo,
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@ -163,10 +58,10 @@ index 26a3ffbba1..66d4703590 100644
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#error host CPU specific signal handler needed
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diff --git a/configure b/configure
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index 0a19b033bc..e598cbfa22 100755
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index 2a7796e..f9e4b10 100755
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--- a/configure
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+++ b/configure
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@@ -655,6 +655,12 @@ elif check_define __s390__ ; then
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@@ -700,6 +700,12 @@ elif check_define __s390__ ; then
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else
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cpu="s390"
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fi
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@ -179,7 +74,7 @@ index 0a19b033bc..e598cbfa22 100755
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elif check_define __arm__ ; then
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cpu="arm"
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elif check_define __aarch64__ ; then
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@@ -667,7 +673,7 @@ ARCH=
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@@ -712,7 +718,7 @@ ARCH=
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# Normalise host CPU name and set ARCH.
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# Note that this case should only have supported host CPUs, not guests.
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case "$cpu" in
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@ -187,8 +82,8 @@ index 0a19b033bc..e598cbfa22 100755
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+ ppc|ppc64|s390|s390x|sparc64|x32|riscv32|riscv64)
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cpu="$cpu"
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supported_cpu="yes"
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;;
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@@ -6628,6 +6634,8 @@ elif test "$ARCH" = "x86_64" -o "$ARCH" = "x32" ; then
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eval "cross_cc_${cpu}=\$host_cc"
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@@ -6773,6 +6779,8 @@ elif test "$ARCH" = "x86_64" -o "$ARCH" = "x32" ; then
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QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg/i386 $QEMU_INCLUDES"
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elif test "$ARCH" = "ppc64" ; then
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QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg/ppc $QEMU_INCLUDES"
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@ -197,7 +92,7 @@ index 0a19b033bc..e598cbfa22 100755
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else
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QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg/\$(ARCH) $QEMU_INCLUDES"
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fi
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@@ -7042,7 +7050,7 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
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@@ -7265,7 +7273,7 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
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ppc*)
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disas_config "PPC"
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;;
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@ -207,7 +102,7 @@ index 0a19b033bc..e598cbfa22 100755
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;;
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s390*)
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diff --git a/disas.c b/disas.c
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index 5325b7e6be..82a408f272 100644
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index 5325b7e..82a408f 100644
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--- a/disas.c
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+++ b/disas.c
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@@ -522,8 +522,14 @@ void disas(FILE *out, void *code, unsigned long size)
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@ -228,7 +123,7 @@ index 5325b7e6be..82a408f272 100644
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print_insn = print_insn_arm_a64;
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s.info.cap_arch = CS_ARCH_ARM64;
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diff --git a/include/elf.h b/include/elf.h
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index c0dc9bb5fd..06b1cd2b6c 100644
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index 934dbbd..3b8b50b 100644
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--- a/include/elf.h
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+++ b/include/elf.h
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@@ -1285,6 +1285,61 @@ typedef struct {
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@ -294,7 +189,7 @@ index c0dc9bb5fd..06b1cd2b6c 100644
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Elf32_Addr r_offset;
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Elf32_Word r_info;
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diff --git a/include/exec/poison.h b/include/exec/poison.h
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index 41cd2eb1d8..79aec29071 100644
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index 41cd2eb..79aec29 100644
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--- a/include/exec/poison.h
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+++ b/include/exec/poison.h
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@@ -79,6 +79,7 @@
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@ -307,7 +202,7 @@ index 41cd2eb1d8..79aec29071 100644
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#pragma GCC poison CONFIG_SPARC_DIS
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diff --git a/linux-user/host/riscv32/hostdep.h b/linux-user/host/riscv32/hostdep.h
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new file mode 100644
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index 0000000000..d63dc57f93
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index 0000000..d63dc57
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--- /dev/null
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+++ b/linux-user/host/riscv32/hostdep.h
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@@ -0,0 +1,15 @@
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@ -328,7 +223,7 @@ index 0000000000..d63dc57f93
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+#endif
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diff --git a/linux-user/host/riscv64/hostdep.h b/linux-user/host/riscv64/hostdep.h
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new file mode 100644
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index 0000000000..4288410ef3
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index 0000000..4288410
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--- /dev/null
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+++ b/linux-user/host/riscv64/hostdep.h
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@@ -0,0 +1,15 @@
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@ -349,7 +244,7 @@ index 0000000000..4288410ef3
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+#endif
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diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
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new file mode 100644
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index 0000000000..8f81d2761a
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index 0000000..8f81d27
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--- /dev/null
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+++ b/tcg/riscv/tcg-target.h
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@@ -0,0 +1,172 @@
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@ -527,7 +422,7 @@ index 0000000000..8f81d2761a
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+#endif
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diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
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new file mode 100644
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index 0000000000..a67c6365e7
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index 0000000..a67c636
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--- /dev/null
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+++ b/tcg/riscv/tcg-target.inc.c
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@@ -0,0 +1,1649 @@
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@ -105,7 +105,7 @@ Requires: %{name}-ui-sdl = %{epoch}:%{version}-%{release}
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Summary: QEMU is a FAST! processor emulator
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Name: qemu
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Version: 3.0.0
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Release: 1%{?rcrel}.0.riscv64%{?dist}
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Release: 1%{?rcrel}.1.riscv64%{?dist}
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Epoch: 2
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License: GPLv2 and BSD and MIT and CC-BY
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URL: http://www.qemu.org/
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@ -134,7 +134,7 @@ Source21: 95-kvm-ppc64-memlock.conf
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# riscv backend
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# Source: https://github.com/riscv/riscv-qemu/commit/0805ad337785f0cce29ecf162bad9e1c477051f3.patch
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# Development: https://github.com/riscv/riscv-qemu/commits/wip-riscv-tcg-backend
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Patch0: qemu-2.12.0-riscv64-backend.patch
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Patch0: qemu-3.0.0-riscv64-backend.patch
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# documentation deps
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BuildRequires: texinfo
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@ -1619,6 +1619,9 @@ getent passwd qemu >/dev/null || \
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%changelog
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* Tue Sep 11 2018 David Abdurachmanov <david.abdurachmanov@gmail.com> - 2:3.0.0-1.1.riscv64
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- Rebase backend patch
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* Mon Sep 10 2018 David Abdurachmanov <david.abdurachmanov@gmail.com> - 2:3.0.0-1.0.riscv64
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- Enable riscv64 as host
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