138 lines
5.0 KiB
Diff
138 lines
5.0 KiB
Diff
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From 552720cea4c1ca99dd1919cb8a80b6b8f3b13cda Mon Sep 17 00:00:00 2001
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From: Aurelien Jarno <aurelien@aurel32.net>
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Date: Fri, 21 Sep 2012 18:20:26 +0200
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Subject: [PATCH] tcg/mips: implement movcond op on MIPS32R2
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movcond operation can be implemented on MIPS32 Release 2 using the MOVN,
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MOVZ, SLT and SLTU instructions.
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Reviewed-by: Richard Henderson <rth@twiddle.net>
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
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---
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tcg/mips/tcg-target.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++++++
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tcg/mips/tcg-target.h | 8 ++++++
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2 files changed, 77 insertions(+)
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diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
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index b2e1056..c272b38 100644
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--- a/tcg/mips/tcg-target.c
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+++ b/tcg/mips/tcg-target.c
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@@ -308,6 +308,8 @@ enum {
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OPC_SRAV = OPC_SPECIAL | 0x07,
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OPC_JR = OPC_SPECIAL | 0x08,
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OPC_JALR = OPC_SPECIAL | 0x09,
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+ OPC_MOVZ = OPC_SPECIAL | 0x0A,
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+ OPC_MOVN = OPC_SPECIAL | 0x0B,
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OPC_MFHI = OPC_SPECIAL | 0x10,
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OPC_MFLO = OPC_SPECIAL | 0x12,
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OPC_MULT = OPC_SPECIAL | 0x18,
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@@ -735,6 +737,68 @@ static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGArg arg1,
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reloc_pc16(label_ptr, (tcg_target_long) s->code_ptr);
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}
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+static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
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+ TCGArg c1, TCGArg c2, TCGArg v)
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+{
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+ switch (cond) {
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+ case TCG_COND_EQ:
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+ if (c1 == 0) {
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+ tcg_out_opc_reg(s, OPC_MOVZ, ret, v, c2);
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+ } else if (c2 == 0) {
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+ tcg_out_opc_reg(s, OPC_MOVZ, ret, v, c1);
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+ } else {
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+ tcg_out_opc_reg(s, OPC_XOR, TCG_REG_AT, c1, c2);
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+ tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT);
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+ }
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+ break;
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+ case TCG_COND_NE:
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+ if (c1 == 0) {
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+ tcg_out_opc_reg(s, OPC_MOVN, ret, v, c2);
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+ } else if (c2 == 0) {
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+ tcg_out_opc_reg(s, OPC_MOVN, ret, v, c1);
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+ } else {
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+ tcg_out_opc_reg(s, OPC_XOR, TCG_REG_AT, c1, c2);
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+ tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT);
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+ }
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+ break;
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+ case TCG_COND_LT:
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+ tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, c1, c2);
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+ tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT);
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+ break;
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+ case TCG_COND_LTU:
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+ tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, c1, c2);
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+ tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT);
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+ break;
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+ case TCG_COND_GE:
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+ tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, c1, c2);
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+ tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT);
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+ break;
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+ case TCG_COND_GEU:
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+ tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, c1, c2);
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+ tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT);
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+ break;
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+ case TCG_COND_LE:
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+ tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, c2, c1);
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+ tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT);
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+ break;
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+ case TCG_COND_LEU:
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+ tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, c2, c1);
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+ tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT);
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+ break;
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+ case TCG_COND_GT:
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+ tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, c2, c1);
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+ tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT);
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+ break;
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+ case TCG_COND_GTU:
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+ tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, c2, c1);
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+ tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT);
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+ break;
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+ default:
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+ tcg_abort();
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+ break;
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+ }
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+}
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+
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static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
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TCGArg arg1, TCGArg arg2)
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{
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@@ -1468,6 +1532,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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tcg_out_brcond2(s, args[4], args[0], args[1], args[2], args[3], args[5]);
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break;
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+ case INDEX_op_movcond_i32:
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+ tcg_out_movcond(s, args[5], args[0], args[1], args[2], args[3]);
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+ break;
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+
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case INDEX_op_setcond_i32:
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tcg_out_setcond(s, args[3], args[0], args[1], args[2]);
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break;
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@@ -1559,6 +1627,7 @@ static const TCGTargetOpDef mips_op_defs[] = {
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{ INDEX_op_deposit_i32, { "r", "0", "rZ" } },
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{ INDEX_op_brcond_i32, { "rZ", "rZ" } },
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+ { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "0" } },
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{ INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
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{ INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },
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diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
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index 897a737..d147e70 100644
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--- a/tcg/mips/tcg-target.h
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+++ b/tcg/mips/tcg-target.h
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@@ -86,7 +86,15 @@ typedef enum {
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#define TCG_TARGET_HAS_orc_i32 0
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#define TCG_TARGET_HAS_eqv_i32 0
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#define TCG_TARGET_HAS_nand_i32 0
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+
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+/* optional instructions only implemented on MIPS4, MIPS32 and Loongson 2 */
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+#if defined(_MIPS_ARCH_MIPS4) || defined(_MIPS_ARCH_MIPS32) || \
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+ defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_LOONGSON2E) || \
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+ defined(_MIPS_ARCH_LOONGSON2F)
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+#define TCG_TARGET_HAS_movcond_i32 1
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+#else
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#define TCG_TARGET_HAS_movcond_i32 0
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+#endif
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/* optional instructions only implemented on MIPS32R2 */
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#ifdef _MIPS_ARCH_MIPS32R2
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