179 lines
5.8 KiB
Diff
179 lines
5.8 KiB
Diff
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From 140048c58e4ceb4f3bac87d7154d2731bb2bcd5d Mon Sep 17 00:00:00 2001
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From: Blue Swirl <blauwirbel@gmail.com>
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Date: Tue, 4 Sep 2012 20:08:34 +0000
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Subject: [PATCH] target-arm: convert void helpers
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Add an explicit CPUState parameter instead of relying on AREG0.
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For easier review, convert only op helpers which don't return any value.
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Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
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---
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target-arm/helper.h | 8 ++++----
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target-arm/op_helper.c | 20 ++++++++++----------
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target-arm/translate.c | 8 ++++----
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3 files changed, 18 insertions(+), 18 deletions(-)
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diff --git a/target-arm/helper.h b/target-arm/helper.h
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index 21e9cfe..106aacd 100644
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--- a/target-arm/helper.h
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+++ b/target-arm/helper.h
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@@ -50,10 +50,10 @@ DEF_HELPER_2(usad8, i32, i32, i32)
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DEF_HELPER_1(logicq_cc, i32, i64)
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DEF_HELPER_3(sel_flags, i32, i32, i32, i32)
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-DEF_HELPER_1(exception, void, i32)
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-DEF_HELPER_0(wfi, void)
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+DEF_HELPER_2(exception, void, env, i32)
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+DEF_HELPER_1(wfi, void, env)
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-DEF_HELPER_2(cpsr_write, void, i32, i32)
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+DEF_HELPER_3(cpsr_write, void, env, i32, i32)
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DEF_HELPER_0(cpsr_read, i32)
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DEF_HELPER_3(v7m_msr, void, env, i32, i32)
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@@ -68,7 +68,7 @@ DEF_HELPER_2(get_r13_banked, i32, env, i32)
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DEF_HELPER_3(set_r13_banked, void, env, i32, i32)
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DEF_HELPER_1(get_user_reg, i32, i32)
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-DEF_HELPER_2(set_user_reg, void, i32, i32)
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+DEF_HELPER_3(set_user_reg, void, env, i32, i32)
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DEF_HELPER_1(vfp_get_fpscr, i32, env)
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DEF_HELPER_2(vfp_set_fpscr, void, env, i32)
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diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
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index d77bfab..b1adce3 100644
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--- a/target-arm/op_helper.c
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+++ b/target-arm/op_helper.c
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@@ -23,7 +23,7 @@
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#define SIGNBIT (uint32_t)0x80000000
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#define SIGNBIT64 ((uint64_t)1 << 63)
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-static void raise_exception(int tt)
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+static void raise_exception(CPUARMState *env, int tt)
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{
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env->exception_index = tt;
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cpu_loop_exit(env);
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@@ -93,7 +93,7 @@ void tlb_fill(CPUARMState *env1, target_ulong addr, int is_write, int mmu_idx,
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cpu_restore_state(tb, env, retaddr);
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}
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}
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- raise_exception(env->exception_index);
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+ raise_exception(env, env->exception_index);
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}
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env = saved_env;
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}
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@@ -230,14 +230,14 @@ uint32_t HELPER(usat16)(uint32_t x, uint32_t shift)
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return res;
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}
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-void HELPER(wfi)(void)
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+void HELPER(wfi)(CPUARMState *env)
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{
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env->exception_index = EXCP_HLT;
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env->halted = 1;
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cpu_loop_exit(env);
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}
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-void HELPER(exception)(uint32_t excp)
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+void HELPER(exception)(CPUARMState *env, uint32_t excp)
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{
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env->exception_index = excp;
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cpu_loop_exit(env);
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@@ -248,7 +248,7 @@ uint32_t HELPER(cpsr_read)(void)
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return cpsr_read(env) & ~CPSR_EXEC;
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}
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-void HELPER(cpsr_write)(uint32_t val, uint32_t mask)
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+void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
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{
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cpsr_write(env, val, mask);
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}
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@@ -271,7 +271,7 @@ uint32_t HELPER(get_user_reg)(uint32_t regno)
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return val;
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}
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-void HELPER(set_user_reg)(uint32_t regno, uint32_t val)
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+void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val)
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{
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if (regno == 13) {
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env->banked_r13[0] = val;
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@@ -290,7 +290,7 @@ void HELPER(set_cp_reg)(CPUARMState *env, void *rip, uint32_t value)
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const ARMCPRegInfo *ri = rip;
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int excp = ri->writefn(env, ri, value);
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if (excp) {
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- raise_exception(excp);
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+ raise_exception(env, excp);
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}
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}
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@@ -300,7 +300,7 @@ uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip)
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uint64_t value;
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int excp = ri->readfn(env, ri, &value);
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if (excp) {
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- raise_exception(excp);
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+ raise_exception(env, excp);
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}
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return value;
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}
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@@ -310,7 +310,7 @@ void HELPER(set_cp_reg64)(CPUARMState *env, void *rip, uint64_t value)
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const ARMCPRegInfo *ri = rip;
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int excp = ri->writefn(env, ri, value);
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if (excp) {
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- raise_exception(excp);
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+ raise_exception(env, excp);
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}
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}
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@@ -320,7 +320,7 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
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uint64_t value;
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int excp = ri->readfn(env, ri, &value);
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if (excp) {
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- raise_exception(excp);
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+ raise_exception(env, excp);
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}
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return value;
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}
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diff --git a/target-arm/translate.c b/target-arm/translate.c
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index edef79a..6f651d9 100644
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--- a/target-arm/translate.c
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+++ b/target-arm/translate.c
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@@ -199,7 +199,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
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static inline void gen_set_cpsr(TCGv var, uint32_t mask)
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{
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TCGv tmp_mask = tcg_const_i32(mask);
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- gen_helper_cpsr_write(var, tmp_mask);
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+ gen_helper_cpsr_write(cpu_env, var, tmp_mask);
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tcg_temp_free_i32(tmp_mask);
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}
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/* Set NZCV flags from the high 4 bits of var. */
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@@ -209,7 +209,7 @@ static void gen_exception(int excp)
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{
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TCGv tmp = tcg_temp_new_i32();
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tcg_gen_movi_i32(tmp, excp);
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- gen_helper_exception(tmp);
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+ gen_helper_exception(cpu_env, tmp);
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tcg_temp_free_i32(tmp);
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}
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@@ -7719,7 +7719,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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tmp = gen_ld32(addr, IS_USER(s));
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if (user) {
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tmp2 = tcg_const_i32(i);
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- gen_helper_set_user_reg(tmp2, tmp);
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+ gen_helper_set_user_reg(cpu_env, tmp2, tmp);
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tcg_temp_free_i32(tmp2);
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tcg_temp_free_i32(tmp);
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} else if (i == rn) {
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@@ -9913,7 +9913,7 @@ static inline void gen_intermediate_code_internal(CPUARMState *env,
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/* nothing more to generate */
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break;
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case DISAS_WFI:
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- gen_helper_wfi();
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+ gen_helper_wfi(cpu_env);
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break;
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case DISAS_SWI:
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gen_exception(EXCP_SWI);
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