2012-10-28 18:05:07 +00:00
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From 608a36df28b4db83124d06081029023e01901fc9 Mon Sep 17 00:00:00 2001
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From: "Maciej W. Rozycki" <macro@codesourcery.com>
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Date: Fri, 8 Jun 2012 02:04:40 +0100
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Subject: [PATCH] MIPS/user: Fix reset CPU state initialization
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This change updates the CPU reset sequence to use a common piece of code
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that figures out CPU state flags, fixing the problem with MIPS_HFLAG_COP1X
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not being set where applicable that causes floating-point MADD family
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instructions (and other instructions from the MIPS IV FP subset) to trap.
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As compute_hflags is now shared between op_helper.c and translate.c, the
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function is now moved to a common header. There are no changes to this
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function.
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The problem was seen with the 24Kf MIPS32r2 processor in user emulation.
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The new approach prevents system and user emulation from diverging -- all
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the hflags state is initialized in one place now.
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Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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(cherry picked from commit 03e6e5017757645f00b2f3b4f3a257973985e455)
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Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
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---
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target-mips/cpu.h | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
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target-mips/op_helper.c | 49 -------------------------------------------------
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target-mips/translate.c | 16 +++-------------
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3 files changed, 52 insertions(+), 62 deletions(-)
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diff --git a/target-mips/cpu.h b/target-mips/cpu.h
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index be4f805..b7a5112 100644
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--- a/target-mips/cpu.h
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+++ b/target-mips/cpu.h
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@@ -742,4 +742,53 @@ static inline void cpu_pc_from_tb(CPUMIPSState *env, TranslationBlock *tb)
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env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
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}
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+static inline void compute_hflags(CPUMIPSState *env)
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+{
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+ env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
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+ MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
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+ MIPS_HFLAG_UX);
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+ if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
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+ !(env->CP0_Status & (1 << CP0St_ERL)) &&
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+ !(env->hflags & MIPS_HFLAG_DM)) {
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+ env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
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+ }
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+#if defined(TARGET_MIPS64)
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+ if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
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+ (env->CP0_Status & (1 << CP0St_PX)) ||
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+ (env->CP0_Status & (1 << CP0St_UX))) {
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+ env->hflags |= MIPS_HFLAG_64;
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+ }
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+ if (env->CP0_Status & (1 << CP0St_UX)) {
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+ env->hflags |= MIPS_HFLAG_UX;
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+ }
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+#endif
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+ if ((env->CP0_Status & (1 << CP0St_CU0)) ||
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+ !(env->hflags & MIPS_HFLAG_KSU)) {
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+ env->hflags |= MIPS_HFLAG_CP0;
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+ }
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+ if (env->CP0_Status & (1 << CP0St_CU1)) {
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+ env->hflags |= MIPS_HFLAG_FPU;
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+ }
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+ if (env->CP0_Status & (1 << CP0St_FR)) {
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+ env->hflags |= MIPS_HFLAG_F64;
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+ }
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+ if (env->insn_flags & ISA_MIPS32R2) {
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+ if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
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+ env->hflags |= MIPS_HFLAG_COP1X;
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+ }
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+ } else if (env->insn_flags & ISA_MIPS32) {
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+ if (env->hflags & MIPS_HFLAG_64) {
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+ env->hflags |= MIPS_HFLAG_COP1X;
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+ }
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+ } else if (env->insn_flags & ISA_MIPS4) {
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+ /* All supported MIPS IV CPUs use the XX (CU3) to enable
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+ and disable the MIPS IV extensions to the MIPS III ISA.
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+ Some other MIPS IV CPUs ignore the bit, so the check here
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+ would be too restrictive for them. */
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+ if (env->CP0_Status & (1 << CP0St_CU3)) {
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+ env->hflags |= MIPS_HFLAG_COP1X;
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+ }
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+ }
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+}
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+
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#endif /* !defined (__MIPS_CPU_H__) */
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diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
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index d2a8a55..ce5ddaf 100644
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--- a/target-mips/op_helper.c
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+++ b/target-mips/op_helper.c
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@@ -30,55 +30,6 @@
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static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
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#endif
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-static inline void compute_hflags(CPUMIPSState *env)
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-{
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- env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
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- MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
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- MIPS_HFLAG_UX);
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- if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
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- !(env->CP0_Status & (1 << CP0St_ERL)) &&
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- !(env->hflags & MIPS_HFLAG_DM)) {
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- env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
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- }
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-#if defined(TARGET_MIPS64)
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- if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
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- (env->CP0_Status & (1 << CP0St_PX)) ||
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- (env->CP0_Status & (1 << CP0St_UX))) {
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- env->hflags |= MIPS_HFLAG_64;
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- }
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- if (env->CP0_Status & (1 << CP0St_UX)) {
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- env->hflags |= MIPS_HFLAG_UX;
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- }
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-#endif
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- if ((env->CP0_Status & (1 << CP0St_CU0)) ||
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- !(env->hflags & MIPS_HFLAG_KSU)) {
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- env->hflags |= MIPS_HFLAG_CP0;
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- }
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- if (env->CP0_Status & (1 << CP0St_CU1)) {
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- env->hflags |= MIPS_HFLAG_FPU;
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- }
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- if (env->CP0_Status & (1 << CP0St_FR)) {
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- env->hflags |= MIPS_HFLAG_F64;
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- }
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- if (env->insn_flags & ISA_MIPS32R2) {
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- if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
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- env->hflags |= MIPS_HFLAG_COP1X;
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- }
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- } else if (env->insn_flags & ISA_MIPS32) {
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- if (env->hflags & MIPS_HFLAG_64) {
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- env->hflags |= MIPS_HFLAG_COP1X;
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- }
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- } else if (env->insn_flags & ISA_MIPS4) {
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- /* All supported MIPS IV CPUs use the XX (CU3) to enable
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- and disable the MIPS IV extensions to the MIPS III ISA.
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- Some other MIPS IV CPUs ignore the bit, so the check here
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- would be too restrictive for them. */
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- if (env->CP0_Status & (1 << CP0St_CU3)) {
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- env->hflags |= MIPS_HFLAG_COP1X;
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- }
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- }
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-}
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-
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/*****************************************************************************/
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/* Exceptions processing helpers */
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diff --git a/target-mips/translate.c b/target-mips/translate.c
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index aba7935..4e04e97 100644
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--- a/target-mips/translate.c
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+++ b/target-mips/translate.c
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@@ -12816,18 +12816,13 @@ void cpu_state_reset(CPUMIPSState *env)
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env->insn_flags = env->cpu_model->insn_flags;
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#if defined(CONFIG_USER_ONLY)
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- env->hflags = MIPS_HFLAG_UM;
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+ env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU);
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/* Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR
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hardware registers. */
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env->CP0_HWREna |= 0x0000000F;
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if (env->CP0_Config1 & (1 << CP0C1_FP)) {
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- env->hflags |= MIPS_HFLAG_FPU;
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+ env->CP0_Status |= (1 << CP0St_CU1);
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}
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-#ifdef TARGET_MIPS64
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- if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
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- env->hflags |= MIPS_HFLAG_F64;
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- }
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-#endif
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#else
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if (env->hflags & MIPS_HFLAG_BMASK) {
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/* If the exception was raised from a delay slot,
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@@ -12857,7 +12852,6 @@ void cpu_state_reset(CPUMIPSState *env)
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}
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/* Count register increments in debug mode, EJTAG version 1 */
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env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
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- env->hflags = MIPS_HFLAG_CP0;
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if (env->CP0_Config3 & (1 << CP0C3_MT)) {
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int i;
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@@ -12885,11 +12879,7 @@ void cpu_state_reset(CPUMIPSState *env)
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}
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}
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#endif
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-#if defined(TARGET_MIPS64)
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- if (env->cpu_model->insn_flags & ISA_MIPS3) {
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- env->hflags |= MIPS_HFLAG_64;
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- }
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-#endif
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+ compute_hflags(env);
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env->exception_index = EXCP_NONE;
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}
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--
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2012-12-16 23:27:22 +00:00
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1.8.0.2
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2012-10-28 18:05:07 +00:00
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