39 lines
1.5 KiB
Diff
39 lines
1.5 KiB
Diff
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From e6cd59a324a330fe7fd50f3b91df4f34ad2ea111 Mon Sep 17 00:00:00 2001
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From: Aurelien Jarno <aurelien@aurel32.net>
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Date: Wed, 14 Nov 2012 15:04:42 +0100
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Subject: [PATCH] mips/malta: fix CBUS UART interrupt pin
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According to the MIPS Malta Developement Platform User's Manual, the
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i8259 interrupt controller is supposed to be connected to the hardware
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IRQ0, and the CBUS UART to the hardware interrupt 2.
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In QEMU they are both connected to hardware interrupt 0, the CBUS UART
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interrupt being wrong. This patch fixes that. It should be noted that
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the irq array in QEMU includes the software interrupts, hence
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env->irq[2] is the first hardware interrupt.
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Cc: Ralf Baechle <ralf@linux-mips.org>
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Reviewed-by: Eric Johnson <ericj@mips.com>
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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(cherry picked from commit 68d001928b151a0c50f367c0bdca645b3d5e9ed3)
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Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
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---
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hw/mips_malta.c | 3 ++-
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1 file changed, 2 insertions(+), 1 deletion(-)
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diff --git a/hw/mips_malta.c b/hw/mips_malta.c
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index ad23f26..9289a28 100644
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--- a/hw/mips_malta.c
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+++ b/hw/mips_malta.c
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@@ -860,7 +860,8 @@ void mips_malta_init (ram_addr_t ram_size,
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be = 0;
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#endif
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/* FPGA */
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- malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[2], serial_hds[2]);
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+ /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */
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+ malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[4], serial_hds[2]);
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/* Load firmware in flash / BIOS. */
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dinfo = drive_get(IF_PFLASH, 0, fl_idx);
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