90 lines
3.4 KiB
Diff
90 lines
3.4 KiB
Diff
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From d19858a5515cd15dabf88b8f180754c1c3f3eb76 Mon Sep 17 00:00:00 2001
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From: Aurelien Jarno <aurelien@aurel32.net>
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Date: Fri, 21 Sep 2012 18:20:26 +0200
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Subject: [PATCH] tcg/mips: implement rotl/rotr ops on MIPS32R2
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rotr operations can be optimized on MIPS32 Release 2 using the ROTR and
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ROTRV instructions. Also implemented rotl operations by subtracting the
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shift from 32.
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Reviewed-by: Richard Henderson <rth@twiddle.net>
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
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---
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tcg/mips/tcg-target.c | 20 ++++++++++++++++++++
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tcg/mips/tcg-target.h | 3 ++-
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2 files changed, 22 insertions(+), 1 deletion(-)
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diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
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index 8b2f9fc..592e42a 100644
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--- a/tcg/mips/tcg-target.c
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+++ b/tcg/mips/tcg-target.c
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@@ -300,9 +300,11 @@ enum {
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OPC_SPECIAL = 0x00 << 26,
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OPC_SLL = OPC_SPECIAL | 0x00,
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OPC_SRL = OPC_SPECIAL | 0x02,
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+ OPC_ROTR = OPC_SPECIAL | (0x01 << 21) | 0x02,
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OPC_SRA = OPC_SPECIAL | 0x03,
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OPC_SLLV = OPC_SPECIAL | 0x04,
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OPC_SRLV = OPC_SPECIAL | 0x06,
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+ OPC_ROTRV = OPC_SPECIAL | (0x01 << 6) | 0x06,
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OPC_SRAV = OPC_SPECIAL | 0x07,
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OPC_JR = OPC_SPECIAL | 0x08,
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OPC_JALR = OPC_SPECIAL | 0x09,
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@@ -1420,6 +1422,22 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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tcg_out_opc_reg(s, OPC_SRLV, args[0], args[2], args[1]);
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}
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break;
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+ case INDEX_op_rotl_i32:
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+ if (const_args[2]) {
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+ tcg_out_opc_sa(s, OPC_ROTR, args[0], args[1], 0x20 - args[2]);
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+ } else {
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+ tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_AT, 32);
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+ tcg_out_opc_reg(s, OPC_SUBU, TCG_REG_AT, TCG_REG_AT, args[2]);
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+ tcg_out_opc_reg(s, OPC_ROTRV, args[0], TCG_REG_AT, args[1]);
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+ }
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+ break;
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+ case INDEX_op_rotr_i32:
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+ if (const_args[2]) {
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+ tcg_out_opc_sa(s, OPC_ROTR, args[0], args[1], args[2]);
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+ } else {
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+ tcg_out_opc_reg(s, OPC_ROTRV, args[0], args[2], args[1]);
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+ }
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+ break;
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/* The bswap routines do not work on non-R2 CPU. In that case
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we let TCG generating the corresponding code. */
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@@ -1523,6 +1541,8 @@ static const TCGTargetOpDef mips_op_defs[] = {
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{ INDEX_op_shl_i32, { "r", "rZ", "ri" } },
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{ INDEX_op_shr_i32, { "r", "rZ", "ri" } },
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{ INDEX_op_sar_i32, { "r", "rZ", "ri" } },
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+ { INDEX_op_rotr_i32, { "r", "rZ", "ri" } },
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+ { INDEX_op_rotl_i32, { "r", "rZ", "ri" } },
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{ INDEX_op_bswap16_i32, { "r", "r" } },
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{ INDEX_op_bswap32_i32, { "r", "r" } },
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diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
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index c5c13f7..470314c 100644
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--- a/tcg/mips/tcg-target.h
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+++ b/tcg/mips/tcg-target.h
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@@ -80,7 +80,6 @@ typedef enum {
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#define TCG_TARGET_HAS_div_i32 1
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#define TCG_TARGET_HAS_not_i32 1
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#define TCG_TARGET_HAS_nor_i32 1
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-#define TCG_TARGET_HAS_rot_i32 0
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#define TCG_TARGET_HAS_ext8s_i32 1
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#define TCG_TARGET_HAS_ext16s_i32 1
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#define TCG_TARGET_HAS_andc_i32 0
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@@ -94,9 +93,11 @@ typedef enum {
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#ifdef _MIPS_ARCH_MIPS32R2
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#define TCG_TARGET_HAS_bswap16_i32 1
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#define TCG_TARGET_HAS_bswap32_i32 1
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+#define TCG_TARGET_HAS_rot_i32 1
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#else
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#define TCG_TARGET_HAS_bswap16_i32 0
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#define TCG_TARGET_HAS_bswap32_i32 0
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+#define TCG_TARGET_HAS_rot_i32 0
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#endif
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/* optional instructions automatically implemented */
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