From 1f40c0cbd186c2743dc30c3bad6773b8d49e7902 Mon Sep 17 00:00:00 2001 From: Charalampos Stratakis Date: Tue, 1 Nov 2016 15:05:11 +0100 Subject: [PATCH] Remove --with-tsc configure flag as it has been removed upstream. Also removing patch 143 related to that flag. Relevant upstream commit: https://hg.python.org/cpython/rev/2310a5b75fae --- 00143-tsc-on-ppc.patch | 58 ------------------------------------------ python3.spec | 9 +------ 2 files changed, 1 insertion(+), 66 deletions(-) delete mode 100644 00143-tsc-on-ppc.patch diff --git a/00143-tsc-on-ppc.patch b/00143-tsc-on-ppc.patch deleted file mode 100644 index 7d3e876..0000000 --- a/00143-tsc-on-ppc.patch +++ /dev/null @@ -1,58 +0,0 @@ -diff -up Python-2.7.2/Python/ceval.c.tsc-on-ppc Python-2.7.2/Python/ceval.c ---- Python-2.7.2/Python/ceval.c.tsc-on-ppc 2011-08-23 14:59:48.051300849 -0400 -+++ Python-2.7.2/Python/ceval.c 2011-08-23 15:33:25.412162902 -0400 -@@ -37,24 +37,42 @@ typedef unsigned long long uint64; - */ - #if defined(__ppc__) || defined (__powerpc__) - --#define READ_TIMESTAMP(var) ppc_getcounter(&var) -+#if defined( __powerpc64__) || defined(__LP64__) -+/* 64-bit PowerPC */ -+#define READ_TIMESTAMP(var) ppc64_getcounter(&var) -+static void -+ppc64_getcounter(uint64 *v) -+{ -+ /* On 64-bit PowerPC we can read the 64-bit timebase directly into a -+ 64-bit register */ -+ uint64 timebase; -+#ifdef _ARCH_PWR4 -+ asm volatile ("mfspr %0,268" : "=r" (timebase)); -+#else -+ asm volatile ("mftb %0" : "=r" (timebase)); -+#endif -+ *v = timebase; -+} -+ -+#else -+/* 32-bit PowerPC */ -+#define READ_TIMESTAMP(var) ppc32_getcounter(&var) - - static void --ppc_getcounter(uint64 *v) -+ppc32_getcounter(uint64 *v) - { -- unsigned long tbu, tb, tbu2; -+ union { long long ll; long ii[2]; } u; -+ long tmp; - - loop: -- asm volatile ("mftbu %0" : "=r" (tbu) ); -- asm volatile ("mftb %0" : "=r" (tb) ); -- asm volatile ("mftbu %0" : "=r" (tbu2)); -- if (__builtin_expect(tbu != tbu2, 0)) goto loop; -- -- /* The slightly peculiar way of writing the next lines is -- compiled better by GCC than any other way I tried. */ -- ((long*)(v))[0] = tbu; -- ((long*)(v))[1] = tb; -+ asm volatile ("mftbu %0" : "=r" (u.ii[0]) ); -+ asm volatile ("mftb %0" : "=r" (u.ii[1]) ); -+ asm volatile ("mftbu %0" : "=r" (tmp)); -+ if (__builtin_expect(u.ii[0] != tmp, 0)) goto loop; -+ -+ *v = u.ll; - } -+#endif /* powerpc 32/64 bit */ - - #elif defined(__i386__) - diff --git a/python3.spec b/python3.spec index 6d3ef9b..ad3399b 100644 --- a/python3.spec +++ b/python3.spec @@ -258,12 +258,6 @@ Patch132: 00132-add-rpmbuild-hooks-to-unittest.patch # Some tests within distutils fail when run in an rpmbuild: Patch137: 00137-skip-distutils-tests-that-fail-in-rpmbuild.patch -# 00143 # -# Fix the --with-tsc option on ppc64, and rework it on 32-bit ppc to avoid -# aliasing violations (rhbz#698726) -# Sent upstream as http://bugs.python.org/issue12872 -Patch143: 00143-tsc-on-ppc.patch - # 00146 # # Support OpenSSL FIPS mode (e.g. when OPENSSL_FORCE_FIPS_MODE=1 is set) # - handle failures from OpenSSL (e.g. on attempts to use MD5 in a @@ -613,7 +607,6 @@ sed -r -i s/'_PIP_VERSION = "[0-9.]+"'/'_PIP_VERSION = "%{pip_version}"'/ Lib/en %patch111 -p1 %patch132 -p1 %patch137 -p1 -#patch143 -p1 -b .tsc-on-ppc #patch146 -p1 %patch155 -p1 %patch157 -p1 @@ -719,7 +712,7 @@ BuildPython debug \ python-debug \ python%{pybasever}-debug \ %ifarch %{ix86} x86_64 ppc %{power64} - "--with-pydebug --with-tsc --without-ensurepip" \ + "--with-pydebug --without-ensurepip" \ %else "--with-pydebug --without-ensurepip" \ %endif