59 lines
1.7 KiB
Diff
59 lines
1.7 KiB
Diff
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diff -up Python-2.7.2/Python/ceval.c.tsc-on-ppc Python-2.7.2/Python/ceval.c
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--- Python-2.7.2/Python/ceval.c.tsc-on-ppc 2011-08-23 14:59:48.051300849 -0400
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+++ Python-2.7.2/Python/ceval.c 2011-08-23 15:33:25.412162902 -0400
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@@ -37,24 +37,42 @@ typedef unsigned long long uint64;
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*/
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#if defined(__ppc__) || defined (__powerpc__)
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-#define READ_TIMESTAMP(var) ppc_getcounter(&var)
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+#if defined( __powerpc64__) || defined(__LP64__)
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+/* 64-bit PowerPC */
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+#define READ_TIMESTAMP(var) ppc64_getcounter(&var)
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+static void
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+ppc64_getcounter(uint64 *v)
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+{
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+ /* On 64-bit PowerPC we can read the 64-bit timebase directly into a
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+ 64-bit register */
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+ uint64 timebase;
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+#ifdef _ARCH_PWR4
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+ asm volatile ("mfspr %0,268" : "=r" (timebase));
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+#else
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+ asm volatile ("mftb %0" : "=r" (timebase));
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+#endif
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+ *v = timebase;
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+}
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+
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+#else
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+/* 32-bit PowerPC */
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+#define READ_TIMESTAMP(var) ppc32_getcounter(&var)
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static void
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-ppc_getcounter(uint64 *v)
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+ppc32_getcounter(uint64 *v)
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{
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- register unsigned long tbu, tb, tbu2;
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+ union { long long ll; long ii[2]; } u;
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+ long tmp;
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loop:
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- asm volatile ("mftbu %0" : "=r" (tbu) );
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- asm volatile ("mftb %0" : "=r" (tb) );
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- asm volatile ("mftbu %0" : "=r" (tbu2));
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- if (__builtin_expect(tbu != tbu2, 0)) goto loop;
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-
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- /* The slightly peculiar way of writing the next lines is
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- compiled better by GCC than any other way I tried. */
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- ((long*)(v))[0] = tbu;
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- ((long*)(v))[1] = tb;
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+ asm volatile ("mftbu %0" : "=r" (u.ii[0]) );
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+ asm volatile ("mftb %0" : "=r" (u.ii[1]) );
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+ asm volatile ("mftbu %0" : "=r" (tmp));
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+ if (__builtin_expect(u.ii[0] != tmp, 0)) goto loop;
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+
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+ *v = u.ll;
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}
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+#endif /* powerpc 32/64 bit */
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#elif defined(__i386__)
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