From 870c83a103e64e4b520a07968cf99fdbcb2d43ce Mon Sep 17 00:00:00 2001
From: David Abdurachmanov <davidlt@rivosinc.com>
Date: Mon, 11 Sep 2023 11:00:18 +0300
Subject: [PATCH] Add is_riscv() support

Signed-off-by: David Abdurachmanov <davidlt@rivosinc.com>
---
 ...7139efb7f8c7d452f75d4ce7937e1804e8e1.patch | 41 +++++++++++++++++++
 python-blivet.spec                            |  7 +++-
 2 files changed, 47 insertions(+), 1 deletion(-)
 create mode 100644 f2437139efb7f8c7d452f75d4ce7937e1804e8e1.patch

diff --git a/f2437139efb7f8c7d452f75d4ce7937e1804e8e1.patch b/f2437139efb7f8c7d452f75d4ce7937e1804e8e1.patch
new file mode 100644
index 0000000..415fd27
--- /dev/null
+++ b/f2437139efb7f8c7d452f75d4ce7937e1804e8e1.patch
@@ -0,0 +1,41 @@
+From f2437139efb7f8c7d452f75d4ce7937e1804e8e1 Mon Sep 17 00:00:00 2001
+From: Nikita ROUSSEAU <48907457+nirousseau@users.noreply.github.com>
+Date: Thu, 18 May 2023 20:11:25 +0000
+Subject: [PATCH] Add RISCV64 architecture helper [is_riscv64()] for arch
+ module.
+
+This merge request is required to keep the pyAnaconda code clean at https://github.com/rhinstaller/anaconda/blob/master/pyanaconda/modules/storage/platform.py#L493
+The idea is to explicty call the blivet.arch.is_riscv64() helper in the switch/case in order to correctly determine riscv64 architecture for pyAnaconda.
+---
+ blivet/arch.py | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/blivet/arch.py b/blivet/arch.py
+index c18dcfa4c..6c2a584e3 100644
+--- a/blivet/arch.py
++++ b/blivet/arch.py
+@@ -349,6 +349,15 @@ def is_arm():
+     return os.uname()[4].startswith('arm')
+ 
+ 
++def is_riscv64():
++    """
++    :return: True if the hardware supports RISCV64, False otherwise.
++    :rtype: boolean
++
++    """
++    return os.uname()[4] == 'riscv64'
++
++
+ def is_loongarch(bits=None):
+     """
+     :return: True if the hardware supports loongarch, False otherwise.
+@@ -405,6 +414,8 @@ def get_arch():
+         return 'alpha'
+     elif is_arm():
+         return 'arm'
++    elif is_riscv64():
++        return 'riscv64'
+     elif is_loongarch(bits=32):
+         return 'loongarch32'
+     elif is_loongarch(bits=64):
diff --git a/python-blivet.spec b/python-blivet.spec
index 63e3961..a9d3dae 100644
--- a/python-blivet.spec
+++ b/python-blivet.spec
@@ -23,7 +23,7 @@ Version: 3.7.1
 
 #%%global prerelease .b2
 # prerelease, if defined, should be something like .a1, .b1, .b2.dev1, or .c2
-Release: 1%{?prerelease}%{?dist}
+Release: 1%{?prerelease}.0.riscv64%{?dist}
 Epoch: 1
 License: LGPL-2.1-or-later
 %global realname blivet
@@ -35,6 +35,8 @@ Source1: http://github.com/storaged-project/blivet/archive/%{realname}-%{realver
 Patch0: 0001-remove-btrfs-plugin.patch
 %endif
 
+Patch9: f2437139efb7f8c7d452f75d4ce7937e1804e8e1.patch
+
 # Versions of required components (done so we make sure the buildrequires
 # match the requires versions of things).
 %global partedver 1.8.1
@@ -196,6 +198,9 @@ configuration.
 %endif
 
 %changelog
+* Mon Sep 11 2023 David Abdurachmanov <davidlt@rivosinc.com> - 3.7.1-1.0.riscv64
+- Add is_riscv64() support
+
 * Thu Mar 16 2023 Vojtech Trefny <vtrefny@redhat.com> - 3.7.1-1
 - Fix the get_mount_device function (vponcova)
 - Prefer using UUID for the kickstart --onpart argument (vtrefny)