50 lines
2.3 KiB
Diff
50 lines
2.3 KiB
Diff
# HG changeset patch
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# User Armin Rigo <arigo@tunes.org>
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# Date 1571380165 -7200
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# Node ID d81c769a235307f6671a8fa916f48d6896cbb823
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# Parent f27546b858f97bfa286a891e1474579759028784
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Arguably, clarify the logic. The real motivation is a gcc bug, see issue #3086
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diff --git a/rpython/jit/backend/aarch64/opassembler.py b/rpython/jit/backend/aarch64/opassembler.py
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--- a/rpython/jit/backend/aarch64/opassembler.py
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+++ b/rpython/jit/backend/aarch64/opassembler.py
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@@ -808,9 +808,7 @@
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# Inline a series of STR operations, starting at 'dstaddr_loc'.
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#
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self.mc.gen_load_int(r.ip0.value, 0)
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- i = 0
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- adjustment = 0
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- needs_adjustment = itemsize < 8 and (startbyte % 8)
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+ i = dst_i = 0
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total_size = size_box.getint()
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while i < total_size:
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sz = itemsize
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@@ -818,19 +816,19 @@
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next_group += 8
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if next_group <= total_size:
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sz = 8
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+ if dst_i % 8: # unaligned?
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+ self.mc.ADD_ri(dstaddr_loc.value, dstaddr_loc.value, dst_i)
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+ dst_i = 0
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if sz == 8:
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- if needs_adjustment:
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- self.mc.ADD_ri(dstaddr_loc.value, dstaddr_loc.value, i)
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- adjustment = -i
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- needs_adjustment = False
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- self.mc.STR_ri(r.ip0.value, dstaddr_loc.value, i + adjustment)
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+ self.mc.STR_ri(r.ip0.value, dstaddr_loc.value, dst_i)
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elif sz == 4:
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- self.mc.STRW_ri(r.ip0.value, dstaddr_loc.value, i + adjustment)
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+ self.mc.STRW_ri(r.ip0.value, dstaddr_loc.value, dst_i)
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elif sz == 2:
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- self.mc.STRH_ri(r.ip0.value, dstaddr_loc.value, i + adjustment)
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+ self.mc.STRH_ri(r.ip0.value, dstaddr_loc.value, dst_i)
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else:
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- self.mc.STRB_ri(r.ip0.value, dstaddr_loc.value, i + adjustment)
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+ self.mc.STRB_ri(r.ip0.value, dstaddr_loc.value, dst_i)
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i += sz
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+ dst_i += sz
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else:
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if isinstance(size_box, ConstInt):
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