papi/papi-5.6.0-riscv64.patch

100 lines
2.9 KiB
Diff

diff --git a/src/configure b/src/configure
index 3d05182..357b874 100755
--- a/src/configure
+++ b/src/configure
@@ -4628,7 +4628,7 @@ _ACEOF
# First set pthread-mutexes based on arch
case $arch in
- aarch64|arm*)
+ aarch64|arm*|riscv*)
pthread_mutexes=yes
CFLAGS="$CFLAGS -DUSE_PTHREAD_MUTEXES"
echo "forcing use of pthread mutexes... " >&6
diff --git a/src/configure.in b/src/configure.in
index cff36bc..697c317 100644
--- a/src/configure.in
+++ b/src/configure.in
@@ -378,7 +378,7 @@ AC_DEFINE_UNQUOTED(CPU,$CPU,[cpu type])
# First set pthread-mutexes based on arch
case $arch in
- aarch64|arm*)
+ aarch64|arm*|riscv*)
pthread_mutexes=yes
CFLAGS="$CFLAGS -DUSE_PTHREAD_MUTEXES"
echo "forcing use of pthread mutexes... " >&6
diff --git a/src/libpfm4/config.mk b/src/libpfm4/config.mk
index 51d4f25..18f5838 100644
--- a/src/libpfm4/config.mk
+++ b/src/libpfm4/config.mk
@@ -177,6 +177,9 @@ ifeq ($(ARCH),cell)
CONFIG_PFMLIB_CELL=y
endif
+ifeq ($(ARCH),riscv64)
+CONFIG_PFMLIB_ARCH_RISCV64=y
+endif
#
# you shouldn't have to touch anything beyond this point
diff --git a/src/linux-context.h b/src/linux-context.h
index 524490b..7d51495 100644
--- a/src/linux-context.h
+++ b/src/linux-context.h
@@ -35,6 +35,8 @@ typedef ucontext_t hwd_ucontext_t;
#define OVERFLOW_ADDRESS(ctx) ctx.ucontext->uc_mcontext.pc
#elif defined(__mips__)
#define OVERFLOW_ADDRESS(ctx) ctx.ucontext->uc_mcontext.pc
+#elif defined(__riscv)
+#define OVERFLOW_ADDRESS(ctx) ctx.ucontext->uc_mcontext.__gregs[REG_PC]
#else
#error "OVERFLOW_ADDRESS() undefined!"
#endif
diff --git a/src/linux-timer.c b/src/linux-timer.c
index 853e676..8222acb 100644
--- a/src/linux-timer.c
+++ b/src/linux-timer.c
@@ -288,6 +288,27 @@ get_cycles( void )
return 0;
}
+/************************/
+/* riscv64 get_cycles() */
+/************************/
+
+#elif defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen == 64
+static inline long long
+get_cycles( void )
+{
+ register unsigned long ret;
+
+ __asm__ __volatile__ ("rdcycle %0" : "=r" (ret));
+
+ return ret;
+}
+
+/*
+ * TODO: riscv32 implementation can be done following example in:
+ * Volume I: RISC-V User-Level ISA V2.2
+ * 2.8 Control and Status Register Instructions
+ * Timers and Counters
+ */
#elif !defined(HAVE_GETTIMEOFDAY) && !defined(HAVE_CLOCK_GETTIME)
#error "No get_cycles support for this architecture. "
diff --git a/src/mb.h b/src/mb.h
index 1019691..0b82a9d 100644
--- a/src/mb.h
+++ b/src/mb.h
@@ -39,6 +39,9 @@
#elif defined(__aarch64__)
#define rmb() asm volatile("dmb ld" ::: "memory")
+#elif defined(__riscv)
+#define rmb() asm volatile("fence ir, ir" ::: "memory")
+
#elif defined(__mips__)
#define rmb() asm volatile( \
".set mips2\n\t" \