78 lines
2.9 KiB
Diff
78 lines
2.9 KiB
Diff
commit f65c9d9efce2df3658f66c99c92a7de8a510b004
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Author: William Cohen <wcohen@redhat.com>
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Date: Mon Jan 7 14:00:20 2013 -0500
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Add preset events for ARM Cortex A15
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diff --git a/src/papi_events.csv b/src/papi_events.csv
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index 44e4b65..286ee27 100644
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--- a/src/papi_events.csv
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+++ b/src/papi_events.csv
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@@ -1349,6 +1349,24 @@ PRESET,PAPI_L1_DCA,NOT_DERIVED,DCACHE_ACCESS
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PRESET,PAPI_L1_DCM,NOT_DERIVED,DCACHE_REFILL
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PRESET,PAPI_L1_ICM,NOT_DERIVED,IFETCH_MISS
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#
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+CPU,arm_ac15
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+#
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+PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED
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+PRESET,PAPI_TOT_IIS,NOT_DERIVED,INST_SPEC_EXEC
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+PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
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+#PRESET,PAPI_HW_INT,NOT_DERIVED,EXT_INTERRUPTS
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+PRESET,PAPI_FP_INS,NOT_DERIVED,INST_SPEC_EXEC_VFP
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+PRESET,PAPI_VEC_INS,NOT_DERIVED,INST_SPEC_EXEC_SIMD
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+PRESET,PAPI_BR_INS,NOT_DERIVED,INST_SPEC_EXEC_SOFT_PC
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+PRESET,PAPI_BR_MSP,NOT_DERIVED,BRANCH_MISPRED
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+PRESET,PAPI_LD_INS,NOT_DERIVED,DATA_MEM_READ_ACCESS
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+PRESET,PAPI_SR_INS,NOT_DERIVED,DATA_MEM_WRITE_ACCESS
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+#PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISS
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+#PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_REFILL
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+PRESET,PAPI_L1_DCA,DERIVED_ADD,L1D_READ_ACCESS,L1D_WRITE_ACCESS
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+PRESET,PAPI_L1_DCM,DERIVED_ADD,L1D_READ_REFILL,L1D_WRITE_REFILL
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+PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL
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+#
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CPU,mips_74k
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#
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PRESET,PAPI_TOT_CYC,NOT_DERIVED,CYCLES
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commit 57c520df4ca957a0b2550e1177d87f8b167c06a5
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Author: William Cohen <wcohen@redhat.com>
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Date: Fri Jan 11 16:34:56 2013 -0500
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Clean up armv7 cortex a15 presets
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Clean up armv7 cortex a15 presets and add presets for L1 and L2 cache
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Signed-off-by: William Cohen <wcohen@redhat.com>
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diff --git a/src/papi_events.csv b/src/papi_events.csv
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index 286ee27..13260bc 100644
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--- a/src/papi_events.csv
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+++ b/src/papi_events.csv
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@@ -1354,18 +1354,24 @@ CPU,arm_ac15
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PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED
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PRESET,PAPI_TOT_IIS,NOT_DERIVED,INST_SPEC_EXEC
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PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
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-#PRESET,PAPI_HW_INT,NOT_DERIVED,EXT_INTERRUPTS
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PRESET,PAPI_FP_INS,NOT_DERIVED,INST_SPEC_EXEC_VFP
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PRESET,PAPI_VEC_INS,NOT_DERIVED,INST_SPEC_EXEC_SIMD
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PRESET,PAPI_BR_INS,NOT_DERIVED,INST_SPEC_EXEC_SOFT_PC
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PRESET,PAPI_BR_MSP,NOT_DERIVED,BRANCH_MISPRED
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PRESET,PAPI_LD_INS,NOT_DERIVED,DATA_MEM_READ_ACCESS
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PRESET,PAPI_SR_INS,NOT_DERIVED,DATA_MEM_WRITE_ACCESS
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-#PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISS
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-#PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_REFILL
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PRESET,PAPI_L1_DCA,DERIVED_ADD,L1D_READ_ACCESS,L1D_WRITE_ACCESS
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PRESET,PAPI_L1_DCM,DERIVED_ADD,L1D_READ_REFILL,L1D_WRITE_REFILL
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+PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_READ_ACCESS
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+PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_WRITE_ACCESS
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+PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE_ACCESS
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PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL
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+PRESET,PAPI_L2_DCH,NOT_DERIVED,L2D_CACHE_ACCESS
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+PRESET,PAPI_L2_DCM,NOT_DERIVED,L2D_CACHE_REFILL
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+PRESET,PAPI_L2_DCR,NOT_DERIVED,L2D_READ_ACCESS
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+PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_WRITE_ACCESS
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+PRESET,PAPI_L2_LDM,NOT_DERIVED,L2D_READ_REFILL
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+PRESET,PAPI_L2_STM,NOT_DERIVED,L2D_WRITE_REFILL
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#
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CPU,mips_74k
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#
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