commit f65c9d9efce2df3658f66c99c92a7de8a510b004 Author: William Cohen Date: Mon Jan 7 14:00:20 2013 -0500 Add preset events for ARM Cortex A15 diff --git a/src/papi_events.csv b/src/papi_events.csv index 44e4b65..286ee27 100644 --- a/src/papi_events.csv +++ b/src/papi_events.csv @@ -1349,6 +1349,24 @@ PRESET,PAPI_L1_DCA,NOT_DERIVED,DCACHE_ACCESS PRESET,PAPI_L1_DCM,NOT_DERIVED,DCACHE_REFILL PRESET,PAPI_L1_ICM,NOT_DERIVED,IFETCH_MISS # +CPU,arm_ac15 +# +PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED +PRESET,PAPI_TOT_IIS,NOT_DERIVED,INST_SPEC_EXEC +PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES +#PRESET,PAPI_HW_INT,NOT_DERIVED,EXT_INTERRUPTS +PRESET,PAPI_FP_INS,NOT_DERIVED,INST_SPEC_EXEC_VFP +PRESET,PAPI_VEC_INS,NOT_DERIVED,INST_SPEC_EXEC_SIMD +PRESET,PAPI_BR_INS,NOT_DERIVED,INST_SPEC_EXEC_SOFT_PC +PRESET,PAPI_BR_MSP,NOT_DERIVED,BRANCH_MISPRED +PRESET,PAPI_LD_INS,NOT_DERIVED,DATA_MEM_READ_ACCESS +PRESET,PAPI_SR_INS,NOT_DERIVED,DATA_MEM_WRITE_ACCESS +#PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISS +#PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_REFILL +PRESET,PAPI_L1_DCA,DERIVED_ADD,L1D_READ_ACCESS,L1D_WRITE_ACCESS +PRESET,PAPI_L1_DCM,DERIVED_ADD,L1D_READ_REFILL,L1D_WRITE_REFILL +PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL +# CPU,mips_74k # PRESET,PAPI_TOT_CYC,NOT_DERIVED,CYCLES commit 57c520df4ca957a0b2550e1177d87f8b167c06a5 Author: William Cohen Date: Fri Jan 11 16:34:56 2013 -0500 Clean up armv7 cortex a15 presets Clean up armv7 cortex a15 presets and add presets for L1 and L2 cache Signed-off-by: William Cohen diff --git a/src/papi_events.csv b/src/papi_events.csv index 286ee27..13260bc 100644 --- a/src/papi_events.csv +++ b/src/papi_events.csv @@ -1354,18 +1354,24 @@ CPU,arm_ac15 PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED PRESET,PAPI_TOT_IIS,NOT_DERIVED,INST_SPEC_EXEC PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES -#PRESET,PAPI_HW_INT,NOT_DERIVED,EXT_INTERRUPTS PRESET,PAPI_FP_INS,NOT_DERIVED,INST_SPEC_EXEC_VFP PRESET,PAPI_VEC_INS,NOT_DERIVED,INST_SPEC_EXEC_SIMD PRESET,PAPI_BR_INS,NOT_DERIVED,INST_SPEC_EXEC_SOFT_PC PRESET,PAPI_BR_MSP,NOT_DERIVED,BRANCH_MISPRED PRESET,PAPI_LD_INS,NOT_DERIVED,DATA_MEM_READ_ACCESS PRESET,PAPI_SR_INS,NOT_DERIVED,DATA_MEM_WRITE_ACCESS -#PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISS -#PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_REFILL PRESET,PAPI_L1_DCA,DERIVED_ADD,L1D_READ_ACCESS,L1D_WRITE_ACCESS PRESET,PAPI_L1_DCM,DERIVED_ADD,L1D_READ_REFILL,L1D_WRITE_REFILL +PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_READ_ACCESS +PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_WRITE_ACCESS +PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE_ACCESS PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL +PRESET,PAPI_L2_DCH,NOT_DERIVED,L2D_CACHE_ACCESS +PRESET,PAPI_L2_DCM,NOT_DERIVED,L2D_CACHE_REFILL +PRESET,PAPI_L2_DCR,NOT_DERIVED,L2D_READ_ACCESS +PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_WRITE_ACCESS +PRESET,PAPI_L2_LDM,NOT_DERIVED,L2D_READ_REFILL +PRESET,PAPI_L2_STM,NOT_DERIVED,L2D_WRITE_REFILL # CPU,mips_74k #