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14 Commits

Author SHA1 Message Date
David Abdurachmanov 14627af2cb
Merge remote-tracking branch 'up/master' into master-riscv64
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
2020-07-02 15:06:21 +03:00
David Abdurachmanov f09c2d2f2e
Rebuilt
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
2020-01-19 14:59:54 +02:00
David Abdurachmanov 8bb9e151cd
Fix merge
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
2020-01-16 15:56:50 +02:00
David Abdurachmanov 4072d90d42
Merge remote-tracking branch 'up/master' into master-riscv64
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
2020-01-16 15:54:22 +02:00
David Abdurachmanov ec584226e7
Merge remote-tracking branch 'up/f31' into master-riscv64
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
2019-08-18 17:03:13 -07:00
David Abdurachmanov 3d93b47201
Switch to use autogen.pl
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
2019-07-25 13:00:27 +03:00
David Abdurachmanov 50335cfa8a
memchecker depends on valgrind
Disable memchecker if valgrind is not available

Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
2019-07-25 11:43:11 +03:00
David Abdurachmanov 5a1b8d12c7
Rebase riscv patch
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
2019-07-25 10:00:38 +03:00
David Abdurachmanov f05ec5cb25
Merge remote-tracking branch 'up/master' into master-riscv64
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
2019-07-25 08:51:39 +03:00
David Abdurachmanov 67ca59b77a
Run autoreconf -fiv (due to RISC-V changes)
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
2018-06-02 11:15:11 +02:00
David Abdurachmanov 7486c1d928
Add OPAL patch for riscv64
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
2018-06-02 08:49:16 +02:00
David Abdurachmanov d3dd5bb711
Fix config.* replacement
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
2018-06-01 22:38:59 +02:00
David Abdurachmanov aaf33fdce6
Update config.* scripts for RISC-V support
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
2018-06-01 20:42:28 +02:00
David Abdurachmanov 302cec0581
Switch to use %{valgrind_arches}
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
2018-06-01 14:32:33 +02:00
2 changed files with 75 additions and 1 deletions

View File

@ -0,0 +1,46 @@
diff --git a/config/opal_config_asm.m4 b/config/opal_config_asm.m4
index 65675d1..7c77d65 100644
--- a/config/opal_config_asm.m4
+++ b/config/opal_config_asm.m4
@@ -1130,6 +1130,11 @@ AC_DEFUN([OPAL_CONFIG_ASM],[
fi
OPAL_GCC_INLINE_ASSIGN='"1: li %0,0" : "=&r"(ret)'
;;
+ riscv64*)
+ opal_cv_asm_arch="RISCV64"
+ OPAL_ASM_SUPPORT_64BIT=1
+ OPAL_GCC_INLINE_ASSIGN='"li %0, 0" : "=&r"(ret)'
+ ;;
# There is no current difference between s390 and s390x
# But use two different defines in case some come later
# as s390 is 31bits while s390x is 64bits
diff --git a/opal/include/opal/sys/architecture.h b/opal/include/opal/sys/architecture.h
index ee9aa96..8a9fc53 100644
--- a/opal/include/opal/sys/architecture.h
+++ b/opal/include/opal/sys/architecture.h
@@ -44,6 +44,7 @@
#define OPAL_ARM64 0101
#define OPAL_S390 0110
#define OPAL_S390X 0111
+#define OPAL_RISCV64 0120
#define OPAL_BUILTIN_SYNC 0200
#define OPAL_BUILTIN_GCC 0202
#define OPAL_BUILTIN_NO 0203
diff --git a/opal/include/opal/sys/cma.h b/opal/include/opal/sys/cma.h
index 4211013..9e02f99 100644
--- a/opal/include/opal/sys/cma.h
+++ b/opal/include/opal/sys/cma.h
@@ -92,6 +92,13 @@
#define __NR_process_vm_readv 340
#define __NR_process_vm_writev 341
+#elif OPAL_ASSEMBLY_ARCH == OPAL_RISCV64
+
+/* RISCV64 uses the asm-generic syscall numbers */
+
+#define __NR_process_vm_readv 270
+#define __NR_process_vm_writev 271
+
#else
#error "Unsupported architecture for process_vm_readv and process_vm_writev syscalls"
#endif

View File

@ -41,7 +41,7 @@
Name: openmpi%{?_cc_name_suffix}
Version: 4.0.4
Release: 1%{?dist}
Release: 1.0.riscv64%{?dist}
Summary: Open Message Passing Interface
License: BSD and MIT and Romio
URL: http://www.open-mpi.org/
@ -53,9 +53,14 @@ Source2: openmpi.pth.py2
Source3: openmpi.pth.py3
Source4: macros.openmpi
# Add support for riscv64
Patch10: openmpi-4.0.1-riscv64.patch
BuildRequires: gcc-c++
BuildRequires: gcc-gfortran
%ifarch %{valgrind_arches}
BuildRequires: valgrind-devel
%endif
%if %{with rdma}
BuildRequires: opensm-devel > 3.3.0
BuildRequires: rdma-core-devel
@ -94,6 +99,12 @@ BuildRequires: zlib-devel
BuildRequires: rpm-mpi-hooks
%endif
BuildRequires: automake
BuildRequires: autoconf
BuildRequires: libtool
BuildRequires: gettext
BuildRequires: perl-interpreter
Provides: mpi
%if 0%{?rhel}
# Need this for /etc/profile.d/modules.sh
@ -175,6 +186,17 @@ OpenMPI support for Python 3.
%prep
%autosetup -p1
./autogen.pl --force
# Update config.* scripts to get RISC-V (riscv64) support
for f in $(find . -name config.guess); do
cp -v -f /usr/lib/rpm/redhat/config.guess "$f"
done
for f in $(find . -name config.sub); do
cp -v -f /usr/lib/rpm/redhat/config.sub "$f"
done
%build
./configure --prefix=%{_libdir}/%{name} \
--mandir=%{_mandir}/%{namearch} \
@ -186,8 +208,10 @@ OpenMPI support for Python 3.
--enable-mpi-java \
--enable-mpi1-compatibility \
--with-sge \
%ifarch %{valgrind_arches}
--with-valgrind \
--enable-memchecker \
%endif
--with-hwloc=/usr \
%if !0%{?el7}
--with-libevent=external \
@ -362,6 +386,10 @@ make check
%changelog
* Thu Jul 02 2020 David Abdurachmanov <david.abdurachmanov@sifive.com> - 4.0.4-1.0.riscv64
- Add OPAL patch to enable riscv64
- Switch to use %{valgrind_arches}
* Wed Jun 17 2020 Orion Poplawski <orion@nwra.com> - 4.0.4-1
- Update to 4.0.4