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New upstream version 4.06.0. 

Enable parallel builds again.
Rebase patches.
This commit is contained in:
Richard W.M. Jones 2017-11-06 12:39:44 +00:00
parent b562129589
commit a4c8f9a8f0
14 changed files with 186 additions and 1097 deletions
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36
0001-Changes-clarify-compatibility-breaking-change-items.patch
View File

@ -1,36 +0,0 @@
From 5bd96201dbd70c387c5af4b510d0de4abc0cfd7d Mon Sep 17 00:00:00 2001
From: Gabriel Scherer <gabriel.scherer@gmail.com>
Date: Wed, 12 Jul 2017 11:57:22 -0400
Subject: [PATCH 01/12] Changes: clarify compatibility-breaking change items
---
Changes | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Changes b/Changes
index cc59f635e..10642f19d 100644
--- a/Changes
+++ b/Changes
@@ -64,6 +64,9 @@ OCaml 4.05.0 (13 Jul 2017):
* MPR#7414, GPR#929: Soundness bug with non-generalized type variables and
functors.
+ (compatibility: some code using module-global mutable state will
+ fail at compile-time and is fixed by adding extra annotations;
+ see the Mantis and Github discussions.)
(Jacques Garrigue, report by Leo White)
### Compiler user-interface and warnings:
@@ -567,6 +570,9 @@ The complete list of changes is listed below.
(Mark Shinwell, Leo White, review by Xavier Leroy)
* GPR#1088: Gc.minor_words now returns accurate numbers.
+ (compatibility: the .mli declaration of `Gc.minor_words`
+ and `Gc.get_minor_free` changed, which may break libraries
+ re-exporting these values.)
(Stephen Dolan, review by Pierre Chambart and Xavier Leroy)
OCaml 4.04.2 (23 Jun 2017):
--
2.13.2

18
0004-Don-t-add-rpaths-to-libraries.patch → 0001-Don-t-add-rpaths-to-libraries.patch
View File

@ -1,25 +1,23 @@
From b2118848e9a0aa96c5ccb3ede65f2d0e9cfb114a Mon Sep 17 00:00:00 2001
From 358855aa61775b72a8cba0d107286df960b1380c Mon Sep 17 00:00:00 2001
From: "Richard W.M. Jones" <rjones@redhat.com>
Date: Tue, 24 Jun 2014 10:00:15 +0100
Subject: [PATCH 04/12] Don't add rpaths to libraries.
Subject: [PATCH 1/4] Don't add rpaths to libraries.
---
tools/Makefile | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
tools/Makefile | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tools/Makefile b/tools/Makefile
index 9a8cf652b..269aa18e6 100644
index 92d9e99e7..d0b635b06 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -156,9 +156,9 @@ $(call byte_and_opt,ocamlmklib,ocamlmklibconfig.cmo config.cmo misc.cmo \
@@ -156,8 +156,8 @@ $(call byte_and_opt,ocamlmklib,ocamlmklibconfig.cmo config.cmo misc.cmo \
ocamlmklibconfig.ml: ../config/Makefile Makefile
(echo 'let bindir = "$(BINDIR)"'; \
echo 'let supports_shared_libraries = $(SUPPORTS_SHARED_LIBRARIES)';\
- echo 'let byteccrpath = "$(BYTECCRPATH)"'; \
- echo 'let nativeccrpath = "$(NATIVECCRPATH)"'; \
- echo 'let default_rpath = "$(RPATH)"'; \
- echo 'let mksharedlibrpath = "$(MKSHAREDLIBRPATH)"'; \
+ echo 'let byteccrpath = ""'; \
+ echo 'let nativeccrpath = ""'; \
+ echo 'let default_rpath = ""'; \
+ echo 'let mksharedlibrpath = ""'; \
echo 'let toolpref = "$(TOOLPREF)"'; \
sed -n -e 's/^#ml //p' ../config/Makefile) \

44
0002-MPR-7591-frametable-not-8-aligned-on-x86-64-port.patch
View File

@ -1,44 +0,0 @@
From 22dbcdfb921b19d171134de90984805622877e55 Mon Sep 17 00:00:00 2001
From: Xavier Leroy <xavier.leroy@inria.fr>
Date: Sat, 22 Jul 2017 16:32:23 -0400
Subject: [PATCH 02/12] MPR#7591: frametable not 8-aligned on x86-64 port
Cherry-pick of 7077b60 from trunk.
---
Changes | 7 +++++++
asmcomp/amd64/emit.mlp | 3 ++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/Changes b/Changes
index 10642f19d..cc7e0a82f 100644
--- a/Changes
+++ b/Changes
@@ -1,3 +1,10 @@
+Working 4.05.x branch
+---------------------
+
+- MPR#7591, GPR#1257: on x86-64, frame table is not 8-aligned
+ (Xavier Leroy, report by Mantis user "voglerr", review by Gabriel Scherer)
+
+
OCaml 4.05.0 (13 Jul 2017):
---------------------------
diff --git a/asmcomp/amd64/emit.mlp b/asmcomp/amd64/emit.mlp
index c3f8692a8..75a785f74 100644
--- a/asmcomp/amd64/emit.mlp
+++ b/asmcomp/amd64/emit.mlp
@@ -1065,8 +1065,9 @@ let end_assembly() =
D.data ();
emit_global_label "data_end";
- D.long (const 0);
+ D.qword (const 0);
+ D.align 8; (* PR#7591 *)
emit_global_label "frametable";
let setcnt = ref 0 in
--
2.13.2

10
0005-ocamlbyteinfo-ocamlplugininfo-Useful-utilities-from-.patch → 0002-ocamlbyteinfo-ocamlplugininfo-Useful-utilities-from-.patch
View File

@ -1,7 +1,7 @@
From 80e2921e472f66f70575d6e4e6c8ff6f5714e4e4 Mon Sep 17 00:00:00 2001
From 930dbd7512305bb4b80d91e621c4e714531b5513 Mon Sep 17 00:00:00 2001
From: "Richard W.M. Jones" <rjones@redhat.com>
Date: Tue, 29 May 2012 20:40:36 +0100
Subject: [PATCH 05/12] ocamlbyteinfo, ocamlplugininfo: Useful utilities from
Subject: [PATCH 2/4] ocamlbyteinfo, ocamlplugininfo: Useful utilities from
Debian, sent upstream.
See:
@ -15,7 +15,7 @@ http://git.debian.org/?p=pkg-ocaml-maint/packages/ocaml.git;a=tree;f=debian/ocam
diff --git a/ocamlbyteinfo.ml b/ocamlbyteinfo.ml
new file mode 100644
index 000000000..eb9a293e3
index 000000000..0a537e4d5
--- /dev/null
+++ b/ocamlbyteinfo.ml
@@ -0,0 +1,101 @@
@ -49,9 +49,9 @@ index 000000000..eb9a293e3
+ else acc
+ in fold 0 0 []
+ in
+ let sect = String.create len in
+ let sect = Bytes.create len in
+ let _ = really_input ic sect 0 len in
+ get_string_list sect len
+ get_string_list (Bytes.to_string sect) len
+
+let print = Printf.printf
+let perr s =

409
0003-Fixes-for-out-of-range-Ialloc.patch
View File

@ -1,409 +0,0 @@
From 664f0763d37f85e2ec53d6394251b5948dcfa727 Mon Sep 17 00:00:00 2001
From: Mark Shinwell <mshinwell@janestreet.com>
Date: Mon, 31 Jul 2017 14:37:47 +0100
Subject: [PATCH 03/12] Fixes for out-of-range Ialloc
Cherry-pick of GPR#1271 which was merged on trunk.
Fixes for Ialloc instructions allocating more than Max_young_wosize words in the minor heap
Out-of-range Ialloc instructions cause various problems, see in particular GPR #1250.
---
Changes | 5 +
asmcomp/cmmgen.ml | 38 ++--
asmcomp/selectgen.ml | 3 +-
testsuite/tests/basic-more/pr1271.ml | 288 ++++++++++++++++++++++++++++
testsuite/tests/basic-more/pr1271.reference | 2 +
5 files changed, 317 insertions(+), 19 deletions(-)
create mode 100644 testsuite/tests/basic-more/pr1271.ml
create mode 100644 testsuite/tests/basic-more/pr1271.reference
diff --git a/Changes b/Changes
index cc7e0a82f..e8dbd42e2 100644
--- a/Changes
+++ b/Changes
@@ -4,6 +4,11 @@ Working 4.05.x branch
- MPR#7591, GPR#1257: on x86-64, frame table is not 8-aligned
(Xavier Leroy, report by Mantis user "voglerr", review by Gabriel Scherer)
+- GPR#1271: Don't generate Ialloc instructions for closures that exceed
+ Max_young_wosize; instead allocate them on the major heap. (Related
+ to GPR#1250.)
+ (Mark Shinwell)
+
OCaml 4.05.0 (13 Jul 2017):
---------------------------
diff --git a/asmcomp/cmmgen.ml b/asmcomp/cmmgen.ml
index 4ac4b40c6..2120d3985 100644
--- a/asmcomp/cmmgen.ml
+++ b/asmcomp/cmmgen.ml
@@ -1641,29 +1641,31 @@ let rec transl env e =
List.iter (fun f -> Queue.add f functions) fundecls;
Cconst_symbol lbl
| Uclosure(fundecls, clos_vars) ->
- let block_size =
- fundecls_size fundecls + List.length clos_vars in
let rec transl_fundecls pos = function
[] ->
List.map (transl env) clos_vars
| f :: rem ->
Queue.add f functions;
- let header =
- if pos = 0
- then alloc_closure_header block_size f.dbg
- else alloc_infix_header pos f.dbg in
- if f.arity = 1 || f.arity = 0 then
- header ::
- Cconst_symbol f.label ::
- int_const f.arity ::
- transl_fundecls (pos + 3) rem
- else
- header ::
- Cconst_symbol(curry_function f.arity) ::
- int_const f.arity ::
- Cconst_symbol f.label ::
- transl_fundecls (pos + 4) rem in
- Cop(Calloc, transl_fundecls 0 fundecls, Debuginfo.none)
+ let without_header =
+ if f.arity = 1 || f.arity = 0 then
+ Cconst_symbol f.label ::
+ int_const f.arity ::
+ transl_fundecls (pos + 3) rem
+ else
+ Cconst_symbol(curry_function f.arity) ::
+ int_const f.arity ::
+ Cconst_symbol f.label ::
+ transl_fundecls (pos + 4) rem
+ in
+ if pos = 0 then without_header
+ else (alloc_infix_header pos f.dbg) :: without_header
+ in
+ let dbg =
+ match fundecls with
+ | [] -> Debuginfo.none
+ | fundecl::_ -> fundecl.dbg
+ in
+ make_alloc dbg Obj.closure_tag (transl_fundecls 0 fundecls)
| Uoffset(arg, offset) ->
(* produces a valid Caml value, pointing just after an infix header *)
let ptr = transl env arg in
diff --git a/asmcomp/selectgen.ml b/asmcomp/selectgen.ml
index 7cd8cd5c3..1158fc0d0 100644
--- a/asmcomp/selectgen.ml
+++ b/asmcomp/selectgen.ml
@@ -738,7 +738,8 @@ method emit_expr (env:environment) exp =
loc_arg (Proc.loc_external_results rd) in
self#insert_move_results loc_res rd stack_ofs;
Some rd
- | Ialloc { words = _; spacetime_index; label_after_call_gc; } ->
+ | Ialloc { words; spacetime_index; label_after_call_gc; } ->
+ assert (words <= Config.max_young_wosize);
let rd = self#regs_for typ_val in
let size = size_expr env (Ctuple new_args) in
let op =
diff --git a/testsuite/tests/basic-more/pr1271.ml b/testsuite/tests/basic-more/pr1271.ml
new file mode 100644
index 000000000..3890d0fbb
--- /dev/null
+++ b/testsuite/tests/basic-more/pr1271.ml
@@ -0,0 +1,288 @@
+(* GPR#1271 *)
+
+module F (X : sig val x : int end) = struct
+ let rec f1 y = f270 (X.x + y)
+ and f2 y = (f1 [@inlined never]) y
+ and f3 y = (f2 [@inlined never]) y
+ and f4 y = (f3 [@inlined never]) y
+ and f5 y = (f4 [@inlined never]) y
+ and f6 y = (f5 [@inlined never]) y
+ and f7 y = (f6 [@inlined never]) y
+ and f8 y = (f7 [@inlined never]) y
+ and f9 y = (f8 [@inlined never]) y
+ and f10 y = (f9 [@inlined never]) y
+ and f11 y = (f10 [@inlined never]) y
+ and f12 y = (f11 [@inlined never]) y
+ and f13 y = (f12 [@inlined never]) y
+ and f14 y = (f13 [@inlined never]) y
+ and f15 y = (f14 [@inlined never]) y
+ and f16 y = (f15 [@inlined never]) y
+ and f17 y = (f16 [@inlined never]) y
+ and f18 y = (f17 [@inlined never]) y
+ and f19 y = (f18 [@inlined never]) y
+ and f20 y = (f19 [@inlined never]) y
+ and f21 y = (f20 [@inlined never]) y
+ and f22 y = (f21 [@inlined never]) y
+ and f23 y = (f22 [@inlined never]) y
+ and f24 y = (f23 [@inlined never]) y
+ and f25 y = (f24 [@inlined never]) y
+ and f26 y = (f25 [@inlined never]) y
+ and f27 y = (f26 [@inlined never]) y
+ and f28 y = (f27 [@inlined never]) y
+ and f29 y = (f28 [@inlined never]) y
+ and f30 y = (f29 [@inlined never]) y
+ and f31 y = (f30 [@inlined never]) y
+ and f32 y = (f31 [@inlined never]) y
+ and f33 y = (f32 [@inlined never]) y
+ and f34 y = (f33 [@inlined never]) y
+ and f35 y = (f34 [@inlined never]) y
+ and f36 y = (f35 [@inlined never]) y
+ and f37 y = (f36 [@inlined never]) y
+ and f38 y = (f37 [@inlined never]) y
+ and f39 y = (f38 [@inlined never]) y
+ and f40 y = (f39 [@inlined never]) y
+ and f41 y = (f40 [@inlined never]) y
+ and f42 y = (f41 [@inlined never]) y
+ and f43 y = (f42 [@inlined never]) y
+ and f44 y = (f43 [@inlined never]) y
+ and f45 y = (f44 [@inlined never]) y
+ and f46 y = (f45 [@inlined never]) y
+ and f47 y = (f46 [@inlined never]) y
+ and f48 y = (f47 [@inlined never]) y
+ and f49 y = (f48 [@inlined never]) y
+ and f50 y = (f49 [@inlined never]) y
+ and f51 y = (f50 [@inlined never]) y
+ and f52 y = (f51 [@inlined never]) y
+ and f53 y = (f52 [@inlined never]) y
+ and f54 y = (f53 [@inlined never]) y
+ and f55 y = (f54 [@inlined never]) y
+ and f56 y = (f55 [@inlined never]) y
+ and f57 y = (f56 [@inlined never]) y
+ and f58 y = (f57 [@inlined never]) y
+ and f59 y = (f58 [@inlined never]) y
+ and f60 y = (f59 [@inlined never]) y
+ and f61 y = (f60 [@inlined never]) y
+ and f62 y = (f61 [@inlined never]) y
+ and f63 y = (f62 [@inlined never]) y
+ and f64 y = (f63 [@inlined never]) y
+ and f65 y = (f64 [@inlined never]) y
+ and f66 y = (f65 [@inlined never]) y
+ and f67 y = (f66 [@inlined never]) y
+ and f68 y = (f67 [@inlined never]) y
+ and f69 y = (f68 [@inlined never]) y
+ and f70 y = (f69 [@inlined never]) y
+ and f71 y = (f70 [@inlined never]) y
+ and f72 y = (f71 [@inlined never]) y
+ and f73 y = (f72 [@inlined never]) y
+ and f74 y = (f73 [@inlined never]) y
+ and f75 y = (f74 [@inlined never]) y
+ and f76 y = (f75 [@inlined never]) y
+ and f77 y = (f76 [@inlined never]) y
+ and f78 y = (f77 [@inlined never]) y
+ and f79 y = (f78 [@inlined never]) y
+ and f80 y = (f79 [@inlined never]) y
+ and f81 y = (f80 [@inlined never]) y
+ and f82 y = (f81 [@inlined never]) y
+ and f83 y = (f82 [@inlined never]) y
+ and f84 y = (f83 [@inlined never]) y
+ and f85 y = (f84 [@inlined never]) y
+ and f86 y = (f85 [@inlined never]) y
+ and f87 y = (f86 [@inlined never]) y
+ and f88 y = (f87 [@inlined never]) y
+ and f89 y = (f88 [@inlined never]) y
+ and f90 y = (f89 [@inlined never]) y
+ and f91 y = (f90 [@inlined never]) y
+ and f92 y = (f91 [@inlined never]) y
+ and f93 y = (f92 [@inlined never]) y
+ and f94 y = (f93 [@inlined never]) y
+ and f95 y = (f94 [@inlined never]) y
+ and f96 y = (f95 [@inlined never]) y
+ and f97 y = (f96 [@inlined never]) y
+ and f98 y = (f97 [@inlined never]) y
+ and f99 y = (f98 [@inlined never]) y
+ and f100 y = (f99 [@inlined never]) y
+ and f101 y = (f100 [@inlined never]) y
+ and f102 y = (f101 [@inlined never]) y
+ and f103 y = (f102 [@inlined never]) y
+ and f104 y = (f103 [@inlined never]) y
+ and f105 y = (f104 [@inlined never]) y
+ and f106 y = (f105 [@inlined never]) y
+ and f107 y = (f106 [@inlined never]) y
+ and f108 y = (f107 [@inlined never]) y
+ and f109 y = (f108 [@inlined never]) y
+ and f110 y = (f109 [@inlined never]) y
+ and f111 y = (f110 [@inlined never]) y
+ and f112 y = (f111 [@inlined never]) y
+ and f113 y = (f112 [@inlined never]) y
+ and f114 y = (f113 [@inlined never]) y
+ and f115 y = (f114 [@inlined never]) y
+ and f116 y = (f115 [@inlined never]) y
+ and f117 y = (f116 [@inlined never]) y
+ and f118 y = (f117 [@inlined never]) y
+ and f119 y = (f118 [@inlined never]) y
+ and f120 y = (f119 [@inlined never]) y
+ and f121 y = (f120 [@inlined never]) y
+ and f122 y = (f121 [@inlined never]) y
+ and f123 y = (f122 [@inlined never]) y
+ and f124 y = (f123 [@inlined never]) y
+ and f125 y = (f124 [@inlined never]) y
+ and f126 y = (f125 [@inlined never]) y
+ and f127 y = (f126 [@inlined never]) y
+ and f128 y = (f127 [@inlined never]) y
+ and f129 y = (f128 [@inlined never]) y
+ and f130 y = (f129 [@inlined never]) y
+ and f131 y = (f130 [@inlined never]) y
+ and f132 y = (f131 [@inlined never]) y
+ and f133 y = (f132 [@inlined never]) y
+ and f134 y = (f133 [@inlined never]) y
+ and f135 y = (f134 [@inlined never]) y
+ and f136 y = (f135 [@inlined never]) y
+ and f137 y = (f136 [@inlined never]) y
+ and f138 y = (f137 [@inlined never]) y
+ and f139 y = (f138 [@inlined never]) y
+ and f140 y = (f139 [@inlined never]) y
+ and f141 y = (f140 [@inlined never]) y
+ and f142 y = (f141 [@inlined never]) y
+ and f143 y = (f142 [@inlined never]) y
+ and f144 y = (f143 [@inlined never]) y
+ and f145 y = (f144 [@inlined never]) y
+ and f146 y = (f145 [@inlined never]) y
+ and f147 y = (f146 [@inlined never]) y
+ and f148 y = (f147 [@inlined never]) y
+ and f149 y = (f148 [@inlined never]) y
+ and f150 y = (f149 [@inlined never]) y
+ and f151 y = (f150 [@inlined never]) y
+ and f152 y = (f151 [@inlined never]) y
+ and f153 y = (f152 [@inlined never]) y
+ and f154 y = (f153 [@inlined never]) y
+ and f155 y = (f154 [@inlined never]) y
+ and f156 y = (f155 [@inlined never]) y
+ and f157 y = (f156 [@inlined never]) y
+ and f158 y = (f157 [@inlined never]) y
+ and f159 y = (f158 [@inlined never]) y
+ and f160 y = (f159 [@inlined never]) y
+ and f161 y = (f160 [@inlined never]) y
+ and f162 y = (f161 [@inlined never]) y
+ and f163 y = (f162 [@inlined never]) y
+ and f164 y = (f163 [@inlined never]) y
+ and f165 y = (f164 [@inlined never]) y
+ and f166 y = (f165 [@inlined never]) y
+ and f167 y = (f166 [@inlined never]) y
+ and f168 y = (f167 [@inlined never]) y
+ and f169 y = (f168 [@inlined never]) y
+ and f170 y = (f169 [@inlined never]) y
+ and f171 y = (f170 [@inlined never]) y
+ and f172 y = (f171 [@inlined never]) y
+ and f173 y = (f172 [@inlined never]) y
+ and f174 y = (f173 [@inlined never]) y
+ and f175 y = (f174 [@inlined never]) y
+ and f176 y = (f175 [@inlined never]) y
+ and f177 y = (f176 [@inlined never]) y
+ and f178 y = (f177 [@inlined never]) y
+ and f179 y = (f178 [@inlined never]) y
+ and f180 y = (f179 [@inlined never]) y
+ and f181 y = (f180 [@inlined never]) y
+ and f182 y = (f181 [@inlined never]) y
+ and f183 y = (f182 [@inlined never]) y
+ and f184 y = (f183 [@inlined never]) y
+ and f185 y = (f184 [@inlined never]) y
+ and f186 y = (f185 [@inlined never]) y
+ and f187 y = (f186 [@inlined never]) y
+ and f188 y = (f187 [@inlined never]) y
+ and f189 y = (f188 [@inlined never]) y
+ and f190 y = (f189 [@inlined never]) y
+ and f191 y = (f190 [@inlined never]) y
+ and f192 y = (f191 [@inlined never]) y
+ and f193 y = (f192 [@inlined never]) y
+ and f194 y = (f193 [@inlined never]) y
+ and f195 y = (f194 [@inlined never]) y
+ and f196 y = (f195 [@inlined never]) y
+ and f197 y = (f196 [@inlined never]) y
+ and f198 y = (f197 [@inlined never]) y
+ and f199 y = (f198 [@inlined never]) y
+ and f200 y = (f199 [@inlined never]) y
+ and f201 y = (f200 [@inlined never]) y
+ and f202 y = (f201 [@inlined never]) y
+ and f203 y = (f202 [@inlined never]) y
+ and f204 y = (f203 [@inlined never]) y
+ and f205 y = (f204 [@inlined never]) y
+ and f206 y = (f205 [@inlined never]) y
+ and f207 y = (f206 [@inlined never]) y
+ and f208 y = (f207 [@inlined never]) y
+ and f209 y = (f208 [@inlined never]) y
+ and f210 y = (f209 [@inlined never]) y
+ and f211 y = (f210 [@inlined never]) y
+ and f212 y = (f211 [@inlined never]) y
+ and f213 y = (f212 [@inlined never]) y
+ and f214 y = (f213 [@inlined never]) y
+ and f215 y = (f214 [@inlined never]) y
+ and f216 y = (f215 [@inlined never]) y
+ and f217 y = (f216 [@inlined never]) y
+ and f218 y = (f217 [@inlined never]) y
+ and f219 y = (f218 [@inlined never]) y
+ and f220 y = (f219 [@inlined never]) y
+ and f221 y = (f220 [@inlined never]) y
+ and f222 y = (f221 [@inlined never]) y
+ and f223 y = (f222 [@inlined never]) y
+ and f224 y = (f223 [@inlined never]) y
+ and f225 y = (f224 [@inlined never]) y
+ and f226 y = (f225 [@inlined never]) y
+ and f227 y = (f226 [@inlined never]) y
+ and f228 y = (f227 [@inlined never]) y
+ and f229 y = (f228 [@inlined never]) y
+ and f230 y = (f229 [@inlined never]) y
+ and f231 y = (f230 [@inlined never]) y
+ and f232 y = (f231 [@inlined never]) y
+ and f233 y = (f232 [@inlined never]) y
+ and f234 y = (f233 [@inlined never]) y
+ and f235 y = (f234 [@inlined never]) y
+ and f236 y = (f235 [@inlined never]) y
+ and f237 y = (f236 [@inlined never]) y
+ and f238 y = (f237 [@inlined never]) y
+ and f239 y = (f238 [@inlined never]) y
+ and f240 y = (f239 [@inlined never]) y
+ and f241 y = (f240 [@inlined never]) y
+ and f242 y = (f241 [@inlined never]) y
+ and f243 y = (f242 [@inlined never]) y
+ and f244 y = (f243 [@inlined never]) y
+ and f245 y = (f244 [@inlined never]) y
+ and f246 y = (f245 [@inlined never]) y
+ and f247 y = (f246 [@inlined never]) y
+ and f248 y = (f247 [@inlined never]) y
+ and f249 y = (f248 [@inlined never]) y
+ and f250 y = (f249 [@inlined never]) y
+ and f251 y = (f250 [@inlined never]) y
+ and f252 y = (f251 [@inlined never]) y
+ and f253 y = (f252 [@inlined never]) y
+ and f254 y = (f253 [@inlined never]) y
+ and f255 y = (f254 [@inlined never]) y
+ and f256 y = (f255 [@inlined never]) y
+ and f257 y = (f256 [@inlined never]) y
+ and f258 y = (f257 [@inlined never]) y
+ and f259 y = (f258 [@inlined never]) y
+ and f260 y = (f259 [@inlined never]) y
+ and f261 y = (f260 [@inlined never]) y
+ and f262 y = (f261 [@inlined never]) y
+ and f263 y = (f262 [@inlined never]) y
+ and f264 y = (f263 [@inlined never]) y
+ and f265 y = (f264 [@inlined never]) y
+ and f266 y = (f265 [@inlined never]) y
+ and f267 y = (f266 [@inlined never]) y
+ and f268 y = (f267 [@inlined never]) y
+ and f269 y = (f268 [@inlined never]) y
+ and f270 y = (f269 [@inlined never]) y
+end
+
+let words0 = Gc.minor_words ()
+let words1 = Gc.minor_words ()
+module X = F (struct let x = 42 end)
+let words2 = Gc.minor_words ()
+
+let expected = words1 -. words0
+
+let () =
+ match Sys.backend_type with
+ | Sys.Native ->
+ Printf.printf "%.0f" ((words2 -. words1) -. expected)
+ | Sys.Bytecode | Sys.Other _ ->
+ print_string "0"
diff --git a/testsuite/tests/basic-more/pr1271.reference b/testsuite/tests/basic-more/pr1271.reference
new file mode 100644
index 000000000..6e374c16e
--- /dev/null
+++ b/testsuite/tests/basic-more/pr1271.reference
@@ -0,0 +1,2 @@
+0
+All tests succeeded.
--
2.13.2

10
0006-configure-Allow-user-defined-C-compiler-flags.patch → 0003-configure-Allow-user-defined-C-compiler-flags.patch
View File

@ -1,18 +1,18 @@
From 313692e7425fd91917d4e35ad4ade459cb2c1138 Mon Sep 17 00:00:00 2001
From 66e774a2d3f8ebe6b6a4a3775112fc63619add8c Mon Sep 17 00:00:00 2001
From: "Richard W.M. Jones" <rjones@redhat.com>
Date: Tue, 29 May 2012 20:44:18 +0100
Subject: [PATCH 06/12] configure: Allow user defined C compiler flags.
Subject: [PATCH 3/4] configure: Allow user defined C compiler flags.
---
configure | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/configure b/configure
index e79659954..786f4cdbe 100755
index 203396554..9311589cf 100755
--- a/configure
+++ b/configure
@@ -2002,6 +2002,10 @@ if $with_fpic; then
echo "#define CAML_WITH_FPIC" >> m.h
@@ -2046,6 +2046,10 @@ if $flat_float_array; then
echo "#define FLAT_FLOAT_ARRAY" >> m.h
fi
+# Allow user defined C Compiler flags

231
0008-Add-RISC-V-backend-runtime.patch → 0004-Add-RISC-V-backend.patch
View File

@ -1,21 +1,22 @@
From d0f08d1cfa01efb02721f7d2e04ce61f38d6d6a7 Mon Sep 17 00:00:00 2001
From e70b3f9a27786cbec2346e205933b7104a68c0d9 Mon Sep 17 00:00:00 2001
From: Nicolas Ojeda Bar <n.oje.bar@gmail.com>
Date: Fri, 4 Nov 2016 20:39:09 +0100
Subject: [PATCH 08/12] Add RISC-V backend & runtime
Date: Fri, 27 Oct 2017 17:05:25 +0200
Subject: [PATCH 4/4] Add RISC-V backend
---
README.adoc | 1 +
asmcomp/riscv/CSE.ml | 36 +++
asmcomp/riscv/arch.ml | 84 ++++++
asmcomp/riscv/emit.mlp | 616 ++++++++++++++++++++++++++++++++++++++++++++
asmcomp/riscv/proc.ml | 301 ++++++++++++++++++++++
asmcomp/riscv/arch.ml | 87 ++++++
asmcomp/riscv/emit.mlp | 653 ++++++++++++++++++++++++++++++++++++++++++++
asmcomp/riscv/proc.ml | 301 ++++++++++++++++++++
asmcomp/riscv/reload.ml | 16 ++
asmcomp/riscv/scheduling.ml | 19 ++
asmcomp/riscv/selection.ml | 85 ++++++
asmrun/riscv.S | 424 ++++++++++++++++++++++++++++++
asmcomp/riscv/selection.ml | 72 +++++
asmrun/riscv.S | 424 ++++++++++++++++++++++++++++
byterun/caml/stack.h | 5 +
config/gnu/config.guess | 5 +-
configure | 5 +-
11 files changed, 1591 insertions(+), 1 deletion(-)
12 files changed, 1622 insertions(+), 2 deletions(-)
create mode 100644 asmcomp/riscv/CSE.ml
create mode 100644 asmcomp/riscv/arch.ml
create mode 100644 asmcomp/riscv/emit.mlp
@ -26,13 +27,13 @@ Subject: [PATCH 08/12] Add RISC-V backend & runtime
create mode 100644 asmrun/riscv.S
diff --git a/README.adoc b/README.adoc
index fe07edbba..f7d13bc06 100644
index 34ca38a06..85b6d0dce 100644
--- a/README.adoc
+++ b/README.adoc
@@ -34,6 +34,7 @@ IA32 (Pentium):: NetBSD, OpenBSD, Solaris 9
@@ -45,6 +45,7 @@ AMD64:: FreeBSD, OpenBSD, NetBSD
IA32 (Pentium):: NetBSD, OpenBSD, Solaris 9
PowerPC:: NetBSD
ARM:: NetBSD
SPARC:: Solaris, Linux, NetBSD
+RISC-V:: Linux
Other operating systems for the processors above have not been tested, but
@ -81,10 +82,10 @@ index 000000000..302811a99
+ (new cse)#fundecl f
diff --git a/asmcomp/riscv/arch.ml b/asmcomp/riscv/arch.ml
new file mode 100644
index 000000000..61a38b1dd
index 000000000..22c807c49
--- /dev/null
+++ b/asmcomp/riscv/arch.ml
@@ -0,0 +1,84 @@
@@ -0,0 +1,87 @@
+(***********************************************************************)
+(* *)
+(* OCaml *)
@ -119,6 +120,9 @@ index 000000000..61a38b1dd
+type addressing_mode =
+ | Iindexed of int (* reg + displ *)
+
+let is_immediate n =
+ (n <= 2047) && (n >= -2048)
+
+(* Sizes, endianness *)
+
+let big_endian = false
@ -171,10 +175,10 @@ index 000000000..61a38b1dd
+ printreg arg.(0) printreg arg.(1) printreg arg.(2)
diff --git a/asmcomp/riscv/emit.mlp b/asmcomp/riscv/emit.mlp
new file mode 100644
index 000000000..6d0e3aefd
index 000000000..51165d0f1
--- /dev/null
+++ b/asmcomp/riscv/emit.mlp
@@ -0,0 +1,616 @@
@@ -0,0 +1,653 @@
+(***********************************************************************)
+(* *)
+(* OCaml *)
@ -262,13 +266,53 @@ index 000000000..6d0e3aefd
+ | {loc = Reg r} -> emit_string (register_name r)
+ | _ -> fatal_error "Emit.emit_reg"
+
+(* Output a stack reference *)
+(* Adjust sp by the given byte amount *)
+
+let emit_stack r =
+ match r.loc with
+ Stack s ->
+ let ofs = slot_offset s (register_class r) in `{emit_int ofs}(sp)`
+ | _ -> fatal_error "Emit.emit_stack"
+let emit_stack_adjustment = function
+ | 0 -> ()
+ | n when is_immediate n ->
+ ` addi sp, sp, {emit_int n}\n`
+ | n ->
+ ` li {emit_reg reg_tmp1}, {emit_int n}\n`;
+ ` add sp, sp, {emit_reg reg_tmp1}\n`
+
+let reload_ra n =
+ let ofs = n - size_addr in
+ if is_immediate ofs then
+ ` {emit_string lg} ra, {emit_int ofs}(sp)\n`
+ else begin
+ ` li {emit_reg reg_tmp1}, {emit_int ofs}\n`;
+ ` add {emit_reg reg_tmp1}, sp, {emit_reg reg_tmp1}\n`;
+ ` {emit_string lg} ra, 0({emit_reg reg_tmp1})\n`
+ end
+
+let store_ra n =
+ let ofs = n - size_addr in
+ if is_immediate ofs then
+ ` {emit_string stg} ra, {emit_int(n - size_addr)}(sp)\n`
+ else begin
+ ` li {emit_reg reg_tmp1}, {emit_int ofs}\n`;
+ ` add {emit_reg reg_tmp1}, sp, {emit_reg reg_tmp1}\n`;
+ ` {emit_string stg} ra, 0({emit_reg reg_tmp1})\n`
+ end
+
+let emit_store stg src ofs =
+ if is_immediate ofs then
+ ` {emit_string stg} {emit_reg src}, {emit_int ofs}(sp)\n`
+ else begin
+ ` li {emit_reg reg_tmp1}, {emit_int ofs}\n`;
+ ` add {emit_reg reg_tmp1}, sp, {emit_reg reg_tmp1}\n`;
+ ` {emit_string stg} {emit_reg src}, 0({emit_reg reg_tmp1})\n`
+ end
+
+let emit_load lg dst ofs =
+ if is_immediate ofs then
+ ` {emit_string lg} {emit_reg dst}, {emit_int ofs}(sp)\n`
+ else begin
+ ` li {emit_reg reg_tmp1}, {emit_int ofs}\n`;
+ ` add {emit_reg reg_tmp1}, sp, {emit_reg reg_tmp1}\n`;
+ ` {emit_string lg} {emit_reg dst}, 0({emit_reg reg_tmp1})\n`
+ end
+
+(* Record live pointers at call points *)
+
@ -290,12 +334,8 @@ index 000000000..6d0e3aefd
+ | _ -> ()
+ )
+ live;
+ frame_descriptors :=
+ { fd_lbl = lbl;
+ fd_frame_size = frame_size();
+ fd_live_offset = !live_offset;
+ fd_raise = raise_;
+ fd_debuginfo = dbg } :: !frame_descriptors;
+ record_frame_descr ~label:lbl ~frame_size:(frame_size())
+ ~live_offset:!live_offset ~raise_frame:raise_ dbg;
+ lbl
+
+let record_frame ?label live raise_ dbg =
@ -395,6 +435,7 @@ index 000000000..6d0e3aefd
+
+(* Name of current function *)
+let function_name = ref ""
+
+(* Entry point for tail recursive calls *)
+let tailrec_entry_point = ref 0
+
@ -411,14 +452,18 @@ index 000000000..6d0e3aefd
+ ` mv {emit_reg dst}, {emit_reg src}\n`
+ | {loc = Reg _; typ = Float}, {loc = Reg _; typ = Float} ->
+ ` fmv.d {emit_reg dst}, {emit_reg src}\n`
+ | {loc = Reg _; typ = (Val | Int | Addr)}, {loc = Stack _} ->
+ ` {emit_string stg} {emit_reg src}, {emit_stack dst}\n`
+ | {loc = Reg _; typ = Float}, {loc = Stack _} ->
+ ` fsd {emit_reg src}, {emit_stack dst}\n`
+ | {loc = Stack _; typ = (Val | Int | Addr)}, {loc = Reg _ } ->
+ ` {emit_string lg} {emit_reg dst}, {emit_stack src}\n`
+ | {loc = Stack _; typ = Float}, {loc = Reg _} ->
+ ` fld {emit_reg dst}, {emit_stack src}\n`
+ | {loc = Reg _; typ = (Val | Int | Addr)}, {loc = Stack s} ->
+ let ofs = slot_offset s (register_class dst) in
+ emit_store stg src ofs
+ | {loc = Reg _; typ = Float}, {loc = Stack s} ->
+ let ofs = slot_offset s (register_class dst) in
+ emit_store "fsd" src ofs
+ | {loc = Stack s; typ = (Val | Int | Addr)}, {loc = Reg _} ->
+ let ofs = slot_offset s (register_class src) in
+ emit_load lg dst ofs
+ | {loc = Stack s; typ = Float}, {loc = Reg _} ->
+ let ofs = slot_offset s (register_class src) in
+ emit_load "fld" dst ofs
+ | _ ->
+ fatal_error "Emit: Imove"
+ end
@ -438,20 +483,16 @@ index 000000000..6d0e3aefd
+ record_frame ~label i.live false i.dbg
+ | Lop(Itailcall_ind {label_after = _}) ->
+ let n = frame_size() in
+ if !contains_calls then
+ ` {emit_string lg} ra, {emit_int(n - size_addr)}(sp)\n`;
+ if n > 0 then
+ ` addi sp, sp, {emit_int n}\n`;
+ if !contains_calls then reload_ra n;
+ emit_stack_adjustment n;
+ ` jr {emit_reg i.arg.(0)}\n`
+ | Lop(Itailcall_imm {func; label_after = _}) ->
+ if func = !function_name then begin
+ ` j {emit_label !tailrec_entry_point}\n`
+ end else begin
+ let n = frame_size() in
+ if !contains_calls then
+ ` {emit_string lg} ra, {emit_int(n - size_addr)}(sp)\n`;
+ if n > 0 then
+ ` addi sp, sp, {emit_int n}\n`;
+ if !contains_calls then reload_ra n;
+ emit_stack_adjustment n;
+ ` tail {emit_symbol func}\n`
+ end
+ | Lop(Iextcall{func; alloc = true; label_after = label}) ->
@ -462,7 +503,7 @@ index 000000000..6d0e3aefd
+ ` call {emit_symbol func}\n`
+ | Lop(Istackoffset n) ->
+ assert (n mod 16 = 0);
+ ` addi sp, sp, {emit_int (-n)}\n`;
+ emit_stack_adjustment (-n);
+ stack_offset := !stack_offset + n
+ | Lop(Iload(Single, Iindexed ofs)) ->
+ ` flw {emit_reg i.res.(0)}, {emit_int ofs}({emit_reg i.arg.(0)})\n`;
@ -570,13 +611,14 @@ index 000000000..6d0e3aefd
+ | Lop(Ispecific sop) ->
+ let instr = name_for_specific sop in
+ ` {emit_string instr} {emit_reg i.res.(0)}, {emit_reg i.arg.(0)}, {emit_reg i.arg.(1)}, {emit_reg i.arg.(2)}\n`
+ | Lop (Iname_for_debugger _) ->
+ ()
+ | Lreloadretaddr ->
+ let n = frame_size () in
+ ` {emit_string lg} ra, {emit_int(n - size_addr)}(sp)\n`
+ reload_ra n
+ | Lreturn ->
+ let n = frame_size() in
+ if n > 0 then
+ ` addi sp, sp, {emit_int n}\n`;
+ emit_stack_adjustment n;
+ ` ret\n`
+ | Llabel lbl ->
+ `{emit_label lbl}:\n`
@ -690,10 +732,8 @@ index 000000000..6d0e3aefd
+ ` .align 2\n`;
+ `{emit_symbol fundecl.fun_name}:\n`;
+ let n = frame_size() in
+ if n > 0 then
+ ` addi sp, sp, {emit_int(-n)}\n`;
+ if !contains_calls then
+ ` {emit_string stg} ra, {emit_int(n - size_addr)}(sp)\n`;
+ emit_stack_adjustment (-n);
+ if !contains_calls then store_ra n;
+ `{emit_label !tailrec_entry_point}:\n`;
+ emit_all fundecl.fun_body;
+ List.iter emit_call_gc !call_gc_sites;
@ -753,6 +793,7 @@ index 000000000..6d0e3aefd
+(* Beginning / end of an assembly file *)
+
+let begin_assembly() =
+ ` .file \"\"\n`; (* PR#7073 *)
+ (* Emit the beginning of the segments *)
+ let lbl_begin = Compilenv.make_symbol (Some "data_begin") in
+ ` {emit_string data_space}\n`;
@ -1147,10 +1188,10 @@ index 000000000..e436be1cc
+let fundecl f = f
diff --git a/asmcomp/riscv/selection.ml b/asmcomp/riscv/selection.ml
new file mode 100644
index 000000000..60ec5cb4e
index 000000000..092ca88aa
--- /dev/null
+++ b/asmcomp/riscv/selection.ml
@@ -0,0 +1,85 @@
@@ -0,0 +1,72 @@
+(***********************************************************************)
+(* *)
+(* OCaml *)
@ -1175,60 +1216,47 @@ index 000000000..60ec5cb4e
+
+inherit Selectgen.selector_generic as super
+
+method is_immediate n = (n <= 0x7FF) && (n >= -0x800)
+method is_immediate n = is_immediate n
+
+method select_addressing _ = function
+ | Cop(Cadda, [arg; Cconst_int n]) when self#is_immediate n ->
+ | Cop(Cadda, [arg; Cconst_int n], _) when self#is_immediate n ->
+ (Iindexed n, arg)
+ | Cop(Cadda, [arg1; Cop(Caddi, [arg2; Cconst_int n])]) when self#is_immediate n ->
+ (Iindexed n, Cop(Caddi, [arg1; arg2]))
+ | Cop(Cadda, [arg1; Cop(Caddi, [arg2; Cconst_int n], _)], dbg) when self#is_immediate n ->
+ (Iindexed n, Cop(Caddi, [arg1; arg2], dbg))
+ | arg ->
+ (Iindexed 0, arg)
+
+method! select_operation op args =
+method! select_operation op args dbg =
+ match (op, args) with
+ (* RISC-V does not support immediate operands for multiply high *)
+ | (Cmulhi, _) -> (Iintop Imulh, args)
+ (* The and, or and xor instructions have a different range of immediate
+ operands than the other instructions *)
+ | (Cand, _) -> self#select_logical Iand args
+ | (Cor, _) -> self#select_logical Ior args
+ | (Cxor, _) -> self#select_logical Ixor args
+ (* Recognize (neg-)mult-add and (neg-)mult-sub instructions *)
+ | (Caddf, [Cop(Cmulf, [arg1; arg2]); arg3])
+ | (Caddf, [arg3; Cop(Cmulf, [arg1; arg2])]) ->
+ | (Caddf, [Cop(Cmulf, [arg1; arg2], _); arg3])
+ | (Caddf, [arg3; Cop(Cmulf, [arg1; arg2], _)]) ->
+ (Ispecific (Imultaddf false), [arg1; arg2; arg3])
+ | (Csubf, [Cop(Cmulf, [arg1; arg2]); arg3]) ->
+ | (Csubf, [Cop(Cmulf, [arg1; arg2], _); arg3]) ->
+ (Ispecific (Imultsubf false), [arg1; arg2; arg3])
+ | (Cnegf, [Cop(Csubf, [Cop(Cmulf, [arg1; arg2]); arg3])]) ->
+ | (Cnegf, [Cop(Csubf, [Cop(Cmulf, [arg1; arg2], _); arg3], _)]) ->
+ (Ispecific (Imultsubf true), [arg1; arg2; arg3])
+ | (Cnegf, [Cop(Caddf, [Cop(Cmulf, [arg1; arg2]); arg3])]) ->
+ | (Cnegf, [Cop(Caddf, [Cop(Cmulf, [arg1; arg2], _); arg3], _)]) ->
+ (Ispecific (Imultaddf true), [arg1; arg2; arg3])
+ (* RISC-V does not support immediate operands for comparison operators *)
+ | (Ccmpi comp, args) -> (Iintop(Icomp (Isigned comp)), args)
+ | (Ccmpa comp, args) -> (Iintop(Icomp (Iunsigned comp)), args)
+ | (Cmuli, _) -> (Iintop Imul, args)
+ | _ ->
+ super#select_operation op args
+
+method select_logical op = function
+ | [arg; Cconst_int n] when n >= 0 && n <= 0xFFF ->
+ (Iintop_imm(op, n), [arg])
+ | [Cconst_int n; arg] when n >= 0 && n <= 0xFFF ->
+ (Iintop_imm(op, n), [arg])
+ | args ->
+ (Iintop op, args)
+ super#select_operation op args dbg
+
+(* Instruction selection for conditionals *)
+
+method! select_condition = function
+ | Cop(Ccmpi cmp, args) ->
+ | Cop(Ccmpi cmp, args, _) ->
+ (Iinttest(Isigned cmp), Ctuple args)
+ | Cop(Ccmpa cmp, args) ->
+ | Cop(Ccmpa cmp, args, _) ->
+ (Iinttest(Iunsigned cmp), Ctuple args)
+ | Cop(Ccmpf cmp, args) ->
+ | Cop(Ccmpf cmp, args, _) ->
+ (Ifloattest(cmp, false), Ctuple args)
+ | Cop(Cand, [arg; Cconst_int 1]) ->
+ | Cop(Cand, [arg; Cconst_int 1], _) ->
+ (Ioddtest, arg)
+ | arg ->
+ (Itruetest, arg)
@ -1667,10 +1695,10 @@ index 000000000..a82048efc
+ .align 3
+ .size caml_system__frametable, .-caml_system__frametable
diff --git a/byterun/caml/stack.h b/byterun/caml/stack.h
index fd9d528e9..781c2517b 100644
index 266863986..e198be0a6 100644
--- a/byterun/caml/stack.h
+++ b/byterun/caml/stack.h
@@ -75,6 +75,11 @@
@@ -70,6 +70,11 @@
#define Callback_link(sp) ((struct caml_context *)((sp) + 16))
#endif
@ -1682,11 +1710,34 @@ index fd9d528e9..781c2517b 100644
/* Structure of OCaml callback contexts */
struct caml_context {
diff --git a/config/gnu/config.guess b/config/gnu/config.guess
index b79252d6b..8335398b2 100755
--- a/config/gnu/config.guess
+++ b/config/gnu/config.guess
@@ -2,7 +2,7 @@
# Attempt to guess a canonical system name.
# Copyright 1992-2013 Free Software Foundation, Inc.
-timestamp='2013-06-10'
+timestamp='2016-10-23'
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by
@@ -1001,6 +1001,9 @@ EOF
ppcle:Linux:*:*)
echo powerpcle-unknown-linux-${LIBC}
exit ;;
+ riscv*:Linux:*:*)
+ echo ${UNAME_MACHINE}-unknown-linux
+ exit ;;
s390:Linux:*:* | s390x:Linux:*:*)
echo ${UNAME_MACHINE}-ibm-linux-${LIBC}
exit ;;
diff --git a/configure b/configure
index 786f4cdbe..b88dab26b 100755
index 9311589cf..b0c3b9fc6 100755
--- a/configure
+++ b/configure
@@ -854,6 +854,7 @@ if test $with_sharedlibs = "yes"; then
@@ -922,6 +922,7 @@ if $with_sharedlibs; then
arm*-*-freebsd*) natdynlink=true;;
earm*-*-netbsd*) natdynlink=true;;
aarch64-*-linux*) natdynlink=true;;
@ -1694,7 +1745,7 @@ index 786f4cdbe..b88dab26b 100755
esac
fi
@@ -947,6 +948,8 @@ case "$target" in
@@ -996,6 +997,8 @@ case "$target" in
x86_64-*-mingw*) arch=amd64; system=mingw;;
aarch64-*-linux*) arch=arm64; system=linux;;
x86_64-*-cygwin*) arch=amd64; system=cygwin;;
@ -1703,12 +1754,12 @@ index 786f4cdbe..b88dab26b 100755
esac
# Some platforms exist both in 32-bit and 64-bit variants, not distinguished
@@ -1023,7 +1026,7 @@ case "$arch,$system" in
@@ -1054,7 +1057,7 @@ case "$arch,$system" in
aspp="${TOOLPREF}cc -c";;
*,freebsd) as="${TOOLPREF}as"
aspp="${TOOLPREF}cc -c";;
- amd64,*|arm,*|arm64,*|i386,*|power,bsd*|sparc,*)
+ amd64,*|arm,*|arm64,*|i386,*|power,bsd*|sparc,*|riscv,*)
- amd64,*|arm,*|arm64,*|i386,*|power,bsd*|power,netbsd)
+ amd64,*|arm,*|arm64,*|i386,*|power,bsd*|power,netbsd|riscv,*)
as="${TOOLPREF}as"
case "$ccfamily" in
clang-*)

35
0007-Adapt-config.guess-for-RISC-V.patch
View File

@ -1,35 +0,0 @@
From 68a8eb8f3bbc254cd5cb685f058bc5b0ef1029e7 Mon Sep 17 00:00:00 2001
From: Nicolas Ojeda Bar <n.oje.bar@gmail.com>
Date: Tue, 8 Nov 2016 23:56:50 +0100
Subject: [PATCH 07/12] Adapt config.guess for RISC-V
---
config/gnu/config.guess | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/config/gnu/config.guess b/config/gnu/config.guess
index b79252d6b..8335398b2 100755
--- a/config/gnu/config.guess
+++ b/config/gnu/config.guess
@@ -2,7 +2,7 @@
# Attempt to guess a canonical system name.
# Copyright 1992-2013 Free Software Foundation, Inc.
-timestamp='2013-06-10'
+timestamp='2016-10-23'
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by
@@ -1001,6 +1001,9 @@ EOF
ppcle:Linux:*:*)
echo powerpcle-unknown-linux-${LIBC}
exit ;;
+ riscv*:Linux:*:*)
+ echo ${UNAME_MACHINE}-unknown-linux
+ exit ;;
s390:Linux:*:* | s390x:Linux:*:*)
echo ${UNAME_MACHINE}-ibm-linux-${LIBC}
exit ;;
--
2.13.2

43
0009-Try-fix-for-andi-ori-xori-immediates-1.patch
View File

@ -1,43 +0,0 @@
From 84a4b62e1305795f6599c91a50b6e0d9e675cbd5 Mon Sep 17 00:00:00 2001
From: Nicolas Ojeda Bar <n.oje.bar@gmail.com>
Date: Thu, 10 Nov 2016 14:12:53 +0100
Subject: [PATCH 09/12] Try fix for andi/ori/xori immediates (#1)
---
asmcomp/riscv/selection.ml | 13 -------------
1 file changed, 13 deletions(-)
diff --git a/asmcomp/riscv/selection.ml b/asmcomp/riscv/selection.ml
index 60ec5cb4e..ad2b26e9b 100644
--- a/asmcomp/riscv/selection.ml
+++ b/asmcomp/riscv/selection.ml
@@ -36,11 +36,6 @@ method! select_operation op args =
match (op, args) with
(* RISC-V does not support immediate operands for multiply high *)
| (Cmulhi, _) -> (Iintop Imulh, args)
- (* The and, or and xor instructions have a different range of immediate
- operands than the other instructions *)
- | (Cand, _) -> self#select_logical Iand args
- | (Cor, _) -> self#select_logical Ior args
- | (Cxor, _) -> self#select_logical Ixor args
(* Recognize (neg-)mult-add and (neg-)mult-sub instructions *)
| (Caddf, [Cop(Cmulf, [arg1; arg2]); arg3])
| (Caddf, [arg3; Cop(Cmulf, [arg1; arg2])]) ->
@@ -58,14 +53,6 @@ method! select_operation op args =
| _ ->
super#select_operation op args
-method select_logical op = function
- | [arg; Cconst_int n] when n >= 0 && n <= 0xFFF ->
- (Iintop_imm(op, n), [arg])
- | [Cconst_int n; arg] when n >= 0 && n <= 0xFFF ->
- (Iintop_imm(op, n), [arg])
- | args ->
- (Iintop op, args)
-
(* Instruction selection for conditionals *)
method! select_condition = function
--
2.13.2

156
0010-Fix-immediates-range-when-adjusting-indexing-sp.patch
View File

@ -1,156 +0,0 @@
From bf083b3beeb9a622017137c246d2cfa863056cc0 Mon Sep 17 00:00:00 2001
From: Nicolas Ojeda Bar <n.oje.bar@gmail.com>
Date: Tue, 22 Nov 2016 22:30:35 +0100
Subject: [PATCH 10/12] Fix immediates' range when adjusting/indexing sp
---
asmcomp/riscv/arch.ml | 3 +++
asmcomp/riscv/emit.mlp | 53 ++++++++++++++++++++++++++++++++++------------
asmcomp/riscv/selection.ml | 2 +-
3 files changed, 44 insertions(+), 14 deletions(-)
diff --git a/asmcomp/riscv/arch.ml b/asmcomp/riscv/arch.ml
index 61a38b1dd..22c807c49 100644
--- a/asmcomp/riscv/arch.ml
+++ b/asmcomp/riscv/arch.ml
@@ -32,6 +32,9 @@ let spacetime_node_hole_pointer_is_live_before = function
type addressing_mode =
| Iindexed of int (* reg + displ *)
+let is_immediate n =
+ (n <= 2047) && (n >= -2048)
+
(* Sizes, endianness *)
let big_endian = false
diff --git a/asmcomp/riscv/emit.mlp b/asmcomp/riscv/emit.mlp
index 6d0e3aefd..97c49ce80 100644
--- a/asmcomp/riscv/emit.mlp
+++ b/asmcomp/riscv/emit.mlp
@@ -93,6 +93,34 @@ let emit_stack r =
let ofs = slot_offset s (register_class r) in `{emit_int ofs}(sp)`
| _ -> fatal_error "Emit.emit_stack"
+(* Adjust sp by the given byte amount *)
+
+let emit_stack_adjustment = function
+ | 0 -> ()
+ | n when is_immediate n ->
+ ` addi sp, sp, {emit_int n}\n`
+ | n ->
+ ` li {emit_reg reg_tmp1}, {emit_int n}\n`;
+ ` add sp, sp, {emit_reg reg_tmp1}\n`
+
+let emit_store src ofs =
+ if is_immediate ofs then
+ ` {emit_string stg} {emit_reg src}, {emit_int ofs}(sp)\n`
+ else begin
+ ` li {emit_reg reg_tmp1}, {emit_int ofs}\n`;
+ ` add {emit_reg reg_tmp1}, sp, {emit_reg reg_tmp1}\n`;
+ ` {emit_string stg} {emit_reg src}, 0({emit_reg reg_tmp1})\n`
+ end
+
+let emit_load dst ofs =
+ if is_immediate ofs then
+ ` {emit_string lg} {emit_reg dst}, {emit_int ofs}(sp)\n`
+ else begin
+ ` li {emit_reg reg_tmp1}, {emit_int ofs}\n`;
+ ` add {emit_reg reg_tmp1}, sp, {emit_reg reg_tmp1}\n`;
+ ` {emit_string lg} {emit_reg dst}, 0({emit_reg reg_tmp1})\n`
+ end
+
(* Record live pointers at call points *)
let record_frame_label ?label live raise_ dbg =
@@ -218,6 +246,7 @@ let name_for_specific = function
(* Name of current function *)
let function_name = ref ""
+
(* Entry point for tail recursive calls *)
let tailrec_entry_point = ref 0
@@ -234,12 +263,14 @@ let emit_instr i =
` mv {emit_reg dst}, {emit_reg src}\n`
| {loc = Reg _; typ = Float}, {loc = Reg _; typ = Float} ->
` fmv.d {emit_reg dst}, {emit_reg src}\n`
- | {loc = Reg _; typ = (Val | Int | Addr)}, {loc = Stack _} ->
- ` {emit_string stg} {emit_reg src}, {emit_stack dst}\n`
+ | {loc = Reg _; typ = (Val | Int | Addr)}, {loc = Stack s} ->
+ let ofs = slot_offset s (register_class dst) in
+ emit_store src ofs
| {loc = Reg _; typ = Float}, {loc = Stack _} ->
` fsd {emit_reg src}, {emit_stack dst}\n`
- | {loc = Stack _; typ = (Val | Int | Addr)}, {loc = Reg _ } ->
- ` {emit_string lg} {emit_reg dst}, {emit_stack src}\n`
+ | {loc = Stack s; typ = (Val | Int | Addr)}, {loc = Reg _} ->
+ let ofs = slot_offset s (register_class src) in
+ emit_load dst ofs
| {loc = Stack _; typ = Float}, {loc = Reg _} ->
` fld {emit_reg dst}, {emit_stack src}\n`
| _ ->
@@ -263,8 +294,7 @@ let emit_instr i =
let n = frame_size() in
if !contains_calls then
` {emit_string lg} ra, {emit_int(n - size_addr)}(sp)\n`;
- if n > 0 then
- ` addi sp, sp, {emit_int n}\n`;
+ emit_stack_adjustment n;
` jr {emit_reg i.arg.(0)}\n`
| Lop(Itailcall_imm {func; label_after = _}) ->
if func = !function_name then begin
@@ -273,8 +303,7 @@ let emit_instr i =
let n = frame_size() in
if !contains_calls then
` {emit_string lg} ra, {emit_int(n - size_addr)}(sp)\n`;
- if n > 0 then
- ` addi sp, sp, {emit_int n}\n`;
+ emit_stack_adjustment n;
` tail {emit_symbol func}\n`
end
| Lop(Iextcall{func; alloc = true; label_after = label}) ->
@@ -285,7 +314,7 @@ let emit_instr i =
` call {emit_symbol func}\n`
| Lop(Istackoffset n) ->
assert (n mod 16 = 0);
- ` addi sp, sp, {emit_int (-n)}\n`;
+ emit_stack_adjustment (-n);
stack_offset := !stack_offset + n
| Lop(Iload(Single, Iindexed ofs)) ->
` flw {emit_reg i.res.(0)}, {emit_int ofs}({emit_reg i.arg.(0)})\n`;
@@ -398,8 +427,7 @@ let emit_instr i =
` {emit_string lg} ra, {emit_int(n - size_addr)}(sp)\n`
| Lreturn ->
let n = frame_size() in
- if n > 0 then
- ` addi sp, sp, {emit_int n}\n`;
+ emit_stack_adjustment n;
` ret\n`
| Llabel lbl ->
`{emit_label lbl}:\n`
@@ -513,8 +541,7 @@ let fundecl fundecl =
` .align 2\n`;
`{emit_symbol fundecl.fun_name}:\n`;
let n = frame_size() in
- if n > 0 then
- ` addi sp, sp, {emit_int(-n)}\n`;
+ emit_stack_adjustment (-n);
if !contains_calls then
` {emit_string stg} ra, {emit_int(n - size_addr)}(sp)\n`;
`{emit_label !tailrec_entry_point}:\n`;
diff --git a/asmcomp/riscv/selection.ml b/asmcomp/riscv/selection.ml
index ad2b26e9b..283233679 100644
--- a/asmcomp/riscv/selection.ml
+++ b/asmcomp/riscv/selection.ml
@@ -22,7 +22,7 @@ class selector = object (self)
inherit Selectgen.selector_generic as super
-method is_immediate n = (n <= 0x7FF) && (n >= -0x800)
+method is_immediate n = is_immediate n
method select_addressing _ = function
| Cop(Cadda, [arg; Cconst_int n]) when self#is_immediate n ->
--
2.13.2

131
0011-Another-immediate-range-fix.patch
View File

@ -1,131 +0,0 @@
From 9e8d87c255713f7bf397083be9e6453d312c93a3 Mon Sep 17 00:00:00 2001
From: Nicolas Ojeda Bar <n.oje.bar@gmail.com>
Date: Wed, 23 Nov 2016 12:38:28 +0100
Subject: [PATCH 11/12] Another immediate range fix
---
asmcomp/riscv/emit.mlp | 57 ++++++++++++++++++++++++++++++--------------------
1 file changed, 34 insertions(+), 23 deletions(-)
diff --git a/asmcomp/riscv/emit.mlp b/asmcomp/riscv/emit.mlp
index 97c49ce80..6cc190864 100644
--- a/asmcomp/riscv/emit.mlp
+++ b/asmcomp/riscv/emit.mlp
@@ -85,14 +85,6 @@ let emit_reg = function
| {loc = Reg r} -> emit_string (register_name r)
| _ -> fatal_error "Emit.emit_reg"
-(* Output a stack reference *)
-
-let emit_stack r =
- match r.loc with
- Stack s ->
- let ofs = slot_offset s (register_class r) in `{emit_int ofs}(sp)`
- | _ -> fatal_error "Emit.emit_stack"
-
(* Adjust sp by the given byte amount *)
let emit_stack_adjustment = function
@@ -103,7 +95,27 @@ let emit_stack_adjustment = function
` li {emit_reg reg_tmp1}, {emit_int n}\n`;
` add sp, sp, {emit_reg reg_tmp1}\n`
-let emit_store src ofs =
+let reload_ra n =
+ let ofs = n - size_addr in
+ if is_immediate ofs then
+ ` {emit_string lg} ra, {emit_int ofs}(sp)\n`
+ else begin
+ ` li {emit_reg reg_tmp1}, {emit_int ofs}\n`;
+ ` add {emit_reg reg_tmp1}, sp, {emit_reg reg_tmp1}\n`;
+ ` {emit_string lg} ra, 0({emit_reg reg_tmp1})\n`
+ end
+
+let store_ra n =
+ let ofs = n - size_addr in
+ if is_immediate ofs then
+ ` {emit_string stg} ra, {emit_int(n - size_addr)}(sp)\n`
+ else begin
+ ` li {emit_reg reg_tmp1}, {emit_int ofs}\n`;
+ ` add {emit_reg reg_tmp1}, sp, {emit_reg reg_tmp1}\n`;
+ ` {emit_string stg} ra, 0({emit_reg reg_tmp1})\n`
+ end
+
+let emit_store stg src ofs =
if is_immediate ofs then
` {emit_string stg} {emit_reg src}, {emit_int ofs}(sp)\n`
else begin
@@ -112,7 +124,7 @@ let emit_store src ofs =
` {emit_string stg} {emit_reg src}, 0({emit_reg reg_tmp1})\n`
end
-let emit_load dst ofs =
+let emit_load lg dst ofs =
if is_immediate ofs then
` {emit_string lg} {emit_reg dst}, {emit_int ofs}(sp)\n`
else begin
@@ -265,14 +277,16 @@ let emit_instr i =
` fmv.d {emit_reg dst}, {emit_reg src}\n`
| {loc = Reg _; typ = (Val | Int | Addr)}, {loc = Stack s} ->
let ofs = slot_offset s (register_class dst) in
- emit_store src ofs
- | {loc = Reg _; typ = Float}, {loc = Stack _} ->
- ` fsd {emit_reg src}, {emit_stack dst}\n`
+ emit_store stg src ofs
+ | {loc = Reg _; typ = Float}, {loc = Stack s} ->
+ let ofs = slot_offset s (register_class dst) in
+ emit_store "fsd" src ofs
| {loc = Stack s; typ = (Val | Int | Addr)}, {loc = Reg _} ->
let ofs = slot_offset s (register_class src) in
- emit_load dst ofs
- | {loc = Stack _; typ = Float}, {loc = Reg _} ->
- ` fld {emit_reg dst}, {emit_stack src}\n`
+ emit_load lg dst ofs
+ | {loc = Stack s; typ = Float}, {loc = Reg _} ->
+ let ofs = slot_offset s (register_class src) in
+ emit_load "fld" dst ofs
| _ ->
fatal_error "Emit: Imove"
end
@@ -292,8 +306,7 @@ let emit_instr i =
record_frame ~label i.live false i.dbg
| Lop(Itailcall_ind {label_after = _}) ->
let n = frame_size() in
- if !contains_calls then
- ` {emit_string lg} ra, {emit_int(n - size_addr)}(sp)\n`;
+ if !contains_calls then reload_ra n;
emit_stack_adjustment n;
` jr {emit_reg i.arg.(0)}\n`
| Lop(Itailcall_imm {func; label_after = _}) ->
@@ -301,8 +314,7 @@ let emit_instr i =
` j {emit_label !tailrec_entry_point}\n`
end else begin
let n = frame_size() in
- if !contains_calls then
- ` {emit_string lg} ra, {emit_int(n - size_addr)}(sp)\n`;
+ if !contains_calls then reload_ra n;
emit_stack_adjustment n;
` tail {emit_symbol func}\n`
end
@@ -424,7 +436,7 @@ let emit_instr i =
` {emit_string instr} {emit_reg i.res.(0)}, {emit_reg i.arg.(0)}, {emit_reg i.arg.(1)}, {emit_reg i.arg.(2)}\n`
| Lreloadretaddr ->
let n = frame_size () in
- ` {emit_string lg} ra, {emit_int(n - size_addr)}(sp)\n`
+ reload_ra n
| Lreturn ->
let n = frame_size() in
emit_stack_adjustment n;
@@ -542,8 +554,7 @@ let fundecl fundecl =
`{emit_symbol fundecl.fun_name}:\n`;
let n = frame_size() in
emit_stack_adjustment (-n);
- if !contains_calls then
- ` {emit_string stg} ra, {emit_int(n - size_addr)}(sp)\n`;
+ if !contains_calls then store_ra n;
`{emit_label !tailrec_entry_point}:\n`;
emit_all fundecl.fun_body;
List.iter emit_call_gc !call_gc_sites;
--
2.13.2

98
0012-AArch64-GOT-fixed.patch
View File

@ -1,98 +0,0 @@
From c428a156b8e659a884d4867e52c49534125dc72f Mon Sep 17 00:00:00 2001
From: Mark Shinwell <mshinwell@gmail.com>
Date: Wed, 13 Sep 2017 10:23:16 +0100
Subject: [PATCH 12/12] AArch64 GOT fixed
---
Changes | 4 ++++
asmcomp/arm64/emit.mlp | 15 +++++++++++++--
asmcomp/arm64/selection.ml | 4 ++--
3 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/Changes b/Changes
index e8dbd42e2..b84a1f30e 100644
--- a/Changes
+++ b/Changes
@@ -150,6 +150,10 @@ OCaml 4.05.0 (13 Jul 2017):
(Hannes Mehnert, Guillaume Bury,
review by Daniel Bünzli, Gabriel Scherer, Damien Doligez)
+- GPR#1330: when generating dynamically-linkable code on AArch64, always
+ reference symbols (even locally-defined ones) through the GOT.
+ (Mark Shinwell, review by Xavier Leroy)
+
### Standard library:
- MPR#6975, GPR#902: Truncate function added to stdlib Buffer module
diff --git a/asmcomp/arm64/emit.mlp b/asmcomp/arm64/emit.mlp
index f75646e12..729096c57 100644
--- a/asmcomp/arm64/emit.mlp
+++ b/asmcomp/arm64/emit.mlp
@@ -114,6 +114,7 @@ let emit_addressing addr r =
| Iindexed ofs ->
`[{emit_reg r}, #{emit_int ofs}]`
| Ibased(s, ofs) ->
+ assert (not !Clflags.dlcode); (* see selection.ml *)
`[{emit_reg r}, #:lo12:{emit_symbol_offset s ofs}]`
(* Record live pointers at call points *)
@@ -323,7 +324,7 @@ let emit_literals() =
(* Emit code to load the address of a symbol *)
let emit_load_symbol_addr dst s =
- if (not !Clflags.dlcode) || Compilenv.symbol_in_current_unit s then begin
+ if not !Clflags.dlcode then begin
` adrp {emit_reg dst}, {emit_symbol s}\n`;
` add {emit_reg dst}, {emit_reg dst}, #:lo12:{emit_symbol s}\n`
end else begin
@@ -609,6 +610,7 @@ let emit_instr i =
match addr with
| Iindexed _ -> i.arg.(0)
| Ibased(s, ofs) ->
+ assert (not !Clflags.dlcode); (* see selection.ml *)
` adrp {emit_reg reg_tmp1}, {emit_symbol_offset s ofs}\n`;
reg_tmp1 in
begin match size with
@@ -636,6 +638,7 @@ let emit_instr i =
match addr with
| Iindexed _ -> i.arg.(1)
| Ibased(s, ofs) ->
+ assert (not !Clflags.dlcode);
` adrp {emit_reg reg_tmp1}, {emit_symbol_offset s ofs}\n`;
reg_tmp1 in
begin match size with
@@ -924,7 +927,15 @@ let fundecl fundecl =
let emit_item = function
| Cglobal_symbol s -> ` .globl {emit_symbol s}\n`;
- | Cdefine_symbol s -> `{emit_symbol s}:\n`
+ | Cdefine_symbol s ->
+ if !Clflags.dlcode then begin
+ (* GOT relocations against non-global symbols don't seem to work
+ properly: GOT entries are not created for the symbols and the
+ relocations evaluate to random other GOT entries. For the moment
+ force all symbols to be global. *)
+ ` .globl {emit_symbol s}\n`;
+ end;
+ `{emit_symbol s}:\n`
| Cint8 n -> ` .byte {emit_int n}\n`
| Cint16 n -> ` .short {emit_int n}\n`
| Cint32 n -> ` .long {emit_nativeint n}\n`
diff --git a/asmcomp/arm64/selection.ml b/asmcomp/arm64/selection.ml
index d8ea7f83b..b714d0032 100644
--- a/asmcomp/arm64/selection.ml
+++ b/asmcomp/arm64/selection.ml
@@ -82,8 +82,8 @@ let inline_ops =
[ "sqrt"; "caml_bswap16_direct"; "caml_int32_direct_bswap";
"caml_int64_direct_bswap"; "caml_nativeint_direct_bswap" ]
-let use_direct_addressing symb =
- (not !Clflags.dlcode) || Compilenv.symbol_in_current_unit symb
+let use_direct_addressing _symb =
+ not !Clflags.dlcode
(* Instruction selection *)
--
2.13.2

54
ocaml.spec
View File

@ -26,8 +26,8 @@
#%global no_parallel_build_arches aarch64
Name: ocaml
Version: 4.05.0
Release: 4%{?dist}
Version: 4.06.0
Release: 1%{?dist}
Summary: OCaml compiler and programming environment
@ -35,11 +35,11 @@ License: QPL and (LGPLv2+ with exceptions)
URL: http://www.ocaml.org
Source0: http://caml.inria.fr/pub/distrib/ocaml-4.05/ocaml-%{version}.tar.xz
Source0: http://caml.inria.fr/pub/distrib/ocaml-4.06/ocaml-%{version}.tar.xz
Source1: http://caml.inria.fr/pub/distrib/ocaml-4.05/ocaml-4.05-refman-html.tar.gz
Source2: http://caml.inria.fr/pub/distrib/ocaml-4.05/ocaml-4.05-refman.pdf
Source3: http://caml.inria.fr/pub/distrib/ocaml-4.05/ocaml-4.05-refman.info.tar.gz
Source1: http://caml.inria.fr/pub/distrib/ocaml-4.06/ocaml-4.06-refman-html.tar.gz
Source2: http://caml.inria.fr/pub/distrib/ocaml-4.06/ocaml-4.06-refman.pdf
Source3: http://caml.inria.fr/pub/distrib/ocaml-4.06/ocaml-4.06-refman.info.tar.gz
# IMPORTANT NOTE:
#
@ -50,34 +50,21 @@ Source3: http://caml.inria.fr/pub/distrib/ocaml-4.05/ocaml-4.05-refman.in
#
# https://pagure.io/fedora-ocaml
#
# Current branch: fedora-27-4.05.0
# Current branch: fedora-28-4.06.0
#
# ALTERNATIVELY add a patch to the end of the list (leaving the
# existing patches unchanged) adding a comment to note that it should
# be incorporated into the git repo at a later time.
#
# Upstream patches after 4.05.
Patch0001: 0001-Changes-clarify-compatibility-breaking-change-items.patch
Patch0002: 0002-MPR-7591-frametable-not-8-aligned-on-x86-64-port.patch
Patch0003: 0003-Fixes-for-out-of-range-Ialloc.patch
# Fedora-specific downstream patches.
Patch0004: 0004-Don-t-add-rpaths-to-libraries.patch
Patch0005: 0005-ocamlbyteinfo-ocamlplugininfo-Useful-utilities-from-.patch
Patch0006: 0006-configure-Allow-user-defined-C-compiler-flags.patch
Patch0001: 0001-Don-t-add-rpaths-to-libraries.patch
Patch0002: 0002-ocamlbyteinfo-ocamlplugininfo-Useful-utilities-from-.patch
Patch0003: 0003-configure-Allow-user-defined-C-compiler-flags.patch
# Out of tree patches for RISC-V support.
# Out of tree patch for RISC-V support.
# https://github.com/nojb/riscv-ocaml
Patch0007: 0007-Adapt-config.guess-for-RISC-V.patch
Patch0008: 0008-Add-RISC-V-backend-runtime.patch
Patch0009: 0009-Try-fix-for-andi-ori-xori-immediates-1.patch
Patch0010: 0010-Fix-immediates-range-when-adjusting-indexing-sp.patch
Patch0011: 0011-Another-immediate-range-fix.patch
# Fix for some aarch64 linker problems.
# https://caml.inria.fr/mantis/view.php?id=7585
Patch0012: 0012-AArch64-GOT-fixed.patch
Patch0004: 0004-Add-RISC-V-backend.patch
BuildRequires: binutils-devel
BuildRequires: ncurses-devel
@ -216,14 +203,12 @@ cp %{SOURCE2} refman.pdf
%build
# Parallel builds are broken in 4.05.0, see
# https://caml.inria.fr/mantis/view.php?id=7587
#%ifnarch %{no_parallel_build_arches}
#make="make %{?_smp_mflags}"
#%else
%ifnarch %{no_parallel_build_arches}
make="make %{?_smp_mflags}"
%else
unset MAKEFLAGS
make=make
#%endif
%endif
CFLAGS="$RPM_OPT_FLAGS -fno-strict-aliasing" \
./configure \
@ -322,6 +307,7 @@ fi
%{_bindir}/ocaml
%{_bindir}/ocamlbyteinfo
%{_bindir}/ocamlcmt
%{_bindir}/ocamldebug
#%{_bindir}/ocamlplugininfo
%{_bindir}/ocamlyacc
@ -467,6 +453,12 @@ fi
%changelog
* Mon Nov 06 2017 Richard W.M. Jones <rjones@redhat.com> - 4.06.0-1
- New upstream version 4.06.0.
- Enable parallel builds again.
- Rebase patches.
- New binary ocamlcmt.
* Wed Sep 13 2017 Richard W.M. Jones <rjones@redhat.com> - 4.05.0-4
- Add final upstream fix for aarch64/binutils relocation problems.
https://github.com/ocaml/ocaml/pull/1330

8
sources
View File

@ -1,4 +1,4 @@
SHA512 (ocaml-4.05.0.tar.xz) = e87bb25d8a580f608ea3c8308129c4e4f4513e9bb3d218a5038a67b3f39b06656ff6ebe08a4b6f36960fb603be62e6bef2694fc3cf1b0fa0df3a1ca177d4e004
SHA512 (ocaml-4.05-refman-html.tar.gz) = a01aef22015cfcb1d230e63f24f2deeba6a8bc1a1225152e346a15e3a52be261d7f22430e561c7cbf64fbc53d3fa13606b87823efb56d139cf5e988c9a326af8
SHA512 (ocaml-4.05-refman.info.tar.gz) = 49cd780445576061e89cf46690a5f7297d5b2c92446e6fc0e2d8878089e6b18e235785d5eb658e508a15c2bfbdd4a1c990b6eca7dadb4b4a7f313e1a8f3d0642
SHA512 (ocaml-4.05-refman.pdf) = 2190deef5f89064774236790a130c036fe7d615177ce7e17c17a60b4d8500f78a75e15157fe13cf47125219ad731d04fb1339692047aced1ee9d768aae2a8038
SHA512 (ocaml-4.06.0.tar.xz) = c1cdba3fa52ef03ca534b7a4932cfe29bbbc79b587d35ed7f6906eb09a5e5af97540def03b1e01c63dd2311dc4e5a6d02378d541d14688191e4f9302aff79c23
SHA512 (ocaml-4.06-refman-html.tar.gz) = 6a9e534a2d7e07650237f5a8bf9b6894fd0f9c32385d272ac53fe32779b4f6d0a623c94e0f92a2351f6614fcebf3d35fdd843752b509341ec1abcaee14f5a0ff
SHA512 (ocaml-4.06-refman.info.tar.gz) = b4665bb44023c6a8ec37b7c5979ffccf97f4f98708073f4e9ed64b61c04455bf0641d191ded3f750d7ed528eea92ad636056016dd87114bd9beab2a78a4503a9
SHA512 (ocaml-4.06-refman.pdf) = 982e7481bf86620c230d3620cd94d42ea6d432405e33f3642f133448c595c93f3aff3624557b78f96e735f2a94bc59a3885714da70bdbe9a32ce37eed1f2f319