Merge remote-tracking branch 'up/master' into master-riscv64

Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>

firefox-60.2.2-add-riscv64.patch

@@ -0,0 +1,85 @@
+diff --git a/build/moz.configure/init.configure b/build/moz.configure/init.configure
+index 83b8d7055..200ea47e5 100644
+--- a/build/moz.configure/init.configure
++++ b/build/moz.configure/init.configure
+@@ -673,6 +673,9 @@ def split_triplet(triplet, allow_unknown=False):
+     elif cpu.startswith('aarch64'):
+         canonical_cpu = 'aarch64'
+         endianness = 'little'
++    elif cpu.startswith('riscv64'):
++        canonical_cpu = 'riscv64'
++        endianness = 'little'
+     elif cpu == 'sh4':
+         canonical_cpu = 'sh4'
+         endianness = 'little'
+diff --git a/js/src/jit/AtomicOperations.h b/js/src/jit/AtomicOperations.h
+index 3501e65b8..fda0b1487 100644
+--- a/js/src/jit/AtomicOperations.h
++++ b/js/src/jit/AtomicOperations.h
+@@ -393,6 +393,8 @@ inline bool AtomicOperations::isLockfreeJS(int32_t size) {
+ #include "jit/none/AtomicOperations-feeling-lucky.h"
+ #elif defined(__s390__) || defined(__s390x__)
+ #include "jit/none/AtomicOperations-feeling-lucky.h"
++#elif defined(__riscv)
++#include "jit/none/AtomicOperations-feeling-lucky.h"
+ #else
+ #error "No AtomicOperations support provided for this platform"
+ #endif
+diff --git a/js/src/jit/none/AtomicOperations-feeling-lucky.h b/js/src/jit/none/AtomicOperations-feeling-lucky.h
+index c0b436995..f0e2d7150 100644
+--- a/js/src/jit/none/AtomicOperations-feeling-lucky.h
++++ b/js/src/jit/none/AtomicOperations-feeling-lucky.h
+@@ -80,6 +80,14 @@
+ #define GNUC_COMPATIBLE
+ #endif
+ 
++#ifdef __riscv
++#  define GNUC_COMPATIBLE
++#  if __riscv_xlen == 64
++#    define HAS_64BIT_ATOMICS
++#    define HAS_64BIT_LOCKFREE
++#  endif
++#endif
++
+ // The default implementation tactic for gcc/clang is to use the newer
+ // __atomic intrinsics added for use in C++11 <atomic>.  Where that
+ // isn't available, we use GCC's older __sync functions instead.
+diff --git a/mfbt/tests/TestPoisonArea.cpp b/mfbt/tests/TestPoisonArea.cpp
+index 06c24ed03..708ea558e 100644
+--- a/mfbt/tests/TestPoisonArea.cpp
++++ b/mfbt/tests/TestPoisonArea.cpp
+@@ -160,6 +160,14 @@
+ #elif defined __aarch64__
+ #define RETURN_INSTR 0xd65f03c0 /* ret */
+ 
++#elif defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen == 64
++#if defined(__riscv_compressed)
++#define RETURN_INSTR 0x8082 /* ret */
++#define RETURN_INSTR_TYPE uint16_t
++#else
++#define RETURN_INSTR 0x00008067 /* ret */
++#endif
++
+ #elif defined __ia64
+ struct ia64_instr { uint32_t mI[4]; };
+ static const ia64_instr _return_instr =
+diff --git a/python/mozbuild/mozbuild/configure/constants.py b/python/mozbuild/mozbuild/configure/constants.py
+index 33ae5a456..3edb0d618 100644
+--- a/python/mozbuild/mozbuild/configure/constants.py
++++ b/python/mozbuild/mozbuild/configure/constants.py
+@@ -50,6 +50,7 @@ CPU_bitness = {
+     'mips64': 64,
+     'ppc': 32,
+     'ppc64': 64,
++    'riscv64': 64,
+     's390': 32,
+     's390x': 64,
+     'sh4': 32,
+@@ -89,6 +90,7 @@ CPU_preprocessor_checks = OrderedDict((
+     ('mips64', '__mips64'),
+     ('mips32', '__mips__'),
+     ('sh4', '__sh__'),
++    ('riscv64', 'defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen == 64'),
+ ))
+ 
+ assert sorted(CPU_preprocessor_checks.keys()) == sorted(CPU.POSSIBLE_VALUES)

mozjs60.spec

@@ -16,7 +16,7 @@
 
 Name:           mozjs%{major}
 Version:        60.9.0
-Release:        5%{?dist}
+Release:        5.0.riscv64%{?dist}
 Summary:        SpiderMonkey JavaScript library
 
 License:        MPLv2.0 and MPLv1.1 and BSD and GPLv2+ and GPLv3+ and LGPLv2+ and AFL and ASL 2.0
@@ -50,6 +50,9 @@ Patch18:        tests-Expect-a-test-to-fail-on-big-endian.patch
 # Patches from Fedora firefox package:
 Patch26:        build-icu-big-endian.patch
 
+# Add support for RISC-V (riscv64)
+Patch400:       firefox-60.2.2-add-riscv64.patch
+
 # aarch64 fixes for -O2
 Patch30:        Save-x28-before-clobbering-it-in-the-regex-compiler.patch
 Patch31:        Save-and-restore-non-volatile-x28-on-ARM64-for-generated-unboxed-object-constructor.patch
@@ -110,6 +113,9 @@ pushd ../..
 %patch26 -p1 -b .icu
 %endif
 
+# riscv
+%patch400 -p1
+
 # aarch64 -O2 fixes
 %ifarch aarch64
 %patch30 -p1
@@ -148,6 +154,9 @@ autoconf-2.13
   --disable-optimize \
   --enable-pie \
   --disable-jemalloc \
+%ifarch riscv64
+  --disable-ion
+%endif
 
 %if 0%{?big_endian}
 echo "Generate big endian version of config/external/icu/data/icud58l.dat"
@@ -243,6 +252,9 @@ ln -s libmozjs-%{major}.so.0 %{buildroot}%{_libdir}/libmozjs-%{major}.so
 %{_includedir}/mozjs-%{major}/
 
 %changelog
+* Sat Apr 11 2020 David Abdurachmanov <david.abdurachmanov@sifive.com> - 60.9.0-5.0.riscv64
+- Add support for RISC-V (riscv64)
+
 * Mon Feb 17 2020 Kalev Lember <klember@redhat.com> - 60.9.0-5
 - Update enddianness.patch with more s390x fixes
 - Enable tests on s390x again