119 lines
4.1 KiB
Diff
119 lines
4.1 KiB
Diff
From 5ac4f80be3e8b5d42475aeaba246455e0016c7ef Mon Sep 17 00:00:00 2001
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From: Anthony Ramine <n.oxyde@gmail.com>
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Date: Sun, 27 Nov 2016 16:28:12 +0100
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Subject: [rust-lang/llvm#57] Backport rL277331
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---
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lib/Target/AArch64/AArch64InstrInfo.cpp | 3 +
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.../MIR/AArch64/inst-size-tlsdesc-callseq.mir | 84 ++++++++++++++++++++++
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2 files changed, 87 insertions(+)
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create mode 100644 test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir
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diff --git a/lib/Target/AArch64/AArch64InstrInfo.cpp b/lib/Target/AArch64/AArch64InstrInfo.cpp
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index 0aa4708f35ac..d39542a8e4eb 100644
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--- a/lib/Target/AArch64/AArch64InstrInfo.cpp
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+++ b/lib/Target/AArch64/AArch64InstrInfo.cpp
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@@ -56,6 +56,9 @@ unsigned AArch64InstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const {
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case TargetOpcode::IMPLICIT_DEF:
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case TargetOpcode::KILL:
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return 0;
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+ case AArch64::TLSDESC_CALLSEQ:
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+ // This gets lowered to an instruction sequence which takes 16 bytes
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+ return 16;
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}
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llvm_unreachable("GetInstSizeInBytes()- Unable to determin insn size");
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diff --git a/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir b/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir
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new file mode 100644
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index 000000000000..2d966ece768e
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--- /dev/null
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+++ b/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir
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@@ -0,0 +1,84 @@
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+# RUN: llc -mtriple=aarch64-unknown -run-pass aarch64-branch-relax -aarch64-tbz-offset-bits=4 %s -o - | FileCheck %s
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+--- |
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+ ; ModuleID = 'test.ll'
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+ source_filename = "test.ll"
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+ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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+ target triple = "aarch64-unknown"
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+
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+ @ThreadLocalGlobal = external thread_local local_unnamed_addr global i32, align 8
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+
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+ define i32 @test_tlsdesc_callseq_length(i32 %in) {
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+ %val = and i32 %in, 1
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+ %tst = icmp eq i32 %val, 0
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+ br i1 %tst, label %true, label %false
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+
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+ true: ; preds = %0
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+ %1 = load i32, i32* @ThreadLocalGlobal, align 8
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+ ret i32 %1
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+
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+ false: ; preds = %0
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+ ret i32 0
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+ }
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+
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+...
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+---
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+# CHECK-LABEL: name:{{.*}}test_tlsdesc_callseq_length
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+# If the size of TLSDESC_CALLSEQ is computed correctly, that will push
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+# the bb.2.false block too far away from the TBNZW, so the branch will
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+# have to be relaxed (note that we're using -aarch64-tbz-offset-bits to
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+# constrain the range that can be reached with the TBNZW to something smaller
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+# than what TLSDESC_CALLSEQ is lowered to).
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+# CHECK: TBZW killed %w0, 0, %bb.1.true
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+# CHECK: B %bb.2.false
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+name: test_tlsdesc_callseq_length
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+alignment: 2
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+exposesReturnsTwice: false
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+hasInlineAsm: false
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+allVRegsAllocated: true
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+isSSA: false
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+tracksRegLiveness: false
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+tracksSubRegLiveness: false
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+liveins:
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+ - { reg: '%w0' }
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+frameInfo:
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+ isFrameAddressTaken: false
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+ isReturnAddressTaken: false
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+ hasStackMap: false
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+ hasPatchPoint: false
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+ stackSize: 16
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+ offsetAdjustment: 0
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+ maxAlignment: 16
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+ adjustsStack: false
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+ hasCalls: true
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+ maxCallFrameSize: 0
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+ hasOpaqueSPAdjustment: false
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+ hasVAStart: false
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+ hasMustTailInVarArgFunc: false
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+stack:
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+ - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%lr' }
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+body: |
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+ bb.0 (%ir-block.0):
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+ successors: %bb.1.true, %bb.2.false
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+ liveins: %w0, %lr
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+
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+ TBNZW killed %w0, 0, %bb.2.false
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+
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+ bb.1.true:
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+ liveins: %lr
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+
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+ early-clobber %sp = frame-setup STRXpre killed %lr, %sp, -16 :: (store 8 into %stack.0)
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+ frame-setup CFI_INSTRUCTION def_cfa_offset 16
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+ frame-setup CFI_INSTRUCTION offset %w30, -16
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+ TLSDESC_CALLSEQ target-flags(aarch64-tls) @ThreadLocalGlobal, implicit-def dead %lr, implicit-def %x0, implicit-def dead %x1
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+ %x8 = MRS 56962
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+ %w0 = LDRWroX killed %x8, killed %x0, 0, 0 :: (load 4 from @ThreadLocalGlobal, align 8)
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+ early-clobber %sp, %lr = LDRXpost %sp, 16 :: (load 8 from %stack.0)
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+ RET killed %lr, implicit killed %w0
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+
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+ bb.2.false:
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+ liveins: %lr
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+
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+ %w0 = ORRWrs %wzr, %wzr, 0
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+ RET killed %lr, implicit killed %w0
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+
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+...
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--
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2.9.3
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