129 lines
4.8 KiB
Diff
129 lines
4.8 KiB
Diff
Index: lib/Target/ARM/ARMFrameLowering.cpp
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===================================================================
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--- lib/Target/ARM/ARMFrameLowering.cpp (revision 159085)
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+++ lib/Target/ARM/ARMFrameLowering.cpp (working copy)
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@@ -15,6 +15,8 @@
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#include "ARMBaseInstrInfo.h"
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#include "ARMBaseRegisterInfo.h"
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#include "ARMMachineFunctionInfo.h"
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+#include "llvm/CallingConv.h"
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+#include "llvm/Function.h"
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#include "MCTargetDesc/ARMAddressingModes.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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@@ -151,6 +153,10 @@
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int FramePtrSpillFI = 0;
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int D8SpillFI = 0;
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+ // All calls are tail calls in GHC calling conv, and functions have no prologue/epilogue.
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+ if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
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+ return;
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+
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// Allocate the vararg register save area. This is not counted in NumBytes.
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if (VARegSaveSize)
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize,
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@@ -354,6 +360,10 @@
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int NumBytes = (int)MFI->getStackSize();
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unsigned FramePtr = RegInfo->getFrameRegister(MF);
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+ // All calls are tail calls in GHC calling conv, and functions have no prologue/epilogue.
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+ if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
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+ return;
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+
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if (!AFI->hasStackFrame()) {
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if (NumBytes != 0)
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
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Index: lib/Target/ARM/ARMISelLowering.cpp
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===================================================================
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--- lib/Target/ARM/ARMISelLowering.cpp (revision 159085)
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+++ lib/Target/ARM/ARMISelLowering.cpp (working copy)
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@@ -1171,6 +1171,8 @@
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return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
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case CallingConv::ARM_APCS:
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return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
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+ case CallingConv::GHC:
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+ return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
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}
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}
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Index: lib/Target/ARM/ARMCallingConv.td
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===================================================================
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--- lib/Target/ARM/ARMCallingConv.td (revision 159085)
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+++ lib/Target/ARM/ARMCallingConv.td (working copy)
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@@ -79,7 +79,26 @@
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CCDelegateTo<RetCC_ARM_APCS>
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]>;
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+//===----------------------------------------------------------------------===//
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+// ARM APCS Calling Convention for GHC
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+//===----------------------------------------------------------------------===//
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+def CC_ARM_APCS_GHC : CallingConv<[
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+ // Handle all vector types as either f64 or v2f64.
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+ CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
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+ CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
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+
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+ CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>,
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+ CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>,
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+ CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>,
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+
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+ // Promote i8/i16 arguments to i32.
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+ CCIfType<[i8, i16], CCPromoteToType<i32>>,
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+
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+ // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim
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+ CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
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+]>;
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+
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//===----------------------------------------------------------------------===//
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// ARM AAPCS (EABI) Calling Convention, common parts
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//===----------------------------------------------------------------------===//
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@@ -171,3 +190,9 @@
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// iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved register.
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// Also save R7-R4 first to match the stack frame fixed spill areas.
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def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
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+
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+// GHC set of callee saved regs is empty as all those regs are
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+// used for passing STG regs around
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+// sub/add LR is a workaround for not being able to compile empty list:
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+// def CSR_GHC : CalleeSavedRegs<()>;
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+def CSR_GHC : CalleeSavedRegs<(sub (add LR), LR)>;
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Index: lib/Target/ARM/ARMFastISel.cpp
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===================================================================
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--- lib/Target/ARM/ARMFastISel.cpp (revision 159085)
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+++ lib/Target/ARM/ARMFastISel.cpp (working copy)
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@@ -1835,6 +1835,11 @@
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return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
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case CallingConv::ARM_APCS:
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return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
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+ case CallingConv::GHC:
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+ if (Return)
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+ llvm_unreachable("Can't return in GHC call convention");
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+ else
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+ return CC_ARM_APCS_GHC;
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}
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}
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--- lib/Target/ARM/ARMBaseRegisterInfo.cpp.orig 2012-07-12 09:59:58.181723592 +0100
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+++ lib/Target/ARM/ARMBaseRegisterInfo.cpp 2012-07-12 10:01:15.301344412 +0100
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@@ -62,7 +62,19 @@
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const uint16_t*
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ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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- return (STI.isTargetIOS()) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList;
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+ bool ghcCall = false;
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+
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+ if (MF) {
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+ const Function *F = MF->getFunction();
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+ ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
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+ }
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+
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+ if (ghcCall) {
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+ return CSR_GHC_SaveList;
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+ }
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+ else {
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+ return (STI.isTargetIOS()) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList;
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+ }
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}
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const uint32_t*
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