78 lines
2.9 KiB
Diff
78 lines
2.9 KiB
Diff
From 66e43b0a8e5616a4762eedee9bd030a49b9d6545 Mon Sep 17 00:00:00 2001
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From: Guozhi Wei <carrot@google.com>
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Date: Thu, 2 Mar 2017 21:07:59 +0000
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Subject: [PATCH 1/3] [PPC] Fix code generation for bswap(int32) followed by
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store16
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This patch fixes pr32063.
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Current code in PPCTargetLowering::PerformDAGCombine can transform
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bswap
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store
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into a single PPCISD::STBRX instruction. but it doesn't consider the case that the operand size of bswap may be larger than store size. When it occurs, we need 2 modifications,
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1 For the last operand of PPCISD::STBRX, we should not use DAG.getValueType(N->getOperand(1).getValueType()), instead we should use cast<StoreSDNode>(N)->getMemoryVT().
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2 Before PPCISD::STBRX, we need to shift the original operand of bswap to the right side.
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Differential Revision: https://reviews.llvm.org/D30362
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296811 91177308-0d34-0410-b5e6-96231b3b80d8
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---
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lib/Target/PowerPC/PPCISelLowering.cpp | 12 ++++++++++--
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test/CodeGen/PowerPC/pr32063.ll | 16 ++++++++++++++++
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2 files changed, 26 insertions(+), 2 deletions(-)
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create mode 100644 test/CodeGen/PowerPC/pr32063.ll
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diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
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index 6313082..c8eb6f1 100644
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--- a/lib/Target/PowerPC/PPCISelLowering.cpp
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+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
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@@ -11226,9 +11226,17 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
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if (BSwapOp.getValueType() == MVT::i16)
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BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
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+ // If the type of BSWAP operand is wider than stored memory width
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+ // it need to be shifted to the right side before STBRX.
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+ EVT mVT = cast<StoreSDNode>(N)->getMemoryVT();
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+ if (Op1VT.bitsGT(mVT)) {
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+ int shift = Op1VT.getSizeInBits() - mVT.getSizeInBits();
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+ BSwapOp = DAG.getNode(ISD::SRL, dl, Op1VT, BSwapOp,
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+ DAG.getConstant(shift, dl, MVT::i32));
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+ }
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+
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SDValue Ops[] = {
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- N->getOperand(0), BSwapOp, N->getOperand(2),
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- DAG.getValueType(N->getOperand(1).getValueType())
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+ N->getOperand(0), BSwapOp, N->getOperand(2), DAG.getValueType(mVT)
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};
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return
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DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
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diff --git a/test/CodeGen/PowerPC/pr32063.ll b/test/CodeGen/PowerPC/pr32063.ll
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new file mode 100644
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index 0000000..f031ec8
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--- /dev/null
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+++ b/test/CodeGen/PowerPC/pr32063.ll
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@@ -0,0 +1,16 @@
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+; RUN: llc -O2 < %s | FileCheck %s
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+target triple = "powerpc64le-linux-gnu"
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+
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+define void @foo(i32 %v, i16* %p) {
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+ %1 = and i32 %v, -65536
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+ %2 = tail call i32 @llvm.bswap.i32(i32 %1)
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+ %conv = trunc i32 %2 to i16
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+ store i16 %conv, i16* %p
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+ ret void
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+
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+; CHECK: srwi
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+; CHECK: sthbrx
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+; CHECK-NOT: stwbrx
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+}
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+
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+declare i32 @llvm.bswap.i32(i32)
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--
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1.8.3.1
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