Backport r291084 (rhbz1435545)

Fix %postun step for -devel package (rhbz 1403539)
Fix computeKnownBits for ARMISD::CMOV (rust-lang/llvm#67 )
2017-08-25 18:57:25 +00:00 · 2017-08-25 13:42:30 +00:00 · 2017-04-18 15:03:45 -07:00 · 2017-03-17 20:05:54 +00:00 · 2017-03-01 15:46:03 +10:00 · 2017-01-06 17:56:22 -08:00
43 changed files with 4508 additions and 1087 deletions
--- a/.gitignore
+++ b/.gitignore
@ -30,41 +30,3 @@
 /llvm-3.8.1.src.tar.xz
 /llvm-3.9.0.src.tar.xz
 /llvm-3.9.1.src.tar.xz
-/llvm-4.0.0.src.tar.xz
-/llvm-4.0.1.src.tar.xz
-/llvm-5.0.0.src.tar.xz
-/llvm-5.0.1.src.tar.xz
-/llvm-6.0.0rc1.src.tar.xz
-/llvm-6.0.0rc2.src.tar.xz
-/llvm-6.0.0.src.tar.xz
-/llvm-6.0.1rc1.src.tar.xz
-/llvm-6.0.1rc2.src.tar.xz
-/llvm-6.0.1.src.tar.xz
-/llvm-7.0.0rc1.src.tar.xz
-/llvm-7.0.0rc2.src.tar.xz
-/llvm-7.0.0rc3.src.tar.xz
-/llvm-7.0.0.src.tar.xz
-/llvm-7.0.1.src.tar.xz
-/llvm-8.0.0rc1.src.tar.xz
-/llvm-8.0.0rc2.src.tar.xz
-/llvm-8.0.0rc3.src.tar.xz
-/llvm-8.0.0rc4.src.tar.xz
-/llvm-8.0.0.src.tar.xz
-/llvm-9.0.0rc2.src.tar.xz
-/llvm-9.0.0rc3.src.tar.xz
-/llvm-9.0.0.src.tar.xz
-/llvm-9.0.1.src.tar.xz
-/llvm-10.0.0rc1.src.tar.xz
-/llvm-10.0.0rc1.src.tar.xz.sig
-/llvm-10.0.0rc2.src.tar.xz
-/llvm-10.0.0rc2.src.tar.xz.sig
-/llvm-10.0.0rc3.src.tar.xz
-/llvm-10.0.0rc3.src.tar.xz.sig
-/llvm-10.0.0rc4.src.tar.xz
-/llvm-10.0.0rc4.src.tar.xz.sig
-/llvm-10.0.0rc5.src.tar.xz
-/llvm-10.0.0rc5.src.tar.xz.sig
-/llvm-10.0.0rc6.src.tar.xz
-/llvm-10.0.0rc6.src.tar.xz.sig
-/llvm-10.0.0.src.tar.xz
-/llvm-10.0.0.src.tar.xz.sig
--- a/0001-CMake-Split-static-library-exports-into-their-own-ex.patch
+++ b/0001-CMake-Split-static-library-exports-into-their-own-ex.patch
@ -1,66 +0,0 @@
-From 8f6917ea11bd1bfbfe07f3577756d1c4abfdb916 Mon Sep 17 00:00:00 2001
-From: Tom Stellard <tstellar@redhat.com>
-Date: Fri, 6 Sep 2019 11:03:18 -0700
-Subject: [PATCH] CMake: Split static library exports into their own export
- file
-
---
- llvm/cmake/modules/AddLLVM.cmake       | 6 +++++-
- llvm/cmake/modules/CMakeLists.txt      | 3 +++
- llvm/cmake/modules/LLVMConfig.cmake.in | 2 ++
- 3 files changed, 10 insertions(+), 1 deletion(-)
-
-diff --git a/llvm/cmake/modules/AddLLVM.cmake b/llvm/cmake/modules/AddLLVM.cmake
-index 619e986..200fc45 100644
--- a/llvm/cmake/modules/AddLLVM.cmake
-+++ b/llvm/cmake/modules/AddLLVM.cmake
-@@ -691,7 +691,11 @@ macro(add_llvm_library name)
-       if(${name} IN_LIST LLVM_DISTRIBUTION_COMPONENTS OR
-           (in_llvm_libs AND "llvm-libraries" IN_LIST LLVM_DISTRIBUTION_COMPONENTS) OR
-           NOT LLVM_DISTRIBUTION_COMPONENTS)
-        set(export_to_llvmexports EXPORT LLVMExports)
-+        if (ARG_SHARED)
-+          set(export_to_llvmexports EXPORT LLVMExports)
-+        else()
-+          set(export_to_llvmexports EXPORT LLVMStaticExports)
-+        endif()
-         set_property(GLOBAL PROPERTY LLVM_HAS_EXPORTS True)
-       endif()
- 
-diff --git a/llvm/cmake/modules/CMakeLists.txt b/llvm/cmake/modules/CMakeLists.txt
-index 9cf22b4..dc982d2 100644
--- a/llvm/cmake/modules/CMakeLists.txt
-+++ b/llvm/cmake/modules/CMakeLists.txt
-@@ -105,6 +105,7 @@ set(LLVM_CONFIG_BINARY_DIR "\${LLVM_INSTALL_PREFIX}")
- set(LLVM_CONFIG_TOOLS_BINARY_DIR "\${LLVM_INSTALL_PREFIX}/bin")
- set(LLVM_CONFIG_EXPORTS_FILE "\${LLVM_CMAKE_DIR}/LLVMExports.cmake")
- set(LLVM_CONFIG_EXPORTS "${LLVM_EXPORTS}")
-+set(LLVM_CONFIG_STATIC_EXPORTS_FILE "\${LLVM_CMAKE_DIR}/LLVMStaticExports.cmake")
- configure_file(
-   LLVMConfig.cmake.in
-   ${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/LLVMConfig.cmake
-@@ -121,6 +122,8 @@ if (NOT LLVM_INSTALL_TOOLCHAIN_ONLY)
-   if(llvm_has_exports)
-     install(EXPORT LLVMExports DESTINATION ${LLVM_INSTALL_PACKAGE_DIR}
-             COMPONENT cmake-exports)
-+    install(EXPORT LLVMStaticExports DESTINATION ${LLVM_INSTALL_PACKAGE_DIR}
-+            COMPONENT cmake-exports)
-   endif()
- 
-   install(FILES
-diff --git a/llvm/cmake/modules/LLVMConfig.cmake.in b/llvm/cmake/modules/LLVMConfig.cmake.in
-index 536031f..6ef54a0 100644
--- a/llvm/cmake/modules/LLVMConfig.cmake.in
-+++ b/llvm/cmake/modules/LLVMConfig.cmake.in
-@@ -89,6 +89,8 @@ if(NOT TARGET LLVMSupport)
-   set(LLVM_EXPORTED_TARGETS "@LLVM_CONFIG_EXPORTS@")
-   include("@LLVM_CONFIG_EXPORTS_FILE@")
-   @llvm_config_include_buildtree_only_exports@
-+
-+  include("@LLVM_CONFIG_STATIC_EXPORTS_FILE@" OPTIONAL)
- endif()
- 
- # By creating intrinsics_gen here, subprojects that depend on LLVM's
-- 
-1.8.3.1
-
--- a/0001-CMake-Split-test-binary-exports-into-their-own-expor.patch
+++ b/0001-CMake-Split-test-binary-exports-into-their-own-expor.patch
@ -1,65 +0,0 @@
-From 9d496e978f59e153bb76e92229d5a524d92dee04 Mon Sep 17 00:00:00 2001
-From: Tom Stellard <tstellar@redhat.com>
-Date: Tue, 10 Sep 2019 13:33:48 -0700
-Subject: [PATCH] CMake: Split test binary exports into their own export file
-
---
- llvm/cmake/modules/AddLLVM.cmake       | 7 ++++++-
- llvm/cmake/modules/CMakeLists.txt      | 3 +++
- llvm/cmake/modules/LLVMConfig.cmake.in | 1 +
- 3 files changed, 10 insertions(+), 1 deletion(-)
-
-diff --git a/llvm/cmake/modules/AddLLVM.cmake b/llvm/cmake/modules/AddLLVM.cmake
-index 200fc45..9eec7a7 100644
--- a/llvm/cmake/modules/AddLLVM.cmake
-+++ b/llvm/cmake/modules/AddLLVM.cmake
-@@ -953,7 +953,12 @@ macro(add_llvm_utility name)
-       set(export_to_llvmexports)
-       if (${name} IN_LIST LLVM_DISTRIBUTION_COMPONENTS OR
-           NOT LLVM_DISTRIBUTION_COMPONENTS)
-        set(export_to_llvmexports EXPORT LLVMExports)
-+        if (${name} STREQUAL "not" OR ${name} STREQUAL "count" OR
-+            ${name} STREQUAL "yaml-bench" OR ${name} STREQUAL "lli-child-target")
-+          set(export_to_llvmexports EXPORT LLVMTestExports)
-+        else()
-+          set(export_to_llvmexports EXPORT LLVMExports)
-+        endif()
-         set_property(GLOBAL PROPERTY LLVM_HAS_EXPORTS True)
-       endif()
- 
-diff --git a/llvm/cmake/modules/CMakeLists.txt b/llvm/cmake/modules/CMakeLists.txt
-index dc982d2..c861f45 100644
--- a/llvm/cmake/modules/CMakeLists.txt
-+++ b/llvm/cmake/modules/CMakeLists.txt
-@@ -106,6 +106,7 @@ set(LLVM_CONFIG_TOOLS_BINARY_DIR "\${LLVM_INSTALL_PREFIX}/bin")
- set(LLVM_CONFIG_EXPORTS_FILE "\${LLVM_CMAKE_DIR}/LLVMExports.cmake")
- set(LLVM_CONFIG_EXPORTS "${LLVM_EXPORTS}")
- set(LLVM_CONFIG_STATIC_EXPORTS_FILE "\${LLVM_CMAKE_DIR}/LLVMStaticExports.cmake")
-+set(LLVM_CONFIG_TEST_EXPORTS_FILE "\${LLVM_CMAKE_DIR}/LLVMTestExports.cmake")
- configure_file(
-   LLVMConfig.cmake.in
-   ${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/LLVMConfig.cmake
-@@ -124,6 +125,8 @@ if (NOT LLVM_INSTALL_TOOLCHAIN_ONLY)
-             COMPONENT cmake-exports)
-     install(EXPORT LLVMStaticExports DESTINATION ${LLVM_INSTALL_PACKAGE_DIR}
-             COMPONENT cmake-exports)
-+    install(EXPORT LLVMTestExports DESTINATION ${LLVM_INSTALL_PACKAGE_DIR}
-+            COMPONENT cmake-exports)
-   endif()
- 
-   install(FILES
-diff --git a/llvm/cmake/modules/LLVMConfig.cmake.in b/llvm/cmake/modules/LLVMConfig.cmake.in
-index 6ef54a0..d81b09a 100644
--- a/llvm/cmake/modules/LLVMConfig.cmake.in
-+++ b/llvm/cmake/modules/LLVMConfig.cmake.in
-@@ -91,6 +91,7 @@ if(NOT TARGET LLVMSupport)
-   @llvm_config_include_buildtree_only_exports@
- 
-   include("@LLVM_CONFIG_STATIC_EXPORTS_FILE@" OPTIONAL)
-+  include("@LLVM_CONFIG_TEST_EXPORTS_FILE@" OPTIONAL)
- endif()
- 
- # By creating intrinsics_gen here, subprojects that depend on LLVM's
-- 
-1.8.3.1
-
--- a/0001-Fix-R_AARCH64_MOVW_UABS_G3-relocation.patch
+++ b/0001-Fix-R_AARCH64_MOVW_UABS_G3-relocation.patch
@ -0,0 +1,435 @@
+From 29cf3bd00fe84ddab138c9311fe288bb9da8a273 Mon Sep 17 00:00:00 2001
+From: root <root@mammon-seattle-raw.austin.arm.com>
+Date: Thu, 9 Mar 2017 12:22:48 -0600
+Subject: [PATCH] Fix R_AARCH64_MOVW_UABS_G3 relocation
+
+Summary: The relocation is missing mask so an address that
+has non-zero bits in 47:43 may overwrite the register
+number. (Frequently shows up as target register changed
+to xzr....)
+
+Reviewers: t.p.northover, lhames
+Subscribers: davide, aemerson, rengolin, llvm-commits
+Differential Revision: https://reviews.llvm.org/D27609
+---
+ llvm-3.9.1.src/include/llvm/Object/ELFObjectFile.h |   2 +-
+ llvm-3.9.1.src/include/llvm/Object/RelocVisitor.h  |   1 +
+ .../ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp |  67 +++++++++-----
+ .../RuntimeDyld/AArch64/ELF_ARM64_BE-relocations.s | 102 +++++++++++++++++++++
+ .../RuntimeDyld/AArch64/ELF_ARM64_relocations.s    |  99 ++++++++++++++++++++
+ 5 files changed, 249 insertions(+), 22 deletions(-)
+ create mode 100644 llvm-3.9.1.src/test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_BE-relocations.s
+ create mode 100644 llvm-3.9.1.src/test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_relocations.s
+
+diff --git a/llvm-3.9.1.src/include/llvm/Object/ELFObjectFile.h b/llvm-3.9.1.src/include/llvm/Object/ELFObjectFile.h
+index 07c6364..d3b83f9 100644
+--- a/llvm-3.9.1.src/include/llvm/Object/ELFObjectFile.h
+++ b/llvm-3.9.1.src/include/llvm/Object/ELFObjectFile.h
+@@ -907,7 +907,7 @@ unsigned ELFObjectFile<ELFT>::getArch() const {
+   case ELF::EM_X86_64:
+     return Triple::x86_64;
+   case ELF::EM_AARCH64:
+-    return Triple::aarch64;
+    return IsLittleEndian ? Triple::aarch64 : Triple::aarch64_be;
+   case ELF::EM_ARM:
+     return Triple::arm;
+   case ELF::EM_AVR:
+diff --git a/llvm-3.9.1.src/include/llvm/Object/RelocVisitor.h b/llvm-3.9.1.src/include/llvm/Object/RelocVisitor.h
+index 5e0df98..b59e8ec 100644
+--- a/llvm-3.9.1.src/include/llvm/Object/RelocVisitor.h
+++ b/llvm-3.9.1.src/include/llvm/Object/RelocVisitor.h
+@@ -86,6 +86,7 @@ private:
+           return RelocToApply();
+         }
+       case Triple::aarch64:
+      case Triple::aarch64_be:
+         switch (RelocType) {
+         case llvm::ELF::R_AARCH64_ABS32:
+           return visitELF_AARCH64_ABS32(R, Value);
+diff --git a/llvm-3.9.1.src/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp b/llvm-3.9.1.src/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
+index 9cbdb13..9e04b5d 100644
+--- a/llvm-3.9.1.src/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
+++ b/llvm-3.9.1.src/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
+@@ -309,6 +309,8 @@ void RuntimeDyldELF::resolveAArch64Relocation(const SectionEntry &Section,
+   uint32_t *TargetPtr =
+       reinterpret_cast<uint32_t *>(Section.getAddressWithOffset(Offset));
+   uint64_t FinalAddress = Section.getLoadAddressWithOffset(Offset);
+  // Data should use target endian. Code should always use little endian.
+  bool isBE = Arch == Triple::aarch64_be;
+ 
+   DEBUG(dbgs() << "resolveAArch64Relocation, LocalAddress: 0x"
+                << format("%llx", Section.getAddressWithOffset(Offset))
+@@ -324,14 +326,22 @@ void RuntimeDyldELF::resolveAArch64Relocation(const SectionEntry &Section,
+   case ELF::R_AARCH64_ABS64: {
+     uint64_t *TargetPtr =
+         reinterpret_cast<uint64_t *>(Section.getAddressWithOffset(Offset));
+-    *TargetPtr = Value + Addend;
+    if (isBE)
+      support::ubig64_t::ref{TargetPtr} = Value + Addend;
+    else
+      support::ulittle64_t::ref{TargetPtr} = Value + Addend;
+     break;
+   }
+   case ELF::R_AARCH64_PREL32: {
+     uint64_t Result = Value + Addend - FinalAddress;
+     assert(static_cast<int64_t>(Result) >= INT32_MIN &&
+            static_cast<int64_t>(Result) <= UINT32_MAX);
+-    *TargetPtr = static_cast<uint32_t>(Result & 0xffffffffU);
+    if (isBE)
+      support::ubig32_t::ref{TargetPtr} =
+        static_cast<uint32_t>(Result & 0xffffffffU);
+    else
+      support::ulittle32_t::ref{TargetPtr} =
+        static_cast<uint32_t>(Result & 0xffffffffU);
+     break;
+   }
+   case ELF::R_AARCH64_CALL26: // fallthrough
+@@ -339,6 +349,7 @@ void RuntimeDyldELF::resolveAArch64Relocation(const SectionEntry &Section,
+     // Operation: S+A-P. Set Call or B immediate value to bits fff_fffc of the
+     // calculation.
+     uint64_t BranchImm = Value + Addend - FinalAddress;
+    uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
+ 
+     // "Check that -2^27 <= result < 2^27".
+     assert(isInt<28>(BranchImm));
+@@ -352,91 +363,105 @@ void RuntimeDyldELF::resolveAArch64Relocation(const SectionEntry &Section,
+   }
+   case ELF::R_AARCH64_MOVW_UABS_G3: {
+     uint64_t Result = Value + Addend;
+    uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
+ 
+     // AArch64 code is emitted with .rela relocations. The data already in any
+     // bits affected by the relocation on entry is garbage.
+-    *TargetPtr &= 0xffe0001fU;
+    TargetValue &= 0xffe0001fU;
+     // Immediate goes in bits 20:5 of MOVZ/MOVK instruction
+-    *TargetPtr |= Result >> (48 - 5);
+    TargetValue |= ((Result & 0xffff000000000000ULL) >> (48 - 5));
+     // Shift must be "lsl #48", in bits 22:21
+-    assert((*TargetPtr >> 21 & 0x3) == 3 && "invalid shift for relocation");
+    assert((TargetValue >> 21 & 0x3) == 3 && "invalid shift for relocation");
+    support::ulittle32_t::ref{TargetPtr} = TargetValue;
+     break;
+   }
+   case ELF::R_AARCH64_MOVW_UABS_G2_NC: {
+     uint64_t Result = Value + Addend;
+    uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
+ 
+     // AArch64 code is emitted with .rela relocations. The data already in any
+     // bits affected by the relocation on entry is garbage.
+-    *TargetPtr &= 0xffe0001fU;
+    TargetValue &= 0xffe0001fU;
+     // Immediate goes in bits 20:5 of MOVZ/MOVK instruction
+-    *TargetPtr |= ((Result & 0xffff00000000ULL) >> (32 - 5));
+    TargetValue |= ((Result & 0xffff00000000ULL) >> (32 - 5));
+     // Shift must be "lsl #32", in bits 22:21
+-    assert((*TargetPtr >> 21 & 0x3) == 2 && "invalid shift for relocation");
+    assert((TargetValue >> 21 & 0x3) == 2 && "invalid shift for relocation");
+    support::ulittle32_t::ref{TargetPtr} = TargetValue;
+     break;
+   }
+   case ELF::R_AARCH64_MOVW_UABS_G1_NC: {
+     uint64_t Result = Value + Addend;
+    uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
+ 
+     // AArch64 code is emitted with .rela relocations. The data already in any
+     // bits affected by the relocation on entry is garbage.
+-    *TargetPtr &= 0xffe0001fU;
+    TargetValue &= 0xffe0001fU;
+     // Immediate goes in bits 20:5 of MOVZ/MOVK instruction
+-    *TargetPtr |= ((Result & 0xffff0000U) >> (16 - 5));
+    TargetValue |= ((Result & 0xffff0000U) >> (16 - 5));
+     // Shift must be "lsl #16", in bits 22:2
+-    assert((*TargetPtr >> 21 & 0x3) == 1 && "invalid shift for relocation");
+    assert((TargetValue >> 21 & 0x3) == 1 && "invalid shift for relocation");
+    support::ulittle32_t::ref{TargetPtr} = TargetValue;
+     break;
+   }
+   case ELF::R_AARCH64_MOVW_UABS_G0_NC: {
+     uint64_t Result = Value + Addend;
+    uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
+ 
+     // AArch64 code is emitted with .rela relocations. The data already in any
+     // bits affected by the relocation on entry is garbage.
+-    *TargetPtr &= 0xffe0001fU;
+    TargetValue &= 0xffe0001fU;
+     // Immediate goes in bits 20:5 of MOVZ/MOVK instruction
+-    *TargetPtr |= ((Result & 0xffffU) << 5);
+    TargetValue |= ((Result & 0xffffU) << 5);
+     // Shift must be "lsl #0", in bits 22:21.
+-    assert((*TargetPtr >> 21 & 0x3) == 0 && "invalid shift for relocation");
+    assert((TargetValue >> 21 & 0x3) == 0 && "invalid shift for relocation");
+    support::ulittle32_t::ref{TargetPtr} = TargetValue;
+     break;
+   }
+   case ELF::R_AARCH64_ADR_PREL_PG_HI21: {
+     // Operation: Page(S+A) - Page(P)
+     uint64_t Result =
+         ((Value + Addend) & ~0xfffULL) - (FinalAddress & ~0xfffULL);
+    uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
+ 
+     // Check that -2^32 <= X < 2^32
+     assert(isInt<33>(Result) && "overflow check failed for relocation");
+ 
+     // AArch64 code is emitted with .rela relocations. The data already in any
+     // bits affected by the relocation on entry is garbage.
+-    *TargetPtr &= 0x9f00001fU;
+    TargetValue &= 0x9f00001fU;
+     // Immediate goes in bits 30:29 + 5:23 of ADRP instruction, taken
+     // from bits 32:12 of X.
+-    *TargetPtr |= ((Result & 0x3000U) << (29 - 12));
+-    *TargetPtr |= ((Result & 0x1ffffc000ULL) >> (14 - 5));
+    TargetValue |= ((Result & 0x3000U) << (29 - 12));
+    TargetValue |= ((Result & 0x1ffffc000ULL) >> (14 - 5));
+    support::ulittle32_t::ref{TargetPtr} = TargetValue;
+     break;
+   }
+   case ELF::R_AARCH64_LDST32_ABS_LO12_NC: {
+     // Operation: S + A
+     uint64_t Result = Value + Addend;
+    uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
+ 
+     // AArch64 code is emitted with .rela relocations. The data already in any
+     // bits affected by the relocation on entry is garbage.
+-    *TargetPtr &= 0xffc003ffU;
+    TargetValue &= 0xffc003ffU;
+     // Immediate goes in bits 21:10 of LD/ST instruction, taken
+     // from bits 11:2 of X
+-    *TargetPtr |= ((Result & 0xffc) << (10 - 2));
+    TargetValue |= ((Result & 0xffc) << (10 - 2));
+    support::ulittle32_t::ref{TargetPtr} = TargetValue;
+     break;
+   }
+   case ELF::R_AARCH64_LDST64_ABS_LO12_NC: {
+     // Operation: S + A
+     uint64_t Result = Value + Addend;
+    uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
+ 
+     // AArch64 code is emitted with .rela relocations. The data already in any
+     // bits affected by the relocation on entry is garbage.
+-    *TargetPtr &= 0xffc003ffU;
+    TargetValue &= 0xffc003ffU;
+     // Immediate goes in bits 21:10 of LD/ST instruction, taken
+     // from bits 11:3 of X
+-    *TargetPtr |= ((Result & 0xff8) << (10 - 3));
+    TargetValue |= ((Result & 0xff8) << (10 - 3));
+    support::ulittle32_t::ref{TargetPtr} = TargetValue;
+     break;
+   }
+   }
+diff --git a/llvm-3.9.1.src/test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_BE-relocations.s b/llvm-3.9.1.src/test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_BE-relocations.s
+new file mode 100644
+index 0000000..01d01e5
+--- /dev/null
+++ b/llvm-3.9.1.src/test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_BE-relocations.s
+@@ -0,0 +1,102 @@
+# RUN: llvm-mc -triple=aarch64_be-none-linux-gnu -filetype=obj -o %T/be-reloc.o %s
+# RUN: llvm-rtdyld -triple=aarch64_be-none-linux-gnu -verify -dummy-extern f=0x0123456789abcdef -check=%s %T/be-reloc.o
+
+        .text
+        .globl  g
+        .p2align        2
+        .type   g,@function
+g:
+# R_AARCH64_MOVW_UABS_G3
+        movz    x0, #:abs_g3:f
+# R_AARCH64_MOVW_UABS_G2_NC
+        movk    x0, #:abs_g2_nc:f
+# R_AARCH64_MOVW_UABS_G1_NC
+        movk    x0, #:abs_g1_nc:f
+# R_AARCH64_MOVW_UABS_G0_NC
+        movk    x0, #:abs_g0_nc:f
+        ret
+        .Lfunc_end0:
+        .size   g, .Lfunc_end0-g
+
+        .type   k,@object
+        .data
+        .globl  k
+        .p2align        3
+k:
+        .xword  f
+        .size   k, 8
+
+# LE instructions read as BE
+# rtdyld-check: *{4}(g) = 0x6024e0d2
+# rtdyld-check: *{4}(g + 4) = 0xe0acc8f2
+# rtdyld-check: *{4}(g + 8) = 0x6035b1f2
+# rtdyld-check: *{4}(g + 12) = 0xe0bd99f2
+# rtdyld-check: *{8}k = f
+# RUN: llvm-mc -triple=aarch64_be-none-linux-gnu -filetype=obj -o %T/be-reloc.o %s
+# RUN: llvm-rtdyld -triple=aarch64_be-none-linux-gnu -verify -dummy-extern f=0x0123456789abcdef -check=%s %T/be-reloc.o
+
+        .text
+        .globl  g
+        .p2align        2
+        .type   g,@function
+g:
+# R_AARCH64_MOVW_UABS_G3
+        movz    x0, #:abs_g3:f
+# R_AARCH64_MOVW_UABS_G2_NC
+        movk    x0, #:abs_g2_nc:f
+# R_AARCH64_MOVW_UABS_G1_NC
+        movk    x0, #:abs_g1_nc:f
+# R_AARCH64_MOVW_UABS_G0_NC
+        movk    x0, #:abs_g0_nc:f
+        ret
+        .Lfunc_end0:
+        .size   g, .Lfunc_end0-g
+
+        .type   k,@object
+        .data
+        .globl  k
+        .p2align        3
+k:
+        .xword  f
+        .size   k, 8
+
+# LE instructions read as BE
+# rtdyld-check: *{4}(g) = 0x6024e0d2
+# rtdyld-check: *{4}(g + 4) = 0xe0acc8f2
+# rtdyld-check: *{4}(g + 8) = 0x6035b1f2
+# rtdyld-check: *{4}(g + 12) = 0xe0bd99f2
+# rtdyld-check: *{8}k = f
+# RUN: llvm-mc -triple=aarch64_be-none-linux-gnu -filetype=obj -o %T/be-reloc.o %s
+# RUN: llvm-rtdyld -triple=aarch64_be-none-linux-gnu -verify -dummy-extern f=0x0123456789abcdef -check=%s %T/be-reloc.o
+
+        .text
+        .globl  g
+        .p2align        2
+        .type   g,@function
+g:
+# R_AARCH64_MOVW_UABS_G3
+        movz    x0, #:abs_g3:f
+# R_AARCH64_MOVW_UABS_G2_NC
+        movk    x0, #:abs_g2_nc:f
+# R_AARCH64_MOVW_UABS_G1_NC
+        movk    x0, #:abs_g1_nc:f
+# R_AARCH64_MOVW_UABS_G0_NC
+        movk    x0, #:abs_g0_nc:f
+        ret
+        .Lfunc_end0:
+        .size   g, .Lfunc_end0-g
+
+        .type   k,@object
+        .data
+        .globl  k
+        .p2align        3
+k:
+        .xword  f
+        .size   k, 8
+
+# LE instructions read as BE
+# rtdyld-check: *{4}(g) = 0x6024e0d2
+# rtdyld-check: *{4}(g + 4) = 0xe0acc8f2
+# rtdyld-check: *{4}(g + 8) = 0x6035b1f2
+# rtdyld-check: *{4}(g + 12) = 0xe0bd99f2
+# rtdyld-check: *{8}k = f
+diff --git a/llvm-3.9.1.src/test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_relocations.s b/llvm-3.9.1.src/test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_relocations.s
+new file mode 100644
+index 0000000..e07fa97
+--- /dev/null
+++ b/llvm-3.9.1.src/test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_relocations.s
+@@ -0,0 +1,99 @@
+# RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj -o %T/reloc.o %s
+# RUN: llvm-rtdyld -triple=arm64-none-linux-gnu -verify -dummy-extern f=0x0123456789abcdef -check=%s %T/reloc.o
+
+        .text
+        .globl  g
+        .p2align        2
+        .type   g,@function
+g:
+# R_AARCH64_MOVW_UABS_G3
+        movz    x0, #:abs_g3:f
+# R_AARCH64_MOVW_UABS_G2_NC
+        movk    x0, #:abs_g2_nc:f
+# R_AARCH64_MOVW_UABS_G1_NC
+        movk    x0, #:abs_g1_nc:f
+# R_AARCH64_MOVW_UABS_G0_NC
+        movk    x0, #:abs_g0_nc:f
+        ret
+        .Lfunc_end0:
+        .size   g, .Lfunc_end0-g
+
+        .type   k,@object
+        .data
+        .globl  k
+        .p2align        3
+k:
+        .xword  f
+        .size   k, 8
+
+# rtdyld-check: *{4}(g) = 0xd2e02460
+# rtdyld-check: *{4}(g + 4) = 0xf2c8ace0
+# rtdyld-check: *{4}(g + 8) = 0xf2b13560
+# rtdyld-check: *{4}(g + 12) = 0xf299bde0
+# rtdyld-check: *{8}k = f
+# RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj -o %T/reloc.o %s
+# RUN: llvm-rtdyld -triple=arm64-none-linux-gnu -verify -dummy-extern f=0x0123456789abcdef -check=%s %T/reloc.o
+
+        .text
+        .globl  g
+        .p2align        2
+        .type   g,@function
+g:
+# R_AARCH64_MOVW_UABS_G3
+        movz    x0, #:abs_g3:f
+# R_AARCH64_MOVW_UABS_G2_NC
+        movk    x0, #:abs_g2_nc:f
+# R_AARCH64_MOVW_UABS_G1_NC
+        movk    x0, #:abs_g1_nc:f
+# R_AARCH64_MOVW_UABS_G0_NC
+        movk    x0, #:abs_g0_nc:f
+        ret
+        .Lfunc_end0:
+        .size   g, .Lfunc_end0-g
+
+        .type   k,@object
+        .data
+        .globl  k
+        .p2align        3
+k:
+        .xword  f
+        .size   k, 8
+
+# rtdyld-check: *{4}(g) = 0xd2e02460
+# rtdyld-check: *{4}(g + 4) = 0xf2c8ace0
+# rtdyld-check: *{4}(g + 8) = 0xf2b13560
+# rtdyld-check: *{4}(g + 12) = 0xf299bde0
+# rtdyld-check: *{8}k = f
+# RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj -o %T/reloc.o %s
+# RUN: llvm-rtdyld -triple=arm64-none-linux-gnu -verify -dummy-extern f=0x0123456789abcdef -check=%s %T/reloc.o
+
+        .text
+        .globl  g
+        .p2align        2
+        .type   g,@function
+g:
+# R_AARCH64_MOVW_UABS_G3
+        movz    x0, #:abs_g3:f
+# R_AARCH64_MOVW_UABS_G2_NC
+        movk    x0, #:abs_g2_nc:f
+# R_AARCH64_MOVW_UABS_G1_NC
+        movk    x0, #:abs_g1_nc:f
+# R_AARCH64_MOVW_UABS_G0_NC
+        movk    x0, #:abs_g0_nc:f
+        ret
+        .Lfunc_end0:
+        .size   g, .Lfunc_end0-g
+
+        .type   k,@object
+        .data
+        .globl  k
+        .p2align        3
+k:
+        .xword  f
+        .size   k, 8
+
+# rtdyld-check: *{4}(g) = 0xd2e02460
+# rtdyld-check: *{4}(g + 4) = 0xf2c8ace0
+# rtdyld-check: *{4}(g + 8) = 0xf2b13560
+# rtdyld-check: *{4}(g + 12) = 0xf299bde0
+# rtdyld-check: *{8}k = f
+-- 
+2.12.0
+
--- a/0001-PPC64LE-ELFv2-ABI-updates-for-the-.opd-section.patch
+++ b/0001-PPC64LE-ELFv2-ABI-updates-for-the-.opd-section.patch
@ -0,0 +1,53 @@
+From 04c252cc93fe5905a625773cd174ed6ca7651463 Mon Sep 17 00:00:00 2001
+From: Will Schmidt <will_schmidt@vnet.ibm.com>
+Date: Mon, 24 Mar 2014 16:04:15 +0000
+Subject: [PATCH] [PPC64LE] ELFv2 ABI updates for the .opd section
+
+[PPC64LE] ELFv2 ABI updates for the .opd section
+The PPC64 Little Endian (PPC64LE) target supports the ELFv2 ABI, and as
+such, does not have a ".opd" section.  This is keyed off a _CALL_ELF=2
+macro check.
+
+The CALL_ELF check is not clearly documented at this time.  The basis
+for usage in this patch is from the gcc thread here:
+http://gcc.gnu.org/ml/gcc-patches/2013-11/msg01144.html
+
+> Adding comment from Uli:
+Looks good to me.  I think the old-style JIT doesn't really work
+anyway for 64-bit, but at least with this patch LLVM will compile
+and link again on a ppc64le host ...
+
+
+
+
+git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204614 91177308-0d34-0410-b5e6-96231b3b80d8
+---
+ lib/Target/PowerPC/PPCJITInfo.cpp | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/lib/Target/PowerPC/PPCJITInfo.cpp b/lib/Target/PowerPC/PPCJITInfo.cpp
+index 5e3a48d..227919c 100644
+--- a/lib/Target/PowerPC/PPCJITInfo.cpp
+++ b/lib/Target/PowerPC/PPCJITInfo.cpp
+@@ -214,6 +214,10 @@ asm(
+     ".text\n"
+     ".align 2\n"
+     ".globl PPC64CompilationCallback\n"
+#if _CALL_ELF == 2
+    ".type PPC64CompilationCallback,@function\n"
+"PPC64CompilationCallback:\n"
+#else
+     ".section \".opd\",\"aw\",@progbits\n"
+     ".align 3\n"
+ "PPC64CompilationCallback:\n"
+@@ -223,6 +227,7 @@ asm(
+     ".align 4\n"
+     ".type PPC64CompilationCallback,@function\n"
+ ".L.PPC64CompilationCallback:\n"
+#endif
+ #  else
+ asm(
+     ".text\n"
+-- 
+1.9.3
+
--- a/0001-Revert-Merging-r280589.patch
+++ b/0001-Revert-Merging-r280589.patch
@ -0,0 +1,119 @@
+From 95b15b3d2f180b15267032e16c947c0f9b8a112d Mon Sep 17 00:00:00 2001
+From: Dave Airlie <airlied@redhat.com>
+Date: Wed, 1 Mar 2017 13:02:38 +1000
+Subject: [PATCH] Revert "Merging r280589:"
+
+This reverts commit 25e2616626caafb896517e18cd8aa724fba2b200.
+---
+ lib/Target/AMDGPU/SIInstructions.td   |  1 -
+ lib/Target/AMDGPU/SIWholeQuadMode.cpp |  7 +++++
+ test/CodeGen/AMDGPU/wqm.ll            | 49 +++--------------------------------
+ 3 files changed, 11 insertions(+), 46 deletions(-)
+
+diff --git a/lib/Target/AMDGPU/SIInstructions.td b/lib/Target/AMDGPU/SIInstructions.td
+index dde5f2f..18b7d5d 100644
+--- a/lib/Target/AMDGPU/SIInstructions.td
+++ b/lib/Target/AMDGPU/SIInstructions.td
+@@ -2029,7 +2029,6 @@ def SI_RETURN : PseudoInstSI <
+   let hasSideEffects = 1;
+   let SALU = 1;
+   let hasNoSchedulingInfo = 1;
+-  let DisableWQM = 1;
+ }
+ 
+ let Uses = [EXEC], Defs = [EXEC, VCC, M0],
+diff --git a/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+index 1534d58..b200c15 100644
+--- a/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+++ b/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+@@ -219,6 +219,13 @@ char SIWholeQuadMode::scanInstructions(MachineFunction &MF,
+       markInstruction(MI, Flags, Worklist);
+       GlobalFlags |= Flags;
+     }
+
+    if (WQMOutputs && MBB.succ_empty()) {
+      // This is a prolog shader. Make sure we go back to exact mode at the end.
+      Blocks[&MBB].OutNeeds = StateExact;
+      Worklist.push_back(&MBB);
+      GlobalFlags |= StateExact;
+    }
+   }
+ 
+   return GlobalFlags;
+diff --git a/test/CodeGen/AMDGPU/wqm.ll b/test/CodeGen/AMDGPU/wqm.ll
+index 41e4264..809a7ba 100644
+--- a/test/CodeGen/AMDGPU/wqm.ll
+++ b/test/CodeGen/AMDGPU/wqm.ll
+@@ -17,18 +17,17 @@ main_body:
+ ;CHECK-LABEL: {{^}}test2:
+ ;CHECK-NEXT: ; %main_body
+ ;CHECK-NEXT: s_wqm_b64 exec, exec
+;CHECK: image_sample
+ ;CHECK-NOT: exec
+-define amdgpu_ps void @test2(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <4 x i32> %c) {
+;CHECK: _load_dword v0,
+define amdgpu_ps float @test2(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <4 x i32> %c) {
+ main_body:
+   %c.1 = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %c, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
+   %c.2 = bitcast <4 x float> %c.1 to <4 x i32>
+   %c.3 = extractelement <4 x i32> %c.2, i32 0
+   %gep = getelementptr float, float addrspace(1)* %ptr, i32 %c.3
+   %data = load float, float addrspace(1)* %gep
+-
+-  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %data, float undef, float undef, float undef)
+-
+-  ret void
+  ret float %data
+ }
+ 
+ ; ... but disabled for stores (and, in this simple case, not re-enabled).
+@@ -415,46 +414,6 @@ entry:
+   ret void
+ }
+ 
+-; Must return to exact at the end of a non-void returning shader,
+-; otherwise the EXEC mask exported by the epilog will be wrong. This is true
+-; even if the shader has no kills, because a kill could have happened in a
+-; previous shader fragment.
+-;
+-; CHECK-LABEL: {{^}}test_nonvoid_return:
+-; CHECK: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec
+-; CHECK: s_wqm_b64 exec, exec
+-;
+-; CHECK: s_and_b64 exec, exec, [[LIVE]]
+-; CHECK-NOT: exec
+-define amdgpu_ps <4 x float> @test_nonvoid_return() nounwind {
+-  %tex = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
+-  %tex.i = bitcast <4 x float> %tex to <4 x i32>
+-  %dtex = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %tex.i, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
+-  ret <4 x float> %dtex
+-}
+-
+-; CHECK-LABEL: {{^}}test_nonvoid_return_unreachable:
+-; CHECK: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec
+-; CHECK: s_wqm_b64 exec, exec
+-;
+-; CHECK: s_and_b64 exec, exec, [[LIVE]]
+-; CHECK-NOT: exec
+-define amdgpu_ps <4 x float> @test_nonvoid_return_unreachable(i32 inreg %c) nounwind {
+-entry:
+-  %tex = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
+-  %tex.i = bitcast <4 x float> %tex to <4 x i32>
+-  %dtex = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %tex.i, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
+-
+-  %cc = icmp sgt i32 %c, 0
+-  br i1 %cc, label %if, label %else
+-
+-if:
+-  store volatile <4 x float> %dtex, <4 x float>* undef
+-  unreachable
+-
+-else:
+-  ret <4 x float> %dtex
+-}
+ 
+ declare void @llvm.amdgcn.image.store.v4i32(<4 x float>, <4 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #1
+ declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) #1
+-- 
+2.9.3
+
--- a/0001-This-code-block-breaks-the-docs-build-http-lab.llvm..patch
+++ b/0001-This-code-block-breaks-the-docs-build-http-lab.llvm..patch
@ -0,0 +1,30 @@
+From ce04fe5f8eb9f3a27504db75672083c8aaf80ddd Mon Sep 17 00:00:00 2001
+From: Aaron Ballman <aaron@aaronballman.com>
+Date: Tue, 19 Jul 2016 17:46:55 +0000
+Subject: [PATCH] This code block breaks the docs build
+ (http://lab.llvm.org:8011/builders/llvm-sphinx-docs/builds/11920/steps/docs-llvm-html/logs/stdio),
+ but I cannot see anything immediately wrong with it and cannot reproduce the
+ diagnostic locally. Setting the code highlighting to none instead of nasm to
+ hopefully get the bot stumbling back towards green.
+
+git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275998 91177308-0d34-0410-b5e6-96231b3b80d8
+---
+ docs/AMDGPUUsage.rst | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/docs/AMDGPUUsage.rst b/docs/AMDGPUUsage.rst
+index 34a9b60..7d1ef11 100644
+--- a/docs/AMDGPUUsage.rst
+++ b/docs/AMDGPUUsage.rst
+@@ -171,7 +171,7 @@ keys, see the comments in lib/Target/AMDGPU/AmdKernelCodeT.h
+ 
+ Here is an example of a minimal amd_kernel_code_t specification:
+ 
+-.. code-block:: nasm
+.. code-block:: none
+ 
+    .hsa_code_object_version 1,0
+    .hsa_code_object_isa
+-- 
+2.5.5
+
--- a/0001-X86-Change-getHostCPUName-to-report-Intel-model-0x4e.patch
+++ b/0001-X86-Change-getHostCPUName-to-report-Intel-model-0x4e.patch
@ -0,0 +1,58 @@
+From 6974a461b485113b4e6c6ffc668b8fbc9ce45c6e Mon Sep 17 00:00:00 2001
+From: Craig Topper <craig.topper@gmail.com>
+Date: Thu, 5 Jan 2017 05:47:29 +0000
+Subject: [PATCH] [X86] Change getHostCPUName to report Intel model 0x4e as
+ "skylake" instead of "skylake-avx512". Add the proper 0x55 model for
+ "skylake-avx512".
+
+Summary:
+Intel's i5-6300U CPU is reporting to have a model id of 78 (4e).
+The Host detection assumes that to be Skylake Xeon (with AVX512 support),
+instead of a normal Skylake machine.
+
+Patch by: Valentin Churavy
+
+Reviewers: nalimilan, craig.topper
+
+Subscribers: hfinkel, tkelman, craig.topper, nalimilan, llvm-commits
+
+Differential Revision: https://reviews.llvm.org/D28221
+
+git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291084 91177308-0d34-0410-b5e6-96231b3b80d8
+---
+ lib/Support/Host.cpp | 14 +++++++++++---
+ 1 file changed, 11 insertions(+), 3 deletions(-)
+
+diff --git a/lib/Support/Host.cpp b/lib/Support/Host.cpp
+index 49d0ed5..7593cfc 100644
+--- a/lib/Support/Host.cpp
+++ b/lib/Support/Host.cpp
+@@ -475,14 +475,22 @@ getIntelProcessorTypeAndSubtype(unsigned int Family, unsigned int Model,
+ 
+     // Skylake:
+     case 0x4e:
+-      *Type = INTEL_COREI7; // "skylake-avx512"
+-      *Subtype = INTEL_COREI7_SKYLAKE_AVX512;
+-      break;
+     case 0x5e:
+       *Type = INTEL_COREI7; // "skylake"
+       *Subtype = INTEL_COREI7_SKYLAKE;
+       break;
+ 
+    // Skylake Xeon:
+    case 0x55:
+      *Type = INTEL_COREI7;
+      // Check that we really have AVX512
+      if (Features & (1 << FEATURE_AVX512)) {
+        *Subtype = INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512"
+      } else {
+        *Subtype = INTEL_COREI7_SKYLAKE; // "skylake"
+      }
+      break;
+
+     case 0x1c: // Most 45 nm Intel Atom processors
+     case 0x26: // 45 nm Atom Lincroft
+     case 0x27: // 32 nm Atom Medfield
+-- 
+1.8.3.1
+
--- a/0001-add-gcc-abi_tag-support.patch
+++ b/0001-add-gcc-abi_tag-support.patch
--- a/0001-cmake-Install-CheckAtomic.cmake-needed-by-lldb.patch
+++ b/0001-cmake-Install-CheckAtomic.cmake-needed-by-lldb.patch
@ -0,0 +1,39 @@
+From fdda55bb968b2c39da76baa85a29114f53154944 Mon Sep 17 00:00:00 2001
+From: Chris Bieneman <beanz@apple.com>
+Date: Thu, 25 Aug 2016 20:53:00 +0000
+Subject: [PATCH] cmake: Install CheckAtomic.cmake (needed by lldb)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Summary:
+Install CheckAtomic.cmake along with other LLVM modules, therefore making it possible for other projects to use it. This file is needed for LLDB to be built standalone, and installing it was suggested in https://reviews.llvm.org/D23881.
+
+Patch by: Michał Górny
+
+Reviewers: krytarowski, zturner, eugenis, jyknight, labath, beanz
+
+Subscribers: beanz, llvm-commits
+
+Differential Revision: https://reviews.llvm.org/D23887
+
+git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279777 91177308-0d34-0410-b5e6-96231b3b80d8
+---
+ cmake/modules/CMakeLists.txt | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/cmake/modules/CMakeLists.txt b/cmake/modules/CMakeLists.txt
+index 826dd36..d2510b8 100644
+--- a/cmake/modules/CMakeLists.txt
+++ b/cmake/modules/CMakeLists.txt
+@@ -91,6 +91,5 @@ if (NOT LLVM_INSTALL_TOOLCHAIN_ONLY)
+     PATTERN LLVMConfig.cmake EXCLUDE
+     PATTERN LLVMConfigVersion.cmake EXCLUDE
+     PATTERN LLVM-Config.cmake EXCLUDE
+-    PATTERN GetHostTriple.cmake EXCLUDE
+-    PATTERN CheckAtomic.cmake EXCLUDE)
+    PATTERN GetHostTriple.cmake EXCLUDE)
+ endif()
+-- 
+2.5.5
+
--- a/0001-data-install-preserve-timestamps.patch
+++ b/0001-data-install-preserve-timestamps.patch
@ -0,0 +1,22 @@
+Preserve timestamps when installing data files
+
+---
+ Makefile.rules | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/Makefile.rules b/Makefile.rules
+index f0c542b..0ff92bb 100644
+--- a/Makefile.rules
+++ b/Makefile.rules
+@@ -773,7 +773,7 @@ BCCompile.CXX = $(LLVMCXX) $(CPP.Flags) $(CXX.Flags) $(CXXFLAGS) $(CPPFLAGS) \
+ 
+ ProgInstall   = $(INSTALL) $(Install.StripFlag) -m 0755
+ ScriptInstall = $(INSTALL) -m 0755
+-DataInstall   = $(INSTALL) -m 0644
+DataInstall   = $(INSTALL) -p -m 0644
+ 
+ # When compiling under Mingw/Cygwin, the tblgen tool expects Windows
+ # paths. In this case, the SYSPATH function (defined in
+-- 
+1.8.3.1
+
--- a/0001-docs-fix-cmake-code-block-warning.patch
+++ b/0001-docs-fix-cmake-code-block-warning.patch
@ -0,0 +1,44 @@
+From f12c36b2bc2e1db86098c181b88b8003c595e63c Mon Sep 17 00:00:00 2001
+From: Renato Golin <renato.golin@linaro.org>
+Date: Wed, 20 Jul 2016 09:47:09 +0000
+Subject: [PATCH] [docs] fix cmake code-block warning
+
+This will unblock the llvm-sphinx-buildbot, which is currently failing due
+to a warning being treated as error.
+
+git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276100 91177308-0d34-0410-b5e6-96231b3b80d8
+---
+ docs/CMakePrimer.rst | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/docs/CMakePrimer.rst b/docs/CMakePrimer.rst
+index 0347790..1e3a09e 100644
+--- a/docs/CMakePrimer.rst
+++ b/docs/CMakePrimer.rst
+@@ -246,11 +246,11 @@ In general CMake if blocks work the way you'd expect:
+ .. code-block:: cmake
+ 
+   if(<condition>)
+-    .. do stuff
+    message("do stuff")
+   elseif(<condition>)
+-    .. do other stuff
+    message("do other stuff")
+   else()
+-    .. do other other stuff
+    message("do other other stuff")
+   endif()
+ 
+ The single most important thing to know about CMake's if blocks coming from a C
+@@ -265,7 +265,7 @@ The most common form of the CMake ``foreach`` block is:
+ .. code-block:: cmake
+ 
+   foreach(var ...)
+-    .. do stuff
+    message("do stuff")
+   endforeach()
+ 
+ The variable argument portion of the ``foreach`` block can contain dereferenced
+-- 
+2.5.5
+
--- a/0001-fix-docs-2.patch
+++ b/0001-fix-docs-2.patch
@ -0,0 +1,38 @@
+From de4fbfe93560c78f29c8b92cafab0793f5d26bc6 Mon Sep 17 00:00:00 2001
+From: Aaron Ballman <aaron@aaronballman.com>
+Date: Tue, 19 Jul 2016 20:20:03 +0000
+Subject: [PATCH] This code block breaks the docs build
+ (http://lab.llvm.org:8011/builders/llvm-sphinx-docs/builds/11921/steps/docs-llvm-html/logs/stdio).
+ Setting the code highlighting to none instead of llvm to hopefully get the
+ bot stumbling back towards green.
+
+git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276018 91177308-0d34-0410-b5e6-96231b3b80d8
+---
+ docs/BitCodeFormat.rst | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/docs/BitCodeFormat.rst b/docs/BitCodeFormat.rst
+index ffa2176..89c7c1b 100644
+--- a/docs/BitCodeFormat.rst
+++ b/docs/BitCodeFormat.rst
+@@ -596,7 +596,7 @@ will be encoded as 1.
+ 
+ For example, instead of
+ 
+-.. code-block:: llvm
+.. code-block:: none
+ 
+   #n = load #n-1
+   #n+1 = icmp eq #n, #const0
+@@ -604,7 +604,7 @@ For example, instead of
+ 
+ version 1 will encode the instructions as
+ 
+-.. code-block:: llvm
+.. code-block:: none
+ 
+   #n = load #1
+   #n+1 = icmp eq #1, (#n+1)-#const0
+-- 
+2.5.5
+
--- a/0001-fix-docs-3.patch
+++ b/0001-fix-docs-3.patch
@ -0,0 +1,46 @@
+From 9871423412faa2ed8380445a26ed1b0991a18502 Mon Sep 17 00:00:00 2001
+From: Aaron Ballman <aaron@aaronballman.com>
+Date: Tue, 19 Jul 2016 23:50:11 +0000
+Subject: [PATCH] This code block breaks the docs build
+ (http://lab.llvm.org:8011/builders/llvm-sphinx-docs/builds/11925/steps/docs-llvm-html/logs/stdio).
+ Setting the code highlighting to none instead of llvm.
+
+git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276060 91177308-0d34-0410-b5e6-96231b3b80d8
+---
+ docs/BranchWeightMetadata.rst | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/docs/BranchWeightMetadata.rst b/docs/BranchWeightMetadata.rst
+index 6cbcb0f..9e61d23 100644
+--- a/docs/BranchWeightMetadata.rst
+++ b/docs/BranchWeightMetadata.rst
+@@ -29,7 +29,7 @@ Supported Instructions
+ Metadata is only assigned to the conditional branches. There are two extra
+ operands for the true and the false branch.
+ 
+-.. code-block:: llvm
+.. code-block:: none
+ 
+   !0 = metadata !{
+     metadata !"branch_weights",
+@@ -43,7 +43,7 @@ operands for the true and the false branch.
+ Branch weights are assigned to every case (including the ``default`` case which
+ is always case #0).
+ 
+-.. code-block:: llvm
+.. code-block:: none
+ 
+   !0 = metadata !{
+     metadata !"branch_weights",
+@@ -56,7 +56,7 @@ is always case #0).
+ 
+ Branch weights are assigned to every destination.
+ 
+-.. code-block:: llvm
+.. code-block:: none
+ 
+   !0 = metadata !{
+     metadata !"branch_weights",
+-- 
+2.5.5
+
--- a/0002-Adapt-previous-Clang-trunk-patch-to-Clang-3.7.patch
+++ b/0002-Adapt-previous-Clang-trunk-patch-to-Clang-3.7.patch
@ -0,0 +1,24 @@
+From e746af90e6aa52af6e6bb0b88ffe20dbd97a1e4d Mon Sep 17 00:00:00 2001
+From: Stephan Bergmann <sbergman@redhat.com>
+Date: Thu, 3 Dec 2015 14:53:39 +0100
+Subject: [PATCH 2/3] Adapt previous (Clang trunk) patch to Clang 3.7
+
+---
+ lib/AST/ItaniumMangle.cpp | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/lib/AST/ItaniumMangle.cpp b/lib/AST/ItaniumMangle.cpp
+index e32b659..19a09dc 100644
+--- a/tools/clang/lib/AST/ItaniumMangle.cpp
+++ b/tools/clang/lib/AST/ItaniumMangle.cpp
+@@ -31,6 +31,7 @@
+ #include "llvm/ADT/StringExtras.h"
+ #include "llvm/Support/ErrorHandling.h"
+ #include "llvm/Support/raw_ostream.h"
+#include <set>
+ 
+ #define MANGLE_CHECKER 0
+ 
+-- 
+2.4.3
+
--- a/0002-linker-flags-speedup-memory.patch
+++ b/0002-linker-flags-speedup-memory.patch
@ -0,0 +1,12 @@
+diff -up llvm-3.4/tools/llvm-shlib/Makefile.orig llvm-3.4/tools/llvm-shlib/Makefile
+--- llvm-3.4/tools/llvm-shlib/Makefile.orig	2013-11-01 00:35:00.000000000 +1000
+++ llvm-3.4/tools/llvm-shlib/Makefile	2014-01-14 10:13:20.069858909 +1000
+@@ -75,7 +75,7 @@ endif
+ 
+ ifeq ($(HOST_OS), $(filter $(HOST_OS), Linux GNU GNU/kFreeBSD))
+     # Don't allow unresolved symbols.
+-    LLVMLibsOptions += -Wl,--no-undefined
+    LLVMLibsOptions += -Wl,--no-undefined -Wl,-Bsymbolic
+ endif
+ 
+ ifeq ($(HOST_OS),SunOS)
--- a/clang-3.4-arm-hard-float.patch
+++ b/clang-3.4-arm-hard-float.patch
@ -0,0 +1,16 @@
+diff -up llvm-3.4.1.src/tools/clang/lib/Driver/Tools.cpp.jx llvm-3.4.1.src/tools/clang/lib/Driver/Tools.cpp
+--- llvm-3.4.1.src/tools/clang/lib/Driver/Tools.cpp.jx	2013-12-08 21:59:27.000000000 -0500
+++ llvm-3.4.1.src/tools/clang/lib/Driver/Tools.cpp	2014-06-02 11:24:07.628292753 -0400
+@@ -763,9 +763,9 @@ static StringRef getARMFloatABI(const Dr
+         break;
+       }
+       default:
+-        // Assume "soft", but warn the user we are guessing.
+-        FloatABI = "soft";
+-        D.Diag(diag::warn_drv_assuming_mfloat_abi_is) << "soft";
+        // Assume "hard", but warn the user we are guessing.
+        FloatABI = "hard";
+        D.Diag(diag::warn_drv_assuming_mfloat_abi_is) << "hard";
+         break;
+       }
+     }
--- a/fix-broken-include-path.patch
+++ b/fix-broken-include-path.patch
@ -0,0 +1,12 @@
+diff -up llvm-3.7.0.src/include/llvm/CodeGen/CommandFlags.h.dma llvm-3.7.0.src/include/llvm/CodeGen/CommandFlags.h
+--- llvm-3.7.0.src/include/llvm/CodeGen/CommandFlags.h.dma	2015-09-15 15:01:41.570871134 +1000
+++ llvm-3.7.0.src/include/llvm/CodeGen/CommandFlags.h	2015-09-15 15:01:53.642191476 +1000
+@@ -21,7 +21,7 @@
+ #include "llvm/IR/Intrinsics.h"
+ #include "llvm/IR/Module.h"
+ #include "llvm/MC/MCTargetOptionsCommandFlags.h"
+-#include "llvm//MC/SubtargetFeature.h"
+#include "llvm/MC/SubtargetFeature.h"
+ #include "llvm/Support/CodeGen.h"
+ #include "llvm/Support/CommandLine.h"
+ #include "llvm/Support/Host.h"
--- a/gating.yaml
+++ b/gating.yaml
@ -1,12 +0,0 @@
--- !Policy
-product_versions:
-  - fedora-*
-decision_context: bodhi_update_push_testing
-rules:
-  - !PassingTestCaseRule {test_case_name: org.centos.prod.ci.pipeline.allpackages-build.package.test.functional.complete}
--- !Policy
-product_versions:
-  - fedora-*
-decision_context: bodhi_update_push_stable
-rules:
-  - !PassingTestCaseRule {test_case_name: org.centos.prod.ci.pipeline.allpackages-build.package.test.functional.complete}
--- a/hans-gpg-key.asc
+++ b/hans-gpg-key.asc
@ -1,52 +0,0 @@
-----BEGIN PGP PUBLIC KEY BLOCK-----
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--- a/lit.fedora.cfg.py
+++ b/lit.fedora.cfg.py
@ -1,17 +0,0 @@
-
-config.llvm_tools_dir = '/usr/bin'
-config.llvm_shlib_dir = '%(llvm_shlib_dir)s' % lit_config.params
-
-if hasattr(config, 'host_triple'):
-    # This means we are running lit regression tests
-
-    # Regression tests write output to this directory, so we need to be able to specify
-    # a temp directory when invoking lit. e.g. lit -Dllvm_obj_root=/tmp/lit
-    config.llvm_obj_root = "%(llvm_obj_root)s" % lit_config.params
-    lit_config.load_config(config, '%(llvm_test_root)s/lit.cfg.py' % lit_config.params)
-else:
-    # This means we are running lit unit tests
-
-    # For unit tests, llvm_obj_root is used to find the unit test binaries.
-    config.llvm_obj_root = '%(llvm_unittest_bindir)s' % lit_config.params
-    lit_config.load_config(config, '%(llvm_test_root)s/Unit/lit.cfg.py' % lit_config.params)
--- a/lldb-python-module-symlink.patch
+++ b/lldb-python-module-symlink.patch
@ -0,0 +1,16 @@
+Fix broken symlink to Python's lldb module
+
+Resolves: #1177143
+
+diff -rupN lldb-3.5.0.src/scripts/Python/finish-swig-Python-LLDB.sh lldb-3.5.0.src-new/scripts/Python/finish-swig-Python-LLDB.sh
+--- lldb-3.5.0.src/scripts/Python/finish-swig-Python-LLDB.sh	2014-07-01 19:57:19.000000000 +0200
+++ lldb-3.5.0.src-new/scripts/Python/finish-swig-Python-LLDB.sh	2014-12-24 14:18:10.068604693 +0100
+@@ -158,7 +158,7 @@ then
+     then
+         ln -s "../../../LLDB" _lldb.so
+ 	else
+-        ln -s "../../../liblldb${SOEXT}" _lldb.so
+        ln -s "../../../llvm/liblldb${SOEXT}" _lldb.so
+     fi
+ else
+     if [ $Debug -eq 1 ]
--- a/lldb-python.patch
+++ b/lldb-python.patch
@ -0,0 +1,16 @@
+diff -up lldb/scripts/Python/modules/readline/Makefile.jx lldb/scripts/Python/modules/readline/Makefile
+--- lldb/scripts/Python/modules/readline/Makefile.jx	2014-02-26 10:05:48.000000000 -0500
+++ lldb/scripts/Python/modules/readline/Makefile	2014-10-14 11:55:05.112566400 -0400
+@@ -91,9 +91,8 @@ $(LLDB_PYTHON_MODULE_DIR)/$(LIBRARYNAME)
+ # Target to move the shared library from the build python lib dir to
+ # the install python lib dir.
+ install-local:: $(LLDB_PYTHON_MODULE_DIR)/$(LIBRARYNAME)$(SHLIBEXT)
+-	$(Echo) Installing $(BuildMode) $(LLDB_PYTHON_MODULE_DIR)/$(LIBRARYNAME)$(SHLIBEXT) to $(DESTDIR)$(prefix)/lib/$(LLDB_PYTHON_MODULE_REL_DIR)
+-	$(Verb) $(MKDIR) "$(DESTDIR)$(prefix)/lib/$(LLDB_PYTHON_MODULE_REL_DIR)"
+-	$(Verb) $(ProgInstall) "$(LLDB_PYTHON_MODULE_DIR)/$(LIBRARYNAME)$(SHLIBEXT)" "$(DESTDIR)$(prefix)/lib/$(LLDB_PYTHON_MODULE_REL_DIR)"
+-	$(Verb) $(RM) "$(DESTDIR)$(prefix)/lib/$(LIBRARYNAME)$(SHLIBEXT)"
+	$(Echo) Installing $(BuildMode) $(LLDB_PYTHON_MODULE_DIR)/$(LIBRARYNAME)$(SHLIBEXT) to $(DESTDIR)$(prefix)/@lib@/$(LLDB_PYTHON_MODULE_REL_DIR)
+	$(Verb) $(MKDIR) "$(DESTDIR)$(prefix)/@lib@/$(LLDB_PYTHON_MODULE_REL_DIR)"
+	$(Verb) $(ProgInstall) "$(LLDB_PYTHON_MODULE_DIR)/$(LIBRARYNAME)$(SHLIBEXT)" "$(DESTDIR)$(prefix)/@lib@/$(LLDB_PYTHON_MODULE_REL_DIR)"
+
+ endif  # if !defined(LLDB_DISABLE_PYTHON)
--- a/llvm-3.4-radeonsi-backport.patch
+++ b/llvm-3.4-radeonsi-backport.patch
@ -0,0 +1,459 @@
+diff --git a/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp b/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
+index 99e1377..7105879 100644
+--- a/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
+++ b/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
+@@ -316,6 +316,37 @@ void AMDGPUInstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
+   }
+ }
+ 
+void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
+                                     raw_ostream &O) {
+  unsigned SImm16 = MI->getOperand(OpNo).getImm();
+  unsigned Msg = SImm16 & 0xF;
+  if (Msg == 2 || Msg == 3) {
+    unsigned Op = (SImm16 >> 4) & 0xF;
+    if (Msg == 3)
+      O << "Gs_done(";
+    else
+      O << "Gs(";
+    if (Op == 0) {
+      O << "nop";
+    } else {
+      unsigned Stream = (SImm16 >> 8) & 0x3;
+      if (Op == 1)
+	O << "cut";
+      else if (Op == 2)
+	O << "emit";
+      else if (Op == 3)
+	O << "emit-cut";
+      O << " stream " << Stream;
+    }
+    O << "), [m0] ";
+  } else if (Msg == 1)
+    O << "interrupt ";
+  else if (Msg == 15)
+    O << "system ";
+  else
+    O << "unknown(" << Msg << ") ";
+}
+
+ void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
+                                       raw_ostream &O) {
+   // Note: Mask values are taken from SIInsertWaits.cpp and not from ISA docs
+diff --git a/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h b/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h
+index 77af942..2876dd2 100644
+--- a/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h
+++ b/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h
+@@ -53,6 +53,7 @@ private:
+   void printRSel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+   void printCT(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+   void printKCache(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+  void printSendMsg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+   void printWaitFlag(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+ };
+ 
+diff --git a/lib/Target/R600/SIInsertWaits.cpp b/lib/Target/R600/SIInsertWaits.cpp
+index 7ef662e..695ec40 100644
+--- a/lib/Target/R600/SIInsertWaits.cpp
+++ b/lib/Target/R600/SIInsertWaits.cpp
+@@ -314,6 +314,12 @@ Counters SIInsertWaits::handleOperands(MachineInstr &MI) {
+ 
+   Counters Result = ZeroCounts;
+ 
+  // S_SENDMSG implicitly waits for all outstanding LGKM transfers to finish,
+  // but we also want to wait for any other outstanding transfers before
+  // signalling other hardware blocks
+  if (MI.getOpcode() == AMDGPU::S_SENDMSG)
+    return LastIssued;
+
+   // For each register affected by this
+   // instruction increase the result sequence
+   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
+diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
+index 4cd0daa..19d2171 100644
+--- a/lib/Target/R600/SIInstrInfo.td
+++ b/lib/Target/R600/SIInstrInfo.td
+@@ -425,26 +425,48 @@ class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBU
+ 
+ multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> {
+ 
+-  let glc = 0, lds = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */,
+-                                          mayLoad = 1 in {
+-
+-  let offen = 1, idxen = 0, addr64 = 0, offset = 0 in {
+-    def _OFFEN  : MUBUF <op, (outs regClass:$vdata),
+-                         (ins SReg_128:$srsrc, VReg_32:$vaddr),
+-                         asm#" $vdata, $srsrc + $vaddr", []>;
+-  }
+-
+-  let offen = 0, idxen = 1, addr64 = 0 in {
+-    def _IDXEN  : MUBUF <op, (outs regClass:$vdata),
+-                         (ins SReg_128:$srsrc, VReg_32:$vaddr, i16imm:$offset),
+-                         asm#" $vdata, $srsrc[$vaddr] + $offset", []>;
+-  }
+  let lds = 0, mayLoad = 1 in {
+
+    let addr64 = 0 in {
+
+      let offen = 0, idxen = 0 in {
+        def _OFFSET : MUBUF <op, (outs regClass:$vdata),
+                             (ins SReg_128:$srsrc, VReg_32:$vaddr,
+                             i16imm:$offset, SSrc_32:$soffset, i1imm:$glc,
+                             i1imm:$slc, i1imm:$tfe),
+                             asm#" $vdata, $srsrc + $offset + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
+      }
+
+      let offen = 1, idxen = 0, offset = 0 in {
+        def _OFFEN  : MUBUF <op, (outs regClass:$vdata),
+                             (ins SReg_128:$srsrc, VReg_32:$vaddr,
+                             SSrc_32:$soffset, i1imm:$glc, i1imm:$slc,
+                             i1imm:$tfe),
+                             asm#" $vdata, $srsrc + $vaddr + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
+      }
+
+      let offen = 0, idxen = 1 in {
+        def _IDXEN  : MUBUF <op, (outs regClass:$vdata),
+                             (ins SReg_128:$srsrc, VReg_32:$vaddr,
+                             i16imm:$offset, SSrc_32:$soffset, i1imm:$glc,
+                             i1imm:$slc, i1imm:$tfe),
+                             asm#" $vdata, $srsrc[$vaddr] + $offset + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
+      }
+
+      let offen = 1, idxen = 1 in {
+        def _BOTHEN : MUBUF <op, (outs regClass:$vdata),
+                             (ins SReg_128:$srsrc, VReg_64:$vaddr,
+                             SSrc_32:$soffset, i1imm:$glc,
+                             i1imm:$slc, i1imm:$tfe),
+                             asm#" $vdata, $srsrc[$vaddr[0]] + $vaddr[1] + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
+      }
+    }
+ 
+-  let offen = 0, idxen = 0, addr64 = 1 in {
+-    def _ADDR64 : MUBUF <op, (outs regClass:$vdata),
+-                         (ins SReg_128:$srsrc, VReg_64:$vaddr, i16imm:$offset),
+-                         asm#" $vdata, $srsrc + $vaddr + $offset", []>;
+-  }
+    let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
+      def _ADDR64 : MUBUF <op, (outs regClass:$vdata),
+                           (ins SReg_128:$srsrc, VReg_64:$vaddr, i16imm:$offset),
+                           asm#" $vdata, $srsrc + $vaddr + $offset", []>;
+    }
+   }
+ }
+ 
+diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
+index 76f05eb..9acb9b6 100644
+--- a/lib/Target/R600/SIInstructions.td
+++ b/lib/Target/R600/SIInstructions.td
+@@ -22,6 +22,10 @@ def InterpSlot : Operand<i32> {
+   let PrintMethod = "printInterpSlot";
+ }
+ 
+def SendMsgImm : Operand<i32> {
+  let PrintMethod = "printSendMsg";
+}
+
+ def isSI : Predicate<"Subtarget.getGeneration() "
+                       ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">;
+ 
+@@ -826,17 +830,25 @@ def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER",
+ def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16",
+   []
+ >;
+-} // End hasSideEffects
+ //def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>;
+ //def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>;
+ //def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>;
+-//def S_SENDMSG : SOPP_ <0x00000010, "S_SENDMSG", []>;
+
+let Uses = [EXEC] in {
+  def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "S_SENDMSG $simm16",
+      [(int_SI_sendmsg imm:$simm16, M0Reg:$m0)]
+  > {
+    let DisableEncoding = "$m0";
+  }
+} // End Uses = [EXEC]
+
+ //def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>;
+ //def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>;
+ //def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>;
+ //def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>;
+ //def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>;
+ //def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>;
+} // End hasSideEffects
+ 
+ def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst),
+   (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc),
+@@ -1305,8 +1317,8 @@ def SI_END_CF : InstSI <
+ 
+ def SI_KILL : InstSI <
+   (outs),
+-  (ins VReg_32:$src),
+-  "SI_KIL $src",
+  (ins VSrc_32:$src),
+  "SI_KILL $src",
+   [(int_AMDGPU_kill f32:$src)]
+ >;
+ 
+@@ -1397,13 +1409,13 @@ def : Pat<
+ 
+ def : Pat <
+   (int_AMDGPU_kilp),
+-  (SI_KILL (V_MOV_B32_e32 0xbf800000))
+  (SI_KILL 0xbf800000)
+ >;
+ 
+ /* int_SI_vs_load_input */
+ def : Pat<
+   (SIload_input i128:$tlst, IMM12bit:$attr_offset, i32:$buf_idx_vgpr),
+-  (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset)
+  (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0)
+ >;
+ 
+ /* int_SI_export */
+@@ -1809,7 +1821,7 @@ def : Pat <
+ // 3. Offset in an 32Bit VGPR
+ def : Pat <
+   (SIload_constant i128:$sbase, i32:$voff),
+-  (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff)
+  (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0)
+ >;
+ 
+ // The multiplication scales from [0,1] to the unsigned integer range
+@@ -1970,6 +1982,50 @@ defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, i64, global_store>;
+ defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, v2i32, global_store>;
+ defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4, v4i32, global_store>;
+ 
+// BUFFER_LOAD_DWORD*, addr64=0
+multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen,
+                             MUBUF bothen> {
+
+  def : Pat <
+    (vt (int_SI_buffer_load_dword i128:$rsrc, i32:$vaddr, i32:$soffset,
+                                  imm:$offset, 0, 0, imm:$glc, imm:$slc,
+                                  imm:$tfe)),
+    (offset $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
+            (as_i1imm $slc), (as_i1imm $tfe))
+  >;
+
+  def : Pat <
+    (vt (int_SI_buffer_load_dword i128:$rsrc, i32:$vaddr, i32:$soffset,
+                                  imm, 1, 0, imm:$glc, imm:$slc,
+                                  imm:$tfe)),
+    (offen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
+           (as_i1imm $tfe))
+  >;
+
+  def : Pat <
+    (vt (int_SI_buffer_load_dword i128:$rsrc, i32:$vaddr, i32:$soffset,
+                                  imm:$offset, 0, 1, imm:$glc, imm:$slc,
+                                  imm:$tfe)),
+    (idxen $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
+           (as_i1imm $slc), (as_i1imm $tfe))
+  >;
+
+  def : Pat <
+    (vt (int_SI_buffer_load_dword i128:$rsrc, v2i32:$vaddr, i32:$soffset,
+                                  imm, 1, 1, imm:$glc, imm:$slc,
+                                  imm:$tfe)),
+    (bothen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
+            (as_i1imm $tfe))
+  >;
+}
+
+defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN,
+                         BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>;
+defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN,
+                         BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>;
+defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN,
+                         BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>;
+
+ //===----------------------------------------------------------------------===//
+ // MTBUF Patterns
+ //===----------------------------------------------------------------------===//
+diff --git a/lib/Target/R600/SIIntrinsics.td b/lib/Target/R600/SIIntrinsics.td
+index 7fcc964..00e32c0 100644
+--- a/lib/Target/R600/SIIntrinsics.td
+++ b/lib/Target/R600/SIIntrinsics.td
+@@ -38,6 +38,22 @@ let TargetPrefix = "SI", isTarget = 1 in {
+      llvm_i32_ty],   // tfe(imm)
+     []>;
+ 
+  // Fully-flexible BUFFER_LOAD_DWORD_* except for the ADDR64 bit, which is not exposed
+  def int_SI_buffer_load_dword : Intrinsic <
+    [llvm_anyint_ty], // vdata(VGPR), overloaded for types i32, v2i32, v4i32
+    [llvm_anyint_ty,  // rsrc(SGPR)
+     llvm_anyint_ty,  // vaddr(VGPR)
+     llvm_i32_ty,     // soffset(SGPR)
+     llvm_i32_ty,     // inst_offset(imm)
+     llvm_i32_ty,     // offen(imm)
+     llvm_i32_ty,     // idxen(imm)
+     llvm_i32_ty,     // glc(imm)
+     llvm_i32_ty,     // slc(imm)
+     llvm_i32_ty],    // tfe(imm)
+    [IntrReadArgMem]>;
+
+  def int_SI_sendmsg : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
+
+   class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_anyvector_ty, llvm_v32i8_ty, llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
+ 
+   def int_SI_sample : Sample;
+diff --git a/lib/Target/R600/SILowerControlFlow.cpp b/lib/Target/R600/SILowerControlFlow.cpp
+index 958763d..254f3a6 100644
+--- a/lib/Target/R600/SILowerControlFlow.cpp
+++ b/lib/Target/R600/SILowerControlFlow.cpp
+@@ -55,6 +55,7 @@
+ #include "llvm/CodeGen/MachineFunctionPass.h"
+ #include "llvm/CodeGen/MachineInstrBuilder.h"
+ #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/IR/Constants.h"
+ 
+ using namespace llvm;
+ 
+@@ -145,7 +146,9 @@ void SILowerControlFlowPass::SkipIfDead(MachineInstr &MI) {
+   MachineBasicBlock &MBB = *MI.getParent();
+   DebugLoc DL = MI.getDebugLoc();
+ 
+-  if (!shouldSkip(&MBB, &MBB.getParent()->back()))
+  if (MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType !=
+      ShaderType::PIXEL ||
+      !shouldSkip(&MBB, &MBB.getParent()->back()))
+     return;
+ 
+   MachineBasicBlock::iterator Insert = &MI;
+@@ -295,15 +298,27 @@ void SILowerControlFlowPass::Kill(MachineInstr &MI) {
+ 
+   MachineBasicBlock &MBB = *MI.getParent();
+   DebugLoc DL = MI.getDebugLoc();
+  const MachineOperand &Op = MI.getOperand(0);
+ 
+-  // Kill is only allowed in pixel shaders
+  // Kill is only allowed in pixel / geometry shaders
+   assert(MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType ==
+-         ShaderType::PIXEL);
+-
+-  // Clear this pixel from the exec mask if the operand is negative
+-  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC)
+-          .addImm(0)
+-          .addOperand(MI.getOperand(0));
+         ShaderType::PIXEL ||
+         MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType ==
+         ShaderType::GEOMETRY);
+
+  // Clear this thread from the exec mask if the operand is negative
+  if ((Op.isImm() || Op.isFPImm())) {
+    // Constant operand: Set exec mask to 0 or do nothing
+    if (Op.isImm() ? (Op.getImm() & 0x80000000) :
+        Op.getFPImm()->isNegative()) {
+      BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
+              .addImm(0);
+    }
+  } else {
+    BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC)
+           .addImm(0)
+           .addOperand(Op);
+  }
+ 
+   MI.eraseFromParent();
+ }
+diff --git a/test/CodeGen/R600/llvm.AMDGPU.kill.ll b/test/CodeGen/R600/llvm.AMDGPU.kill.ll
+new file mode 100644
+index 0000000..4ab6a8a
+--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.kill.ll
+@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI %s
+
+; SI-LABEL: @kill_gs_const
+; SI-NOT: V_CMPX_LE_F32
+; SI: S_MOV_B64 exec, 0
+
+define void @kill_gs_const() #0 {
+main_body:
+  %0 = icmp ule i32 0, 3
+  %1 = select i1 %0, float 1.000000e+00, float -1.000000e+00
+  call void @llvm.AMDGPU.kill(float %1)
+  %2 = icmp ule i32 3, 0
+  %3 = select i1 %2, float 1.000000e+00, float -1.000000e+00
+  call void @llvm.AMDGPU.kill(float %3)
+  ret void
+}
+
+declare void @llvm.AMDGPU.kill(float)
+
+attributes #0 = { "ShaderType"="2" }
+
+!0 = metadata !{metadata !"const", null, i32 1}
+diff --git a/test/CodeGen/R600/llvm.SI.load.dword.ll b/test/CodeGen/R600/llvm.SI.load.dword.ll
+new file mode 100644
+index 0000000..a622775
+--- /dev/null
+++ b/test/CodeGen/R600/llvm.SI.load.dword.ll
+@@ -0,0 +1,40 @@
+;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
+
+; Example of a simple geometry shader loading vertex attributes from the
+; ESGS ring buffer
+
+; CHECK-LABEL: @main
+; CHECK: BUFFER_LOAD_DWORD
+; CHECK: BUFFER_LOAD_DWORD
+; CHECK: BUFFER_LOAD_DWORD
+; CHECK: BUFFER_LOAD_DWORD
+
+define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [2 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32, i32, i32, i32) #0 {
+main_body:
+  %10 = getelementptr [2 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
+  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
+  %12 = shl i32 %6, 2
+  %13 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %11, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0)
+  %14 = bitcast i32 %13 to float
+  %15 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %11, i32 %12, i32 0, i32 0, i32 1, i32 0, i32 1, i32 1, i32 0)
+  %16 = bitcast i32 %15 to float
+  %17 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %11, i32 %12, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 0)
+  %18 = bitcast i32 %17 to float
+  %19 = call i32 @llvm.SI.buffer.load.dword.i32.v2i32(<16 x i8> %11, <2 x i32> <i32 0, i32 0>, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1, i32 0)
+  %20 = bitcast i32 %19 to float
+  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %14, float %16, float %18, float %20)
+  ret void
+}
+
+; Function Attrs: nounwind readonly
+declare i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
+
+; Function Attrs: nounwind readonly
+declare i32 @llvm.SI.buffer.load.dword.i32.v2i32(<16 x i8>, <2 x i32>, i32, i32, i32, i32, i32, i32, i32) #1
+
+declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
+
+attributes #0 = { "ShaderType"="1" }
+attributes #1 = { nounwind readonly }
+
+!0 = metadata !{metadata !"const", null, i32 1}
+diff --git a/test/CodeGen/R600/llvm.SI.sendmsg.ll b/test/CodeGen/R600/llvm.SI.sendmsg.ll
+new file mode 100644
+index 0000000..581d422
+--- /dev/null
+++ b/test/CodeGen/R600/llvm.SI.sendmsg.ll
+@@ -0,0 +1,21 @@
+;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
+
+; CHECK-LABEL: @main
+; CHECK: S_SENDMSG Gs(emit stream 0)
+; CHECK: S_SENDMSG Gs(cut stream 1)
+; CHECK: S_SENDMSG Gs(emit-cut stream 2)
+; CHECK: S_SENDMSG Gs_done(nop)
+
+define void @main() {
+main_body:
+  call void @llvm.SI.sendmsg(i32 34, i32 0);
+  call void @llvm.SI.sendmsg(i32 274, i32 0);
+  call void @llvm.SI.sendmsg(i32 562, i32 0);
+  call void @llvm.SI.sendmsg(i32 3, i32 0);
+  ret void
+}
+
+; Function Attrs: nounwind
+declare void @llvm.SI.sendmsg(i32, i32) #0
+
+attributes #0 = { nounwind }
--- a/llvm-3.7.1-cmake-s390.patch
+++ b/llvm-3.7.1-cmake-s390.patch
@ -0,0 +1,12 @@
+diff -up llvm-3.7.1.src/cmake/config-ix.cmake.s390 llvm-3.7.1.src/cmake/config-ix.cmake
+--- llvm-3.7.1.src/cmake/config-ix.cmake.s390	2016-02-16 12:27:36.000000000 +0100
+++ llvm-3.7.1.src/cmake/config-ix.cmake	2016-02-16 12:27:52.000000000 +0100
+@@ -356,6 +356,8 @@ elseif (LLVM_NATIVE_ARCH MATCHES "msp430
+   set(LLVM_NATIVE_ARCH MSP430)
+ elseif (LLVM_NATIVE_ARCH MATCHES "hexagon")
+   set(LLVM_NATIVE_ARCH Hexagon)
+elseif (LLVM_NATIVE_ARCH MATCHES "s390")
+  set(LLVM_NATIVE_ARCH SystemZ)
+ elseif (LLVM_NATIVE_ARCH MATCHES "s390x")
+   set(LLVM_NATIVE_ARCH SystemZ)
+ elseif (LLVM_NATIVE_ARCH MATCHES "wasm32")
--- a/llvm-config.h
+++ b/llvm-config.h
@ -0,0 +1,9 @@
+#include <bits/wordsize.h>
+
+#if __WORDSIZE == 32
+#include "llvm-config-32.h"
+#elif __WORDSIZE == 64
+#include "llvm-config-64.h"
+#else
+#error "Unknown word size"
+#endif
--- a/llvm-d18644-systemz-atomic-fence.patch
+++ b/llvm-d18644-systemz-atomic-fence.patch
@ -0,0 +1,169 @@
+Index: llvm/trunk/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+===================================================================
+--- llvm/trunk/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+++ llvm/trunk/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+@@ -260,6 +260,11 @@
+         .addImm(15).addReg(SystemZ::R0D);
+     break;
+ 
+  // Emit nothing here but a comment if we can.
+  case SystemZ::MemBarrier:
+    OutStreamer->emitRawComment("MEMBARRIER");
+    return;
+
+   default:
+     Lower.lower(MI, LoweredMI);
+     break;
+Index: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h
+===================================================================
+--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h
+@@ -146,6 +146,9 @@
+   // Perform a serialization operation.  (BCR 15,0 or BCR 14,0.)
+   SERIALIZE,
+ 
+  // Compiler barrier only; generate a no-op.
+  MEMBARRIER,
+
+   // Transaction begin.  The first operand is the chain, the second
+   // the TDB pointer, and the third the immediate control field.
+   // Returns chain and glue.
+@@ -479,6 +482,7 @@
+   SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
+   SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
+   SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
+   SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
+   SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
+   SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
+Index: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
+===================================================================
+--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
+@@ -216,6 +216,8 @@
+   setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);
+   setOperationAction(ISD::ATOMIC_CMP_SWAP,  MVT::i32, Custom);
+ 
+  setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
+
+   // z10 has instructions for signed but not unsigned FP conversion.
+   // Handle unsigned 32-bit types as signed 64-bit types.
+   if (!Subtarget.hasFPExtension()) {
+@@ -3118,6 +3120,25 @@
+   return Op;
+ }
+ 
+SDValue SystemZTargetLowering::lowerATOMIC_FENCE(SDValue Op,
+                                                 SelectionDAG &DAG) const {
+  SDLoc DL(Op);
+  AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
+    cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
+  SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
+    cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
+
+  // The only fence that needs an instruction is a sequentially-consistent
+  // cross-thread fence.
+  if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
+    return SDValue(DAG.getMachineNode(SystemZ::Serialize, DL, MVT::Other,
+                                      Op.getOperand(0)), 0);
+  }
+
+  // MEMBARRIER is a compiler barrier; it codegens to a no-op.
+  return DAG.getNode(SystemZISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
+}
+
+ // Op is an atomic load.  Lower it into a normal volatile load.
+ SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
+                                                 SelectionDAG &DAG) const {
+@@ -4444,6 +4465,8 @@
+   case ISD::CTTZ_ZERO_UNDEF:
+     return DAG.getNode(ISD::CTTZ, SDLoc(Op),
+                        Op.getValueType(), Op.getOperand(0));
+  case ISD::ATOMIC_FENCE:
+    return lowerATOMIC_FENCE(Op, DAG);
+   case ISD::ATOMIC_SWAP:
+     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_SWAPW);
+   case ISD::ATOMIC_STORE:
+@@ -4547,6 +4570,7 @@
+     OPCODE(SEARCH_STRING);
+     OPCODE(IPM);
+     OPCODE(SERIALIZE);
+    OPCODE(MEMBARRIER);
+     OPCODE(TBEGIN);
+     OPCODE(TBEGIN_NOFLOAT);
+     OPCODE(TEND);
+@@ -5307,6 +5331,7 @@
+ MachineBasicBlock *
+ SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
+                                           MachineBasicBlock *MBB) const {
+
+   MachineFunction &MF = *MBB->getParent();
+   const SystemZInstrInfo *TII =
+       static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
+Index: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
+===================================================================
+--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
+@@ -1231,6 +1231,10 @@
+ let hasSideEffects = 1 in
+ def Serialize : Alias<2, (outs), (ins), [(z_serialize)]>;
+ 
+// A pseudo instruction that serves as a compiler barrier.
+let hasSideEffects = 1 in
+def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>;
+
+ let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in {
+   def LAA   : LoadAndOpRSY<"laa",   0xEBF8, atomic_load_add_32, GR32>;
+   def LAAG  : LoadAndOpRSY<"laag",  0xEBE8, atomic_load_add_64, GR64>;
+Index: llvm/trunk/lib/Target/SystemZ/SystemZOperators.td
+===================================================================
+--- llvm/trunk/lib/Target/SystemZ/SystemZOperators.td
+++ llvm/trunk/lib/Target/SystemZ/SystemZOperators.td
+@@ -188,6 +188,8 @@
+ 
+ def z_serialize         : SDNode<"SystemZISD::SERIALIZE", SDTNone,
+                                  [SDNPHasChain, SDNPMayStore]>;
+def z_membarrier        : SDNode<"SystemZISD::MEMBARRIER", SDTNone,
+                                 [SDNPHasChain, SDNPSideEffect]>;
+ 
+ // Defined because the index is an i32 rather than a pointer.
+ def z_vector_insert     : SDNode<"ISD::INSERT_VECTOR_ELT",
+Index: llvm/trunk/test/CodeGen/SystemZ/atomic-fence-01.ll
+===================================================================
+--- llvm/trunk/test/CodeGen/SystemZ/atomic-fence-01.ll
+++ llvm/trunk/test/CodeGen/SystemZ/atomic-fence-01.ll
+@@ -0,0 +1,16 @@
+; Test (fast) serialization.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s --check-prefix=Z10
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196  | FileCheck %s --check-prefix=Z196
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s --check-prefix=ZEC12
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13   | FileCheck %s --check-prefix=Z13
+
+define void @test() {
+; Z10:   bcr 15, %r0
+; Z196:  bcr 14, %r0
+; ZEC12: bcr 14, %r0
+; Z13:   bcr 14, %r0
+  fence seq_cst
+  ret void
+}
+
+Index: llvm/trunk/test/CodeGen/SystemZ/atomic-fence-02.ll
+===================================================================
+--- llvm/trunk/test/CodeGen/SystemZ/atomic-fence-02.ll
+++ llvm/trunk/test/CodeGen/SystemZ/atomic-fence-02.ll
+@@ -0,0 +1,13 @@
+; Serialization is emitted only for fence seq_cst.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+define void @test() {
+; CHECK: #MEMBARRIER
+  fence acquire
+; CHECK: #MEMBARRIER
+  fence release
+; CHECK: #MEMBARRIER
+  fence acq_rel
+  ret void
+}
--- a/llvm-r294646.patch
+++ b/llvm-r294646.patch
@ -0,0 +1,13 @@
+Index: docs/CommandGuide/lit.rst
+===================================================================
+--- docs/CommandGuide/lit.rst	(revision 294645)
+++ docs/CommandGuide/lit.rst	(revision 294646)
+@@ -56,7 +56,7 @@
+  Search for :file:`{NAME}.cfg` and :file:`{NAME}.site.cfg` when searching for
+  test suites, instead of :file:`lit.cfg` and :file:`lit.site.cfg`.
+ 
+-.. option:: -D NAME, -D NAME=VALUE, --param NAME, --param NAME=VALUE
+.. option:: -D NAME[=VALUE], --param NAME[=VALUE]
+ 
+  Add a user defined parameter ``NAME`` with the given ``VALUE`` (or the empty
+  string if not given).  The meaning and use of these parameters is test suite
--- a/llvm.spec
+++ b/llvm.spec
@ -1,92 +1,57 @@
 # Components enabled if supported by target architecture:
-%define gold_arches %{ix86} x86_64 %{arm} aarch64 %{power64} s390x
-%ifarch %{gold_arches}
+%ifarch %ix86 x86_64
  %bcond_without gold
 %else
  %bcond_with gold
 %endif

-%bcond_with compat_build
-
-%global llvm_libdir %{_libdir}/%{name}
-%global build_llvm_libdir %{buildroot}%{llvm_libdir}
-#%%global rc_ver 6
-%global baserelease 1
-%global llvm_srcdir llvm-%{version}%{?rc_ver:rc%{rc_ver}}.src
-%global maj_ver 10
-%global min_ver 0
-%global patch_ver 0
-
-
-%if %{with compat_build}
-%global pkg_name llvm%{maj_ver}.%{min_ver}
-%global exec_suffix -%{maj_ver}.%{min_ver}
-%global install_prefix %{_libdir}/%{name}
-%global install_bindir %{install_prefix}/bin
-%global install_includedir %{install_prefix}/include
-%global install_libdir %{install_prefix}/lib
-
-%global pkg_bindir %{install_bindir}
-%global pkg_includedir %{_includedir}/%{name}
-%global pkg_libdir %{install_libdir}
-%else
-%global pkg_name llvm
-%global install_prefix /usr
-%global install_libdir %{_libdir}
-%global pkg_libdir %{install_libdir}
-%endif
-
-%global build_install_prefix %{buildroot}%{install_prefix}
-
-Name:		%{pkg_name}
-Version:	%{maj_ver}.%{min_ver}.%{patch_ver}
-Release:	%{baserelease}%{?rc_ver:.rc%{rc_ver}}%{?dist}
+Name:		llvm
+Version:	3.9.1
+Release:	5%{?dist}
 Summary:	The Low Level Virtual Machine

 License:	NCSA
 URL:		http://llvm.org
-%if 0%{?rc_ver:1}
-Source0:	https://prereleases.llvm.org/%{version}/rc%{rc_ver}/%{llvm_srcdir}.tar.xz
-Source3:	https://prereleases.llvm.org/%{version}/rc%{rc_ver}/%{llvm_srcdir}.tar.xz.sig
-%else
-Source0:	https://github.com/llvm/llvm-project/releases/download/llvmorg-%{version}/%{llvm_srcdir}.tar.xz
-Source3:	https://github.com/llvm/llvm-project/releases/download/llvmorg-%{version}/%{llvm_srcdir}.tar.xz.sig
-%endif
-%if %{without compat_build}
-Source1:	run-lit-tests
-Source2:	lit.fedora.cfg.py
-%endif
-Source4:	https://prereleases.llvm.org/%{version}/hans-gpg-key.asc
+Source0:	http://llvm.org/releases/%{version}/%{name}-%{version}.src.tar.xz

-Patch0:		0001-CMake-Split-static-library-exports-into-their-own-ex.patch
-Patch1:		0001-CMake-Split-test-binary-exports-into-their-own-expor.patch
+Source100:	llvm-config.h
+
+Patch1:		0001-This-code-block-breaks-the-docs-build-http-lab.llvm..patch
+Patch2:		0001-fix-docs-2.patch
+Patch3:		0001-fix-docs-3.patch
+Patch4:		0001-docs-fix-cmake-code-block-warning.patch
+# backport from upstream to fix lldb out of tree
+Patch5:		0001-cmake-Install-CheckAtomic.cmake-needed-by-lldb.patch
+# Upstream patch to fix doc build
+# http://llvm.org/viewvc/llvm-project?view=revision&revision=294646
+Patch6:		llvm-r294646.patch
+# This fix caused regressions
+Patch7:		0001-Revert-Merging-r280589.patch
+# https://reviews.llvm.org/D27609
+Patch8:		0001-Fix-R_AARCH64_MOVW_UABS_G3-relocation.patch
+# rhbz1435545
+Patch9:		0001-X86-Change-getHostCPUName-to-report-Intel-model-0x4e.patch
+
+# backports cribbed from https://github.com/rust-lang/llvm/
+Patch47:	rust-lang-llvm-pr47.patch
+Patch53:	rust-lang-llvm-pr53.patch
+Patch54:	rust-lang-llvm-pr54.patch
+Patch55:	rust-lang-llvm-pr55.patch
+Patch57:	rust-lang-llvm-pr57.patch
+Patch67:	rust-lang-llvm-pr67.patch

-BuildRequires:	gcc
-BuildRequires:	gcc-c++
 BuildRequires:	cmake
-BuildRequires:	ninja-build
 BuildRequires:	zlib-devel
-BuildRequires:	libffi-devel
+BuildRequires:  libffi-devel
 BuildRequires:	ncurses-devel
 BuildRequires:	python3-sphinx
-BuildRequires:	python3-recommonmark
-BuildRequires:	multilib-rpm-config
 %if %{with gold}
-BuildRequires:	binutils-devel
+BuildRequires:  binutils-devel
 %endif
-%ifarch %{valgrind_arches}
-# Enable extra functionality when run the LLVM JIT under valgrind.
-BuildRequires:	valgrind-devel
-%endif
-# LLVM's LineEditor library will use libedit if it is available.
-BuildRequires:	libedit-devel
-# We need python3-devel for pathfix.py.
-BuildRequires:	python3-devel
+BuildRequires:  libstdc++-static

 Requires:	%{name}-libs%{?_isa} = %{version}-%{release}

-Provides:	llvm(major) = %{maj_ver}
-
 %description
 LLVM is a compiler infrastructure designed for compile-time, link-time,
 runtime, and idle-time optimization of programs from arbitrary programming
@ -96,15 +61,8 @@ tools as well as libraries with equivalent functionality.
 %package devel
 Summary:	Libraries and header files for LLVM
 Requires:	%{name}%{?_isa} = %{version}-%{release}
-Requires:	%{name}-libs%{?_isa} = %{version}-%{release}
-# The installed LLVM cmake files will add -ledit to the linker flags for any
-# app that requires the libLLVMLineEditor, so we need to make sure
-# libedit-devel is available.
-Requires:	libedit-devel
-Requires(post):	%{_sbindir}/alternatives
-Requires(postun):	%{_sbindir}/alternatives
-
-Provides:	llvm-devel(major) = %{maj_ver}
+Requires(post): %{_sbindir}/alternatives
+Requires(postun): %{_sbindir}/alternatives

 %description devel
 This package contains library and header files needed to develop new native
@ -126,79 +84,59 @@ Shared libraries for the LLVM compiler infrastructure.

 %package static
 Summary:	LLVM static libraries
-Conflicts:	%{name}-devel < 8

 %description static
 Static libraries for the LLVM compiler infrastructure.

-%if %{without compat_build}
+%prep
+%setup -q -n %{name}-%{version}.src
+%patch1 -p1 -b .sphinx
+%patch2 -p1 -b .docs2
+%patch3 -p1 -b .docs3
+%patch4 -p1 -b .docs4
+%patch5 -p1 -b .lldbfix
+%patch6 -p0 -b .doc-lit
+%patch7 -p1 -b .amdfix
+%patch8 -p2 -b .arm64
+%patch47 -p1 -b .rust47
+%patch53 -p1 -b .rust53
+%patch54 -p1 -b .rust54
+%patch55 -p1 -b .rust55
+%patch57 -p1 -b .rust57
+%patch67 -p1 -b .rust67

-%package test
-Summary:	LLVM regression tests
-Requires:	%{name}%{?_isa} = %{version}-%{release}
-Requires:	%{name}-libs%{?_isa} = %{version}-%{release}
-Requires:	python3-lit
-# The regression tests need gold.
-Requires:	binutils
-# This is for llvm-config
-Requires:	%{name}-devel%{?_isa} = %{version}-%{release}
-# Bugpoint tests require gcc
-Requires:	gcc
-Requires:	findutils
+%ifarch armv7hl

-Provides:	llvm-test(major) = %{maj_ver}
-
-%description test
-LLVM regression tests.
-
-%package googletest
-Summary: LLVM's modified googletest sources
-
-%description googletest
-LLVM's modified googletest sources.
+# These tests are marked as XFAIL, but they still run and hang on ARM.
+for f in `grep -Rl 'XFAIL.\+arm' test/ExecutionEngine `; do  rm $f; done

 %endif

-%prep
-%autosetup -n %{llvm_srcdir} -p2
-
-pathfix.py -i %{__python3} -pn \
-	test/BugPoint/compile-custom.ll.py \
-	tools/opt-viewer/*.py
-
 %build
 mkdir -p _build
 cd _build

-%ifarch s390 %{arm} %ix86
+%ifarch s390
 # Decrease debuginfo verbosity to reduce memory consumption during final library linking
 %global optflags %(echo %{optflags} | sed 's/-g /-g1 /')
 %endif

 # force off shared libs as cmake macros turns it on.
-#
-# -DCMAKE_INSTALL_RPATH=";" is a workaround for llvm manually setting the
-# rpath of libraries and binaries.  llvm will skip the manual setting
-# if CAMKE_INSTALL_RPATH is set to a value, but cmake interprets this value
-# as nothing, so it sets the rpath to "" when installing.
-%cmake .. -G Ninja \
+%cmake .. \
 	-DBUILD_SHARED_LIBS:BOOL=OFF \
-	-DLLVM_PARALLEL_LINK_JOBS=1 \
 	-DCMAKE_BUILD_TYPE=RelWithDebInfo \
-	-DCMAKE_INSTALL_RPATH=";" \
-%ifarch s390 %{arm} %ix86
+	-DCMAKE_SHARED_LINKER_FLAGS="-Wl,-Bsymbolic -static-libstdc++" \
+%ifarch s390
 	-DCMAKE_C_FLAGS_RELWITHDEBINFO="%{optflags} -DNDEBUG" \
 	-DCMAKE_CXX_FLAGS_RELWITHDEBINFO="%{optflags} -DNDEBUG" \
 %endif
-%if %{without compat_build}
 %if 0%{?__isa_bits} == 64
 	-DLLVM_LIBDIR_SUFFIX=64 \
 %else
 	-DLLVM_LIBDIR_SUFFIX= \
-%endif
 %endif
 	\
-	-DLLVM_TARGETS_TO_BUILD=all \
+	-DLLVM_TARGETS_TO_BUILD="X86;AMDGPU;PowerPC;NVPTX;SystemZ;AArch64;ARM;Mips;BPF" \
 	-DLLVM_ENABLE_LIBCXX:BOOL=OFF \
 	-DLLVM_ENABLE_ZLIB:BOOL=ON \
 	-DLLVM_ENABLE_FFI:BOOL=ON \
@ -206,7 +144,6 @@ cd _build
 %if %{with gold}
 	-DLLVM_BINUTILS_INCDIR=%{_includedir} \
 %endif
-	-DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=AVR \
 	\
 	-DLLVM_BUILD_RUNTIME:BOOL=ON \
 	\
@ -220,20 +157,13 @@ cd _build
 	-DLLVM_BUILD_EXAMPLES:BOOL=OFF \
 	\
 	-DLLVM_INCLUDE_UTILS:BOOL=ON \
-%if %{with compat_build}
 	-DLLVM_INSTALL_UTILS:BOOL=OFF \
-%else
-	-DLLVM_INSTALL_UTILS:BOOL=ON \
-	-DLLVM_UTILS_INSTALL_DIR:PATH=%{_bindir} \
-	-DLLVM_TOOLS_INSTALL_DIR:PATH=bin \
-%endif
 	\
 	-DLLVM_INCLUDE_DOCS:BOOL=ON \
 	-DLLVM_BUILD_DOCS:BOOL=ON \
 	-DLLVM_ENABLE_SPHINX:BOOL=ON \
 	-DLLVM_ENABLE_DOXYGEN:BOOL=OFF \
 	\
-	-DLLVM_VERSION_SUFFIX='' \
 	-DLLVM_BUILD_LLVM_DYLIB:BOOL=ON \
 	-DLLVM_DYLIB_EXPORT_ALL:BOOL=ON \
 	-DLLVM_LINK_LLVM_DYLIB:BOOL=ON \
@ -241,617 +171,82 @@ cd _build
 	-DLLVM_INSTALL_TOOLCHAIN_ONLY:BOOL=OFF \
 	\
 	-DSPHINX_WARNINGS_AS_ERRORS=OFF \
-	-DLLVM_INSTALL_SPHINX_HTML_DIR=%{_pkgdocdir}/html \
 	-DSPHINX_EXECUTABLE=%{_bindir}/sphinx-build-3

-# Build libLLVM.so first.  This ensures that when libLLVM.so is linking, there
-# are no other compile jobs running.  This will help reduce OOM errors on the
-# builders without having to artificially limit the number of concurrent jobs.
-%ninja_build LLVM
-%ninja_build
+make %{?_smp_mflags}

 %install
-%ninja_install -C _build
-
-
-%if %{without compat_build}
-mkdir -p %{buildroot}/%{_bindir}
-mv %{buildroot}/%{_bindir}/llvm-config %{buildroot}/%{_bindir}/llvm-config-%{__isa_bits}
-
-# Fix some man pages
-ln -s llvm-config.1 %{buildroot}%{_mandir}/man1/llvm-config-%{__isa_bits}.1
-mv %{buildroot}%{_mandir}/man1/tblgen.1 %{buildroot}%{_mandir}/man1/llvm-tblgen.1
-
-# Install binaries needed for lit tests
-%global test_binaries llvm-isel-fuzzer llvm-opt-fuzzer
-
-for f in %{test_binaries}
-do
-    install -m 0755 ./_build/bin/$f %{buildroot}%{_bindir}
-done
-
-
-%multilib_fix_c_header --file %{_includedir}/llvm/Config/llvm-config.h
-
-# Install libraries needed for unittests
-%if 0%{?__isa_bits} == 64
-%global build_libdir _build/lib64
-%else
-%global build_libdir _build/lib
-%endif
-
-install %{build_libdir}/libLLVMTestingSupport.a %{buildroot}%{_libdir}
-
-%global install_srcdir %{buildroot}%{_datadir}/llvm/src
-%global lit_cfg test/%{_arch}.site.cfg.py
-%global lit_unit_cfg test/Unit/%{_arch}.site.cfg.py
-%global lit_fedora_cfg %{_datadir}/llvm/lit.fedora.cfg.py
-
-# Install gtest sources so clang can use them for gtest
-install -d %{install_srcdir}
-install -d %{install_srcdir}/utils/
-cp -R utils/unittest %{install_srcdir}/utils/
-
-# Generate lit config files.  Strip off the last line that initiates the
-# test run, so we can customize the configuration.
-head -n -1 _build/test/lit.site.cfg.py >> %{lit_cfg}
-head -n -1 _build/test/Unit/lit.site.cfg.py >> %{lit_unit_cfg}
-
-# Install custom fedora config file
-cp %{SOURCE2} %{buildroot}%{lit_fedora_cfg}
-
-# Patch lit config files to load custom fedora config:
-for f in %{lit_cfg} %{lit_unit_cfg}; do
-  echo "lit_config.load_config(config, '%{lit_fedora_cfg}')" >> $f
-done
-
-install -d %{buildroot}%{_libexecdir}/tests/llvm
-install -m 0755 %{SOURCE1} %{buildroot}%{_libexecdir}/tests/llvm
-
-# Install lit tests.  We need to put these in a tarball otherwise rpm will complain
-# about some of the test inputs having the wrong object file format.
-install -d %{buildroot}%{_datadir}/llvm/
-tar -czf %{install_srcdir}/test.tar.gz test/
-
-# Install the unit test binaries
-mkdir -p %{build_llvm_libdir}
-cp -R _build/unittests %{build_llvm_libdir}/
-rm -rf `find %{build_llvm_libdir} -iname 'cmake*'`
-
-# Install libraries used for testing
-install -m 0755 %{build_libdir}/BugpointPasses.so %{buildroot}%{_libdir}
-install -m 0755 %{build_libdir}/LLVMHello.so %{buildroot}%{_libdir}
-
-# Install test inputs for PDB tests
-echo "%{_datadir}/llvm/src/unittests/DebugInfo/PDB" > %{build_llvm_libdir}/unittests/DebugInfo/PDB/llvm.srcdir.txt
-mkdir -p %{buildroot}%{_datadir}/llvm/src/unittests/DebugInfo/PDB/
-cp -R unittests/DebugInfo/PDB/Inputs %{buildroot}%{_datadir}/llvm/src/unittests/DebugInfo/PDB/
-
-%else
-
-# Add version suffix to binaries
-mkdir -p %{buildroot}/%{_bindir}
-for f in %{buildroot}/%{install_bindir}/*; do
-  filename=`basename $f`
-  ln -s %{install_bindir}/$filename %{buildroot}/%{_bindir}/$filename%{exec_suffix}
-done
-
-# Move header files
-mkdir -p %{buildroot}/%{pkg_includedir}
-ln -s ../../../%{install_includedir}/llvm %{buildroot}/%{pkg_includedir}/llvm
-ln -s ../../../%{install_includedir}/llvm-c %{buildroot}/%{pkg_includedir}/llvm-c
-
-# Fix multi-lib
-mv %{buildroot}%{_bindir}/llvm-config{%{exec_suffix},%{exec_suffix}-%{__isa_bits}}
-%multilib_fix_c_header --file %{install_includedir}/llvm/Config/llvm-config.h
-
-# Create ld.so.conf.d entry
-mkdir -p %{buildroot}%{_sysconfdir}/ld.so.conf.d
-cat >> %{buildroot}%{_sysconfdir}/ld.so.conf.d/%{name}-%{_arch}.conf << EOF
-%{pkg_libdir}
-EOF
-
-# Add version suffix to man pages and move them to mandir.
-mkdir -p %{buildroot}/%{_mandir}/man1
-for f in `ls %{build_install_prefix}/share/man/man1/*`; do
-  filename=`basename $f | cut -f 1 -d '.'`
-  mv $f %{buildroot}%{_mandir}/man1/$filename%{exec_suffix}.1
-done
-
-# Remove opt-viewer, since this is just a compatibility package.
-rm -Rf %{build_install_prefix}/share/opt-viewer
-
-%endif
+cd _build
+make install DESTDIR=%{buildroot}

+# fix multi-lib
+mv -v %{buildroot}%{_bindir}/llvm-config{,-%{__isa_bits}}
+mv -v %{buildroot}%{_includedir}/llvm/Config/llvm-config{,-%{__isa_bits}}.h
+install -m 0644 %{SOURCE100} %{buildroot}%{_includedir}/llvm/Config/llvm-config.h

 %check
-# TODO: Fix test failures on arm
-ninja check-all -C _build || \
-%ifarch %{arm}
-  :
-%else
-  false
-%endif
+cd _build
+make check-all || :

-%ldconfig_scriptlets libs
-
-%if %{without compat_build}
+%post libs -p /sbin/ldconfig
+%postun libs -p /sbin/ldconfig

 %post devel
 %{_sbindir}/update-alternatives --install %{_bindir}/llvm-config llvm-config %{_bindir}/llvm-config-%{__isa_bits} %{__isa_bits}

 %postun devel
 if [ $1 -eq 0 ]; then
-  %{_sbindir}/update-alternatives --remove llvm-config %{_bindir}/llvm-config
+  %{_sbindir}/update-alternatives --remove llvm-config %{_bindir}/llvm-config-%{__isa_bits}
 fi

-%endif
-
 %files
-%exclude %{_mandir}/man1/llvm-config*
-%{_mandir}/man1/*
 %{_bindir}/*
-
-%if %{without compat_build}
+%{_mandir}/man1/*.1.*
 %exclude %{_bindir}/llvm-config-%{__isa_bits}
-%exclude %{_bindir}/not
-%exclude %{_bindir}/count
-%exclude %{_bindir}/yaml-bench
-%exclude %{_bindir}/lli-child-target
-%exclude %{_bindir}/llvm-isel-fuzzer
-%exclude %{_bindir}/llvm-opt-fuzzer
-%{_datadir}/opt-viewer
-%else
-%exclude %{pkg_bindir}/llvm-config
-%{pkg_bindir}
-%endif
+%exclude %{_mandir}/man1/llvm-config.1.*

 %files libs
-%{pkg_libdir}/libLLVM-%{maj_ver}.so
-%if %{without compat_build}
+%{_libdir}/BugpointPasses.so
+%{_libdir}/LLVMHello.so
 %if %{with gold}
 %{_libdir}/LLVMgold.so
 %endif
-%{_libdir}/libLLVM-%{maj_ver}.%{min_ver}*.so
-%{_libdir}/libLTO.so*
-%else
-%config(noreplace) %{_sysconfdir}/ld.so.conf.d/%{name}-%{_arch}.conf
-%if %{with gold}
-%{_libdir}/%{name}/lib/LLVMgold.so
-%endif
-%{pkg_libdir}/libLLVM-%{maj_ver}.%{min_ver}*.so
-%{pkg_libdir}/libLTO.so*
-%exclude %{pkg_libdir}/libLTO.so
-%endif
-%{pkg_libdir}/libRemarks.so*
+%{_libdir}/libLLVM-3.9*.so
+%{_libdir}/libLTO.so

 %files devel
-%if %{without compat_build}
 %{_bindir}/llvm-config-%{__isa_bits}
-%{_mandir}/man1/llvm-config*
+%{_mandir}/man1/llvm-config.1.*
 %{_includedir}/llvm
 %{_includedir}/llvm-c
 %{_libdir}/libLLVM.so
 %{_libdir}/cmake/llvm
-%exclude %{_libdir}/cmake/llvm/LLVMStaticExports.cmake
-%exclude %{_libdir}/cmake/llvm/LLVMTestExports.cmake
-%else
-%{_bindir}/llvm-config%{exec_suffix}-%{__isa_bits}
-%{pkg_bindir}/llvm-config
-%{_mandir}/man1/llvm-config%{exec_suffix}.1.gz
-%{install_includedir}/llvm
-%{install_includedir}/llvm-c
-%{pkg_includedir}/llvm
-%{pkg_includedir}/llvm-c
-%{pkg_libdir}/libLTO.so
-%{pkg_libdir}/libLLVM.so
-%{pkg_libdir}/cmake/llvm
-%endif

 %files doc
 %doc %{_pkgdocdir}/html

 %files static
-%if %{without compat_build}
 %{_libdir}/*.a
-%exclude %{_libdir}/libLLVMTestingSupport.a
-%{_libdir}/cmake/llvm/LLVMStaticExports.cmake
-%else
-%{_libdir}/%{name}/lib/*.a
-%endif
-
-%if %{without compat_build}
-
-%files test
-%{_libexecdir}/tests/llvm/
-%{llvm_libdir}/unittests/
-%{_datadir}/llvm/src/unittests
-%{_datadir}/llvm/src/test.tar.gz
-%{_datadir}/llvm/lit.fedora.cfg.py
-%{_bindir}/not
-%{_bindir}/count
-%{_bindir}/yaml-bench
-%{_bindir}/lli-child-target
-%{_bindir}/llvm-isel-fuzzer
-%{_bindir}/llvm-opt-fuzzer
-%{_libdir}/BugpointPasses.so
-%{_libdir}/LLVMHello.so
-%{_libdir}/cmake/llvm/LLVMTestExports.cmake
-
-%files googletest
-%{_datadir}/llvm/src/utils
-%{_libdir}/libLLVMTestingSupport.a
-
-%endif

 %changelog
-* Wed Mar 25 2020 sguelton@redhat.com - 10.0.0-1
- 10.0.0 final
+* Fri Aug 25 2017 Tom Stellard <tstellar@redhat.com> - 3.9.1-5
+- Backport r291084 (rhbz1435545)

-* Mon Mar 23 2020 sguelton@redhat.com - 10.0.0-0.6.rc6
- 10.0.0 rc6
+* Thu Aug 24 2017 tstellar@redhat.com - 3.9.1-4
+- Fix %postun step for -devel package (rhbz 1403539).

-* Thu Mar 19 2020 sguelton@redhat.com - 10.0.0-0.5.rc5
- 10.0.0 rc5
-
-* Sat Mar 14 2020 sguelton@redhat.com - 10.0.0-0.4.rc4
- 10.0.0 rc4
-
-* Thu Mar 05 2020 sguelton@redhat.com - 10.0.0-0.3.rc3
- 10.0.0 rc3
-
-* Fri Feb 28 2020 sguelton@redhat.com - 10.0.0-0.2.rc2
- Remove *_finite support, see rhbz#1803203
-
-* Fri Feb 14 2020 sguelton@redhat.com - 10.0.0-0.1.rc2
- 10.0.0 rc2
-
-* Fri Jan 31 2020 sguelton@redhat.com - 10.0.0-0.1.rc1
- 10.0.0 rc1
-
-* Wed Jan 29 2020 Fedora Release Engineering <releng@fedoraproject.org> - 9.0.1-5
- Rebuilt for https://fedoraproject.org/wiki/Fedora_32_Mass_Rebuild
-
-* Tue Jan 21 2020 Tom Stellard <tstellar@redhat.com> - 9.0.1-4
- Rebuild after previous build failed to strip binaries
-
-* Fri Jan 17 2020 Tom Stellard <tstellar@redhat.com> - 9.0.1-3
- Add explicit Requires from sub-packages to llvm-libs
-
-* Fri Jan 10 2020 Tom Stellard <tstellar@redhat.com> - 9.0.1-2
- Fix crash with kernel bpf self-tests
-
-* Thu Dec 19 2019 tstellar@redhat.com - 9.0.1-1
- 9.0.1 Release
-
-* Mon Nov 25 2019 sguelton@redhat.com - 9.0.0-4
- Activate AVR on all architectures
-
-* Mon Sep 30 2019 Tom Stellard <tstellar@redhat.com> - 9.0.0-3
- Build libLLVM.so first to avoid OOM errors
-
-* Fri Sep 27 2019 Tom Stellard <tstellar@redhat.com> - 9.0.0-2
- Remove unneeded BuildRequires: libstdc++-static
-
-* Thu Sep 19 2019 sguelton@redhat.com - 9.0.0-1
- 9.0.0 Release
-
-* Wed Sep 18 2019 sguelton@redhat.com - 9.0.0-0.5.rc3
- Support avr target, see rhbz#1718492
-
-* Tue Sep 10 2019 Tom Stellard <tstellar@redhat.com> - 9.0.0-0.4.rc3
- Split out test executables into their own export file
-
-* Fri Sep 06 2019 Tom Stellard <tstellar@redhat.com> - 9.0.0-0.3.rc3
- Fix patch for splitting out static library exports
-
-* Fri Aug 30 2019 Tom Stellard <tstellar@redhat.com> - 9.0.0-0.2.rc3
- 9.0.0-rc3 Release
-
-* Thu Aug 01 2019 Tom Stellard <tstellar@redhat.com> - 9.0.0-0.1.rc2
- 9.0.0-rc2 Release
-
-* Tue Jul 30 2019 Tom Stellard <tstellar@redhat.com> - 8.0.0-9
- Sync with llvm8.0 spec file
-
-* Thu Jul 25 2019 Fedora Release Engineering <releng@fedoraproject.org> - 8.0.0-8.1
- Rebuilt for https://fedoraproject.org/wiki/Fedora_31_Mass_Rebuild
-
-* Wed Jul 17 2019 Tom Stellard <tstellar@redhat.com> - 8.0.0-8
- Add provides for the major version of sub-packages
-
-* Fri May 17 2019 sguelton@redhat.com - 8.0.0-7
- Fix conflicts between llvm-static = 8 and llvm-dev < 8 around LLVMStaticExports.cmake
-
-* Wed Apr 24 2019 Tom Stellard <tstellar@redhat.com> - 8.0.0-6
- Make sure we aren't passing -g on s390x
-
-* Sat Mar 30 2019 Tom Stellard <tstellar@redhat.com> - 8.0.0-5
- Enable build rpath while keeping install rpath disabled
-
-* Wed Mar 27 2019 Tom Stellard <tstellar@redhat.com> - 8.0.0-4
- Backport r351577 from trunk to fix ninja check failures
-
-* Tue Mar 26 2019 Tom Stellard <tstellar@redhat.com> - 8.0.0-3
- Fix ninja check
-
-* Fri Mar 22 2019 Tom Stellard <tstellar@redhat.com> - 8.0.0-2
- llvm-test fixes
-
-* Wed Mar 20 2019 sguelton@redhat.com - 8.0.0-1
- 8.0.0 final
-
-* Fri Mar 15 2019 sguelton@redhat.com - 8.0.0-0.6.rc4
- Activate all backends (rhbz#1689031)
-
-* Tue Mar 12 2019 sguelton@redhat.com - 8.0.0-0.5.rc4
- 8.0.0 Release candidate 4
-
-* Mon Mar 4 2019 sguelton@redhat.com - 8.0.0-0.4.rc3
- Move some binaries to -test package, cleanup specfile
-
-* Mon Mar 4 2019 sguelton@redhat.com - 8.0.0-0.3.rc3
- 8.0.0 Release candidate 3
-
-* Fri Feb 22 2019 sguelton@redhat.com - 8.0.0-0.2.rc2
- 8.0.0 Release candidate 2
-
-* Sat Feb 9 2019 sguelton@redhat.com - 8.0.0-0.1.rc1
- 8.0.0 Release candidate 1
-
-* Fri Feb 01 2019 Fedora Release Engineering <releng@fedoraproject.org> - 7.0.1-2.1
- Rebuilt for https://fedoraproject.org/wiki/Fedora_30_Mass_Rebuild
-
-* Mon Jan 21 2019 Josh Stone <jistone@redhat.com> - 7.0.1-2
- Fix discriminators in metadata, rhbz#1668033
-
-* Mon Dec 17 2018 sguelton@redhat.com - 7.0.1-1
- 7.0.1 release
-
-* Tue Dec 04 2018 sguelton@redhat.com - 7.0.0-5
- Ensure rpmlint passes on specfile
-
-* Sat Nov 17 2018 Tom Stellard <tstellar@redhat.com> - 7.0.0-4
- Install testing libraries for unittests
-
-* Sat Oct 27 2018 Tom Stellard <tstellar@redhat.com> - 7.0.0-3
- Fix running unittests as not-root user
-
-* Thu Sep 27 2018 Tom Stellard <tstellar@redhat.com> - 7.0.0-2
- Fixes for llvm-test package:
- Add some missing Requires
- Add --threads option to run-lit-tests script
- Set PATH so lit can find tools like count, not, etc.
- Don't hardcode tools directory to /usr/lib64/llvm
- Fix typo in yaml-bench define
- Only print information about failing tests
-
-* Fri Sep 21 2018 Tom Stellard <tstellar@redhat.com> - 7.0.0-1
- 7.0.0 Release
-
-* Thu Sep 13 2018 Tom Stellard <tstellar@redhat.com> - 7.0.0-0.15.rc3
- Disable rpath on install LLVM and related sub-projects
-
-* Wed Sep 12 2018 Tom Stellard <tstellar@redhat.com> - 7.0.0-0.14.rc3
- Remove rpath from executables and libraries
-
-* Tue Sep 11 2018 Tom Stellard <tstellar@redhat.com> - 7.0.0-0.13.rc3
- Re-enable arm and aarch64 targets on x86_64
-
-* Mon Sep 10 2018 Tom Stellard <tstellar@redhat.com> - 7.0.0-0.12.rc3
- 7.0.0-rc3 Release
-
-* Fri Sep 07 2018 Tom Stellard <tstellar@redhat.com> - 7.0.0-0.11.rc2
- Use python3 shebang for opt-viewewr scripts
-
-* Thu Aug 30 2018 Tom Stellard <tstellar@redhat.com> - 7.0.0-0.10.rc2
- Drop all uses of python2 from lit tests
-
-* Thu Aug 30 2018 Tom Stellard <tstellar@redhat.com> - 7.0.0-0.9.rc2
- Build the gold plugin on all supported architectures
-
-* Wed Aug 29 2018 Kevin Fenzi <kevin@scrye.com> - 7.0.0-0.8.rc2
- Re-enable debuginfo to avoid 25x size increase.
-
-* Tue Aug 28 2018 Tom Stellard <tstellar@redhat.com> - 7.0.0-0.7.rc2
- 7.0.0-rc2 Release
-
-* Tue Aug 28 2018 Tom Stellard <tstellar@redhat.com> - 7.0.0-0.6.rc1
- Guard valgrind usage with valgrind_arches macro
-
-* Thu Aug 23 2018 Tom Stellard <tstellar@redhat.com> - 7.0.0-0.5.rc1
- Package lit tests and googletest sources.
-
-* Mon Aug 20 2018 Tom Stellard <tstellar@redhat.com> - 7.0.0-0.4.rc1
- Re-enable AMDGPU target on ARM rhbz#1618922
-
-* Mon Aug 13 2018 Tom Stellard <tstellar@redhat.com> - 7.0.0-0.3.rc1
- Drop references to TestPlugin.so from cmake files
-
-* Fri Aug 10 2018 Tom Stellard <tstellar@redhat.com> - 7.0.0-0.2.rc1
- Fixes for lit tests
-
-* Fri Aug 10 2018 Tom Stellard <tstellar@redhat.com> - 7.0.0-0.1.rc1
- 7.0.0-rc1 Release
- Reduce number of enabled targets on all arches.
- Drop s390 detection patch, LLVM does not support s390 codegen.
-
-* Mon Aug 06 2018 Tom Stellard <tstellar@redhat.com> - 6.0.1-6
- Backport some fixes needed by mesa and rust
-
-* Thu Jul 26 2018 Tom Stellard <tstellar@redhat.com> - 6.0.1-5
- Move libLLVM-6.0.so to llvm6.0-libs.
-
-* Mon Jul 23 2018 Tom Stellard <tstellar@redhat.com> - 6.0.1-4
- Rebuild because debuginfo stripping failed with the previous build
-
-* Fri Jul 13 2018 Tom Stellard <tstellar@redhat.com> - 6.0.1-3
- Sync specfile with llvm6.0 package
-
-* Fri Jul 13 2018 Fedora Release Engineering <releng@fedoraproject.org> - 6.0.1-2
- Rebuilt for https://fedoraproject.org/wiki/Fedora_29_Mass_Rebuild
-
-* Mon Jun 25 2018 Tom Stellard <tstellar@redhat.com> - 6.0.1-1
- 6.0.1 Release
-
-* Thu Jun 07 2018 Tom Stellard <tstellar@redhat.com> - 6.0.1-0.4.rc2
- 6.0.1-rc2
-
-* Wed Jun 06 2018 Tom Stellard <tstellar@redhat.com> - 6.0.1-0.3.rc1
- Re-enable all targets to avoid breaking the ABI.
-
-* Mon Jun 04 2018 Tom Stellard <tstellar@redhat.com> - 6.0.1-0.2.rc1
- Reduce the number of enabled targets based on the architecture
-
-* Thu May 10 2018 Tom Stellard <tstellar@redhat.com> - 6.0.1-0.1.rc1
- 6.0.1 rc1
-
-* Tue Mar 27 2018 Tom Stellard <tstellar@redhat.com> - 6.0.0-11
- Re-enable arm tests that used to hang
-
-* Thu Mar 22 2018 Tom Stellard <tstellar@redhat.com> - 6.0.0-10
- Fix testcase in backported patch
-
-* Tue Mar 20 2018 Tom Stellard <tstellar@redhat.com> - 6.0.0-9
- Prevent external projects from linking against both static and shared
-  libraries.  rhbz#1558657
-
-* Mon Mar 19 2018 Tom Stellard <tstellar@redhat.com> - 6.0.0-8
- Backport r327651 from trunk rhbz#1554349
-
-* Fri Mar 16 2018 Tom Stellard <tstellar@redhat.com> - 6.0.0-7
- Filter out cxxflags and cflags from llvm-config that aren't supported by clang
- rhbz#1556980
-
-* Wed Mar 14 2018 Tom Stellard <tstellar@redhat.com> - 6.0.0-6
- Enable symbol versioning in libLLVM.so
-
-* Wed Mar 14 2018 Tom Stellard <tstellar@redhat.com> - 6.0.0-5
- Stop statically linking libstdc++.  This is no longer required by Steam
-  client, but the steam installer still needs a work-around which should
-  be handled in the steam package.
-* Wed Mar 14 2018 Tom Stellard <tstellar@redhat.com> - 6.0.0-4
- s/make check/ninja check/
-
-* Fri Mar 09 2018 Tom Stellard <tstellar@redhat.com> - 6.0.0-3
- Backport fix for compile time regression on rust rhbz#1552915
-
-* Thu Mar 08 2018 Tom Stellard <tstellar@redhat.com> - 6.0.0-2
- Build with Ninja: This reduces RPM build time on a 6-core x86_64 builder
-  from 82 min to 52 min.
-
-* Thu Mar 08 2018 Tom Stellard <tstellar@redhat.com> - 6.0.0-1
- 6.0.0 Release
-
-* Thu Mar 08 2018 Tom Stellard <tstellar@redhat.com> - 6.0.0-0.5.rc2
- Reduce debuginfo size on i686 to avoid OOM errors during linking
-
-* Fri Feb 09 2018 Tom Stellard <tstellar@redhat.com> - 6.0.0-0.4.rc2
- 6.0.1 rc2
-
-* Fri Feb 09 2018 Igor Gnatenko <ignatenkobrain@fedoraproject.org> - 6.0.0-0.3.rc1
- Escape macros in %%changelog
-
-* Thu Feb 08 2018 Fedora Release Engineering <releng@fedoraproject.org> - 6.0.0-0.2.rc1
- Rebuilt for https://fedoraproject.org/wiki/Fedora_28_Mass_Rebuild
-
-* Fri Jan 19 2018 Tom Stellard <tstellar@redhat.com> - 6.0.0-0.1.rc1
- 6.0.1 rc1
-
-* Tue Dec 19 2017 Tom Stellard <tstellar@redhat.com> - 5.0.1-1
- 5.0.1 Release
-
-* Mon Nov 20 2017 Tom Stellard <tstellar@redhat.com> - 5.0.0-5
- Backport debuginfo fix for rust
-
-* Fri Nov 03 2017 Tom Stellard <tstellar@redhat.com> - 5.0.0-4
- Reduce debuginfo size for ARM
-
-* Tue Oct 10 2017 Tom Stellard <tstellar@redhat.com> - 5.0.0-2
- Reduce memory usage on ARM by disabling debuginfo and some non-ARM targets.
-
-* Mon Sep 25 2017 Tom Stellard <tstellar@redhat.com> - 5.0.0-1
- 5.0.0 Release
-
-* Mon Sep 18 2017 Tom Stellard <tstellar@redhat.com> - 4.0.1-6
- Add Requires: libedit-devel for llvm-devel
-
-* Fri Sep 08 2017 Tom Stellard <tstellar@redhat.com> - 4.0.1-5
- Enable libedit backend for LineEditor API
-
-* Fri Aug 25 2017 Tom Stellard <tstellar@redhat.com> - 4.0.1-4
- Enable extra functionality when run the LLVM JIT under valgrind.
-
-* Thu Aug 03 2017 Fedora Release Engineering <releng@fedoraproject.org> - 4.0.1-3
- Rebuilt for https://fedoraproject.org/wiki/Fedora_27_Binutils_Mass_Rebuild
-
-* Wed Jul 26 2017 Fedora Release Engineering <releng@fedoraproject.org> - 4.0.1-2
- Rebuilt for https://fedoraproject.org/wiki/Fedora_27_Mass_Rebuild
-
-* Wed Jun 21 2017 Tom Stellard <tstellar@redhat.com> - 4.0.1-1
- 4.0.1 Release
-
-* Thu Jun 15 2017 Tom Stellard <tstellar@redhat.com> - 4.0.0-6
- Install llvm utils
-
-* Thu Jun 08 2017 Tom Stellard <tstellar@redhat.com> - 4.0.0-5
- Fix docs-llvm-man target
-
-* Mon May 01 2017 Tom Stellard <tstellar@redhat.com> - 4.0.0-4
- Make cmake files no longer depend on static libs (rhbz 1388200)
-
-* Tue Apr 18 2017 Josh Stone <jistone@redhat.com> - 4.0.0-3
+* Tue Apr 18 2017 Josh Stone <jistone@redhat.com> - 3.9.1-3
 - Fix computeKnownBits for ARMISD::CMOV (rust-lang/llvm#67)

-* Mon Apr 03 2017 Tom Stellard <tstellar@redhat.com> - 4.0.0-2
- Simplify spec with rpm macros.
-
-* Thu Mar 23 2017 Tom Stellard <tstellar@redhat.com> - 4.0.0-1
- LLVM 4.0.0 Final Release
-
-* Wed Mar 22 2017 tstellar@redhat.com - 3.9.1-6
- Fix %%postun sep for -devel package.
-
-* Mon Mar 13 2017 Tom Stellard <tstellar@redhat.com> - 3.9.1-5
+* Fri Mar 17 2017 Peter Robinson <pbrobinson@fedoraproject.org> 3.9.1-2
+- Fix missing mask on relocation for aarch64 (rhbz 1429050)
 - Disable failing tests on ARM.

-* Sun Mar 12 2017 Peter Robinson <pbrobinson@fedoraproject.org> 3.9.1-4
- Fix missing mask on relocation for aarch64 (rhbz 1429050)
+* Wed Mar 01 2017 Dave Airlie <airlied@redhat.com> - 3.9.1-1
+- llvm 3.9.1 (master merge)

-* Wed Mar 01 2017 Dave Airlie <airlied@redhat.com> - 3.9.1-3
- revert upstream radeonsi breaking change.
-
-* Thu Feb 23 2017 Josh Stone <jistone@redhat.com> - 3.9.1-2
- disable sphinx warnings-as-errors
-
-* Fri Feb 10 2017 Orion Poplawski <orion@cora.nwra.com> - 3.9.1-1
- llvm 3.9.1
-
-* Fri Feb 10 2017 Fedora Release Engineering <releng@fedoraproject.org> - 3.9.0-8
- Rebuilt for https://fedoraproject.org/wiki/Fedora_26_Mass_Rebuild
-
-* Tue Nov 29 2016 Josh Stone <jistone@redhat.com> - 3.9.0-7
- Apply backports from rust-lang/llvm#55, #57
-
-* Tue Nov 01 2016 Dave Airlie <airlied@gmail.com - 3.9.0-6
- rebuild for new arches
-
-* Wed Oct 26 2016 Dave Airlie <airlied@redhat.com> - 3.9.0-5
- apply the patch from -4
-
-* Wed Oct 26 2016 Dave Airlie <airlied@redhat.com> - 3.9.0-4
- add fix for lldb out-of-tree build
-
-* Mon Oct 17 2016 Josh Stone <jistone@redhat.com> - 3.9.0-3
- Apply backports from rust-lang/llvm#47, #48, #53, #54
-
-* Sat Oct 15 2016 Josh Stone <jistone@redhat.com> - 3.9.0-2
- Apply an InstCombine backport via rust-lang/llvm#51
-
-* Wed Sep 07 2016 Dave Airlie <airlied@redhat.com> - 3.9.0-1
- llvm 3.9.0
- upstream moved where cmake files are packaged.
- upstream dropped CppBackend
+* Sat Jan 07 2017 Josh Stone <jistone@redhat.com> - 3.8.1-2
+- Support s390x atomic fence

 * Wed Jul 13 2016 Adam Jackson <ajax@redhat.com> - 3.8.1-1
 - llvm 3.8.1
--- a/pr12586.patch
+++ b/pr12586.patch
@ -0,0 +1,13 @@
+diff --git a/tools/clang/lib/Driver/Tools.cpp b/tools/clang/lib/Driver/Tools.cpp
+index 29713ed..0d23694 100644
+--- a/tools/clang/lib/Driver/Tools.cpp
+++ b/tools/clang/lib/Driver/Tools.cpp
+@@ -747,7 +747,7 @@ static StringRef getARMFloatABI(const Driver &D,
+         FloatABI = "hard";
+         break;
+       case llvm::Triple::GNUEABI:
+-        FloatABI = "softfp";
+        FloatABI = Triple.getVendorName() == "hardfloat" ? "hard" : "softfp";
+         break;
+       case llvm::Triple::EABI:
+         // EABI is always AAPCS, and if it was not marked 'hard', it's softfp
--- a/58
+++ b/58
@ -1,58 +0,0 @@
-#!/bin/bash
-
-usage() {
-    echo "usage: `basename $0` [OPTIONS]"
-    echo "  --threads NUM         The number of threads to use for running tests."
-    echo "  --multilib-arch ARCH  Use this option to test 32-bit libs/binaries on"
-    echo "                        64-bit hosts."
-}
-
-threads_arg=''
-
-while [ $# -gt 0 ]; do
-    case $1 in
-        --threads)
-            shift
-            threads_arg="--threads $1"
-            ;;
-	--multilib-arch)
-            shift
-	    ARCH=$1
-	    ;;
-        * )
-            echo "unknown option: $1"
-            echo ""
-            usage
-            exit 1
-            ;;
-    esac
-    shift
-done
-
-set -xe
-
-if [ -z "$ARCH" ]; then
-    ARCH=`rpm --eval '%_arch'`
-fi
-
-case $ARCH in
-    arm)
-	;&
-    i686)
-        LIB_DIR="/usr/lib/"
-        ;;
-    *)
-        LIB_DIR="/usr/lib64/"
-        ;;
-esac
-
-cd $(mktemp -d)
-ln -s /usr/include include
-tar -xzf /usr/share/llvm/src/test.tar.gz
-ln -s $ARCH.site.cfg.py test/lit.site.cfg.py
-ln -s $ARCH.site.cfg.py test/Unit/lit.site.cfg.py
-lit -v -s $threads_arg test \
-	-Dllvm_obj_root=`pwd` \
-	-Dllvm_test_root=`pwd`/test \
-	-Dllvm_unittest_bindir=$LIB_DIR/llvm \
-	-Dllvm_shlib_dir=$LIB_DIR
--- a/rust-lang-llvm-pr47.patch
+++ b/rust-lang-llvm-pr47.patch
@ -0,0 +1,272 @@
+From ae32815f9281a5a8d48014e180901fcdb658285a Mon Sep 17 00:00:00 2001
+From: David Majnemer <david.majnemer@gmail.com>
+Date: Sun, 7 Aug 2016 07:58:00 +0000
+Subject: [rust-lang/llvm#47 1/4] [InstCombine] Infer inbounds on geps of
+ allocas
+
+git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277950 91177308-0d34-0410-b5e6-96231b3b80d8
+---
+ lib/Transforms/InstCombine/InstructionCombining.cpp | 19 +++++++++++++++++++
+ test/Transforms/InstCombine/getelementptr.ll        |  6 +++---
+ 2 files changed, 22 insertions(+), 3 deletions(-)
+
+diff --git a/lib/Transforms/InstCombine/InstructionCombining.cpp b/lib/Transforms/InstCombine/InstructionCombining.cpp
+index 377ccb9c37f7..31b5ad6ae8af 100644
+--- a/lib/Transforms/InstCombine/InstructionCombining.cpp
+++ b/lib/Transforms/InstCombine/InstructionCombining.cpp
+@@ -1898,6 +1898,25 @@ Instruction *InstCombiner::visitGetElementPtrInst(GetElementPtrInst &GEP) {
+     }
+   }
+ 
+  if (!GEP.isInBounds()) {
+    unsigned PtrWidth =
+        DL.getPointerSizeInBits(PtrOp->getType()->getPointerAddressSpace());
+    APInt BasePtrOffset(PtrWidth, 0);
+    Value *UnderlyingPtrOp =
+            PtrOp->stripAndAccumulateInBoundsConstantOffsets(DL,
+                                                             BasePtrOffset);
+    if (auto *AI = dyn_cast<AllocaInst>(UnderlyingPtrOp)) {
+      if (GEP.accumulateConstantOffset(DL, BasePtrOffset) &&
+          BasePtrOffset.isNonNegative()) {
+        APInt AllocSize(PtrWidth, DL.getTypeAllocSize(AI->getAllocatedType()));
+        if (BasePtrOffset.ule(AllocSize)) {
+          return GetElementPtrInst::CreateInBounds(
+              PtrOp, makeArrayRef(Ops).slice(1), GEP.getName());
+        }
+      }
+    }
+  }
+
+   return nullptr;
+ }
+ 
+diff --git a/test/Transforms/InstCombine/getelementptr.ll b/test/Transforms/InstCombine/getelementptr.ll
+index 7446734e210c..14abd84fd18e 100644
+--- a/test/Transforms/InstCombine/getelementptr.ll
+++ b/test/Transforms/InstCombine/getelementptr.ll
+@@ -366,7 +366,7 @@ define i32 @test21() {
+         %rval = load i32, i32* %pbobel
+         ret i32 %rval
+ ; CHECK-LABEL: @test21(
+-; CHECK: getelementptr %intstruct, %intstruct* %pbob1, i64 0, i32 0
+; CHECK: getelementptr inbounds %intstruct, %intstruct* %pbob1, i64 0, i32 0
+ }
+ 
+ 
+@@ -540,8 +540,8 @@ define i8* @test32(i8* %v) {
+ 	%G = load i8*, i8** %F
+ 	ret i8* %G
+ ; CHECK-LABEL: @test32(
+-; CHECK: %D = getelementptr [4 x i8*], [4 x i8*]* %A, i64 0, i64 1
+-; CHECK: %F = getelementptr [4 x i8*], [4 x i8*]* %A, i64 0, i64 2
+; CHECK: %D = getelementptr inbounds [4 x i8*], [4 x i8*]* %A, i64 0, i64 1
+; CHECK: %F = getelementptr inbounds [4 x i8*], [4 x i8*]* %A, i64 0, i64 2
+ }
+ 
+ ; PR3290
+-- 
+2.7.4
+
+From d31c987130ff1bf9cea9a287195ecceda91c37d1 Mon Sep 17 00:00:00 2001
+From: David Majnemer <david.majnemer@gmail.com>
+Date: Sun, 7 Aug 2016 07:58:10 +0000
+Subject: [rust-lang/llvm#47 2/4] [InstSimplify] Try hard to simplify pointer
+ comparisons
+
+Simplify ptrtoint comparisons involving operands with different source
+types.
+
+git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277951 91177308-0d34-0410-b5e6-96231b3b80d8
+---
+ lib/Analysis/InstructionSimplify.cpp    | 10 ++++++++++
+ test/Transforms/InstSimplify/compare.ll | 13 +++++++++++++
+ 2 files changed, 23 insertions(+)
+
+diff --git a/lib/Analysis/InstructionSimplify.cpp b/lib/Analysis/InstructionSimplify.cpp
+index 7c6edbfca270..8b70d89d62cb 100644
+--- a/lib/Analysis/InstructionSimplify.cpp
+++ b/lib/Analysis/InstructionSimplify.cpp
+@@ -3092,6 +3092,16 @@ static Value *SimplifyICmpInst(unsigned Predicate, Value *LHS, Value *RHS,
+   if (LHS->getType()->isPointerTy())
+     if (auto *C = computePointerICmp(Q.DL, Q.TLI, Q.DT, Pred, Q.CxtI, LHS, RHS))
+       return C;
+  if (auto *CLHS = dyn_cast<PtrToIntOperator>(LHS))
+    if (auto *CRHS = dyn_cast<PtrToIntOperator>(RHS))
+      if (Q.DL.getTypeSizeInBits(CLHS->getPointerOperandType()) ==
+              Q.DL.getTypeSizeInBits(CLHS->getType()) &&
+          Q.DL.getTypeSizeInBits(CRHS->getPointerOperandType()) ==
+              Q.DL.getTypeSizeInBits(CRHS->getType()))
+        if (auto *C = computePointerICmp(Q.DL, Q.TLI, Q.DT, Pred, Q.CxtI,
+                                         CLHS->getPointerOperand(),
+                                         CRHS->getPointerOperand()))
+          return C;
+ 
+   if (GetElementPtrInst *GLHS = dyn_cast<GetElementPtrInst>(LHS)) {
+     if (GEPOperator *GRHS = dyn_cast<GEPOperator>(RHS)) {
+diff --git a/test/Transforms/InstSimplify/compare.ll b/test/Transforms/InstSimplify/compare.ll
+index 9d6fd74ae56f..3e7316ec6b48 100644
+--- a/test/Transforms/InstSimplify/compare.ll
+++ b/test/Transforms/InstSimplify/compare.ll
+@@ -205,6 +205,19 @@ define i1 @gep16(i8* %ptr, i32 %a) {
+ ; CHECK-NEXT: ret i1 false
+ }
+ 
+define i1 @gep17() {
+; CHECK-LABEL: @gep17(
+  %alloca = alloca i32, align 4
+  %bc = bitcast i32* %alloca to [4 x i8]*
+  %gep1 = getelementptr inbounds i32, i32* %alloca, i32 1
+  %pti1 = ptrtoint i32* %gep1 to i32
+  %gep2 = getelementptr inbounds [4 x i8], [4 x i8]* %bc, i32 0, i32 1
+  %pti2 = ptrtoint i8* %gep2 to i32
+  %cmp = icmp ugt i32 %pti1, %pti2
+  ret i1 %cmp
+; CHECK-NEXT: ret i1 true
+}
+
+ define i1 @zext(i32 %x) {
+ ; CHECK-LABEL: @zext(
+   %e1 = zext i32 %x to i64
+-- 
+2.7.4
+
+From bd3e05cb1f5293635edff14fcf23cfc73985c977 Mon Sep 17 00:00:00 2001
+From: David Majnemer <david.majnemer@gmail.com>
+Date: Sun, 7 Aug 2016 07:58:12 +0000
+Subject: [rust-lang/llvm#47 3/4] [InstSimplify] Fold gep (gep V, C), (sub 0,
+ V) to C
+
+git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277952 91177308-0d34-0410-b5e6-96231b3b80d8
+---
+ lib/Analysis/InstructionSimplify.cpp    | 20 ++++++++++++++++++++
+ test/Transforms/InstSimplify/compare.ll | 13 +++++++++++++
+ 2 files changed, 33 insertions(+)
+
+diff --git a/lib/Analysis/InstructionSimplify.cpp b/lib/Analysis/InstructionSimplify.cpp
+index 8b70d89d62cb..9d2a47957125 100644
+--- a/lib/Analysis/InstructionSimplify.cpp
+++ b/lib/Analysis/InstructionSimplify.cpp
+@@ -3597,6 +3597,26 @@ static Value *SimplifyGEPInst(Type *SrcTy, ArrayRef<Value *> Ops,
+     }
+   }
+ 
+  // gep (gep V, C), (sub 0, V) -> C
+  if (Q.DL.getTypeAllocSize(LastType) == 1 &&
+      all_of(Ops.slice(1).drop_back(1),
+             [](Value *Idx) { return match(Idx, m_Zero()); })) {
+    unsigned PtrWidth =
+        Q.DL.getPointerSizeInBits(Ops[0]->getType()->getPointerAddressSpace());
+    if (Q.DL.getTypeSizeInBits(Ops.back()->getType()) == PtrWidth) {
+      APInt BasePtrOffset(PtrWidth, 0);
+      Value *StrippedBasePtr =
+          Ops[0]->stripAndAccumulateInBoundsConstantOffsets(Q.DL,
+                                                            BasePtrOffset);
+
+      if (match(Ops.back(),
+                m_Sub(m_Zero(), m_PtrToInt(m_Specific(StrippedBasePtr))))) {
+        auto *CI = ConstantInt::get(GEPTy->getContext(), BasePtrOffset);
+        return ConstantExpr::getIntToPtr(CI, GEPTy);
+      }
+    }
+  }
+
+   // Check to see if this is constant foldable.
+   for (unsigned i = 0, e = Ops.size(); i != e; ++i)
+     if (!isa<Constant>(Ops[i]))
+diff --git a/test/Transforms/InstSimplify/compare.ll b/test/Transforms/InstSimplify/compare.ll
+index 3e7316ec6b48..addb63c57222 100644
+--- a/test/Transforms/InstSimplify/compare.ll
+++ b/test/Transforms/InstSimplify/compare.ll
+@@ -218,6 +218,19 @@ define i1 @gep17() {
+ ; CHECK-NEXT: ret i1 true
+ }
+ 
+define i32 @gep18() {
+; CHECK-LABEL: @gep18(
+  %alloca = alloca i32, align 4                                     ; alloca + 0
+  %gep = getelementptr inbounds i32, i32* %alloca, i32 1            ; alloca + 4
+  %bc = bitcast i32* %gep to [4 x i8]*                              ; alloca + 4
+  %pti = ptrtoint i32* %alloca to i32                               ; alloca
+  %sub = sub i32 0, %pti                                            ; -alloca
+  %add = getelementptr [4 x i8], [4 x i8]* %bc, i32 0, i32 %sub     ; alloca + 4 - alloca == 4
+  %add_to_int = ptrtoint i8* %add to i32                            ; 4
+  ret i32 %add_to_int                                               ; 4
+; CHECK-NEXT: ret i32 4
+}
+
+ define i1 @zext(i32 %x) {
+ ; CHECK-LABEL: @zext(
+   %e1 = zext i32 %x to i64
+-- 
+2.7.4
+
+From c3eb3c7608f439231d0c1340af6b720f113b4bf4 Mon Sep 17 00:00:00 2001
+From: David Majnemer <david.majnemer@gmail.com>
+Date: Tue, 16 Aug 2016 06:13:46 +0000
+Subject: [rust-lang/llvm#47 4/4] [InstSimplify] Fold gep (gep V, C), (xor V,
+ -1) to C-1
+
+git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278779 91177308-0d34-0410-b5e6-96231b3b80d8
+---
+ lib/Analysis/InstructionSimplify.cpp    |  8 +++++++-
+ test/Transforms/InstSimplify/compare.ll | 13 -------------
+ 2 files changed, 7 insertions(+), 14 deletions(-)
+
+diff --git a/lib/Analysis/InstructionSimplify.cpp b/lib/Analysis/InstructionSimplify.cpp
+index 9d2a47957125..f7a435d1ad46 100644
+--- a/lib/Analysis/InstructionSimplify.cpp
+++ b/lib/Analysis/InstructionSimplify.cpp
+@@ -3597,7 +3597,6 @@ static Value *SimplifyGEPInst(Type *SrcTy, ArrayRef<Value *> Ops,
+     }
+   }
+ 
+-  // gep (gep V, C), (sub 0, V) -> C
+   if (Q.DL.getTypeAllocSize(LastType) == 1 &&
+       all_of(Ops.slice(1).drop_back(1),
+              [](Value *Idx) { return match(Idx, m_Zero()); })) {
+@@ -3609,11 +3608,18 @@ static Value *SimplifyGEPInst(Type *SrcTy, ArrayRef<Value *> Ops,
+           Ops[0]->stripAndAccumulateInBoundsConstantOffsets(Q.DL,
+                                                             BasePtrOffset);
+ 
+      // gep (gep V, C), (sub 0, V) -> C
+       if (match(Ops.back(),
+                 m_Sub(m_Zero(), m_PtrToInt(m_Specific(StrippedBasePtr))))) {
+         auto *CI = ConstantInt::get(GEPTy->getContext(), BasePtrOffset);
+         return ConstantExpr::getIntToPtr(CI, GEPTy);
+       }
+      // gep (gep V, C), (xor V, -1) -> C-1
+      if (match(Ops.back(),
+                m_Xor(m_PtrToInt(m_Specific(StrippedBasePtr)), m_AllOnes()))) {
+        auto *CI = ConstantInt::get(GEPTy->getContext(), BasePtrOffset - 1);
+        return ConstantExpr::getIntToPtr(CI, GEPTy);
+      }
+     }
+   }
+ 
+diff --git a/test/Transforms/InstSimplify/compare.ll b/test/Transforms/InstSimplify/compare.ll
+index addb63c57222..3e7316ec6b48 100644
+--- a/test/Transforms/InstSimplify/compare.ll
+++ b/test/Transforms/InstSimplify/compare.ll
+@@ -218,19 +218,6 @@ define i1 @gep17() {
+ ; CHECK-NEXT: ret i1 true
+ }
+ 
+-define i32 @gep18() {
+-; CHECK-LABEL: @gep18(
+-  %alloca = alloca i32, align 4                                     ; alloca + 0
+-  %gep = getelementptr inbounds i32, i32* %alloca, i32 1            ; alloca + 4
+-  %bc = bitcast i32* %gep to [4 x i8]*                              ; alloca + 4
+-  %pti = ptrtoint i32* %alloca to i32                               ; alloca
+-  %sub = sub i32 0, %pti                                            ; -alloca
+-  %add = getelementptr [4 x i8], [4 x i8]* %bc, i32 0, i32 %sub     ; alloca + 4 - alloca == 4
+-  %add_to_int = ptrtoint i8* %add to i32                            ; 4
+-  ret i32 %add_to_int                                               ; 4
+-; CHECK-NEXT: ret i32 4
+-}
+-
+ define i1 @zext(i32 %x) {
+ ; CHECK-LABEL: @zext(
+   %e1 = zext i32 %x to i64
+-- 
+2.7.4
+
--- a/rust-lang-llvm-pr53.patch
+++ b/rust-lang-llvm-pr53.patch
@ -0,0 +1,883 @@
+From 0d4331af6e01235479e44f9775b3fde9e19200a3 Mon Sep 17 00:00:00 2001
+From: Keith Walker <kwalker@arm.com>
+Date: Tue, 27 Sep 2016 16:46:07 +0000
+Subject: [rust-lang/llvm#53 1/2] Propagate DBG_VALUE entries when there are
+ unvisited predecessors
+
+Variables are sometimes missing their debug location information in
+blocks in which the variables should be available. This would occur
+when one or more predecessor blocks had not yet been visited by the
+routine which propagated the information from predecessor blocks.
+
+This is addressed by only considering predecessor blocks which have
+already been visited.
+
+The solution to this problem was suggested by Daniel Berlin on the
+LLVM developer mailing list.
+
+Differential Revision: https://reviews.llvm.org/D24927
+
+
+git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282506 91177308-0d34-0410-b5e6-96231b3b80d8
+---
+ lib/CodeGen/LiveDebugValues.cpp          |  34 ++--
+ test/CodeGen/ARM/dbg-range-extension.mir | 282 +++++++++++++++++++++++++++++++
+ 2 files changed, 306 insertions(+), 10 deletions(-)
+ create mode 100644 test/CodeGen/ARM/dbg-range-extension.mir
+
+diff --git a/lib/CodeGen/LiveDebugValues.cpp b/lib/CodeGen/LiveDebugValues.cpp
+index 4ff88d528108..4cadd5855ed5 100644
+--- a/lib/CodeGen/LiveDebugValues.cpp
+++ b/lib/CodeGen/LiveDebugValues.cpp
+@@ -201,7 +201,8 @@ private:
+                 VarLocInMBB &OutLocs, VarLocMap &VarLocIDs);
+ 
+   bool join(MachineBasicBlock &MBB, VarLocInMBB &OutLocs, VarLocInMBB &InLocs,
+-            const VarLocMap &VarLocIDs);
+            const VarLocMap &VarLocIDs,
+            SmallPtrSet<const MachineBasicBlock *, 16> &Visited);
+ 
+   bool ExtendRanges(MachineFunction &MF);
+ 
+@@ -368,7 +369,8 @@ bool LiveDebugValues::transfer(MachineInstr &MI, OpenRangesSet &OpenRanges,
+ /// inserting a new DBG_VALUE instruction at the start of the @MBB - if the same
+ /// source variable in all the predecessors of @MBB reside in the same location.
+ bool LiveDebugValues::join(MachineBasicBlock &MBB, VarLocInMBB &OutLocs,
+-                           VarLocInMBB &InLocs, const VarLocMap &VarLocIDs) {
+                           VarLocInMBB &InLocs, const VarLocMap &VarLocIDs,
+                           SmallPtrSet<const MachineBasicBlock *, 16> &Visited) {
+   DEBUG(dbgs() << "join MBB: " << MBB.getName() << "\n");
+   bool Changed = false;
+ 
+@@ -376,21 +378,32 @@ bool LiveDebugValues::join(MachineBasicBlock &MBB, VarLocInMBB &OutLocs,
+ 
+   // For all predecessors of this MBB, find the set of VarLocs that
+   // can be joined.
+  int NumVisited = 0;
+   for (auto p : MBB.predecessors()) {
+    // Ignore unvisited predecessor blocks.  As we are processing
+    // the blocks in reverse post-order any unvisited block can
+    // be considered to not remove any incoming values.
+    if (!Visited.count(p))
+      continue;
+     auto OL = OutLocs.find(p);
+     // Join is null in case of empty OutLocs from any of the pred.
+     if (OL == OutLocs.end())
+       return false;
+ 
+-    // Just copy over the Out locs to incoming locs for the first predecessor.
+-    if (p == *MBB.pred_begin()) {
+    // Just copy over the Out locs to incoming locs for the first visited
+    // predecessor, and for all other predecessors join the Out locs.
+    if (!NumVisited)
+       InLocsT = OL->second;
+-      continue;
+-    }
+-    // Join with this predecessor.
+-    InLocsT &= OL->second;
+    else
+      InLocsT &= OL->second;
+    NumVisited++;
+   }
+ 
+  // As we are processing blocks in reverse post-order we
+  // should have processed at least one predecessor, unless it
+  // is the entry block which has no predecessor.
+  assert((NumVisited || MBB.pred_empty()) &&
+         "Should have processed at least one predecessor");
+   if (InLocsT.empty())
+     return false;
+ 
+@@ -463,6 +476,7 @@ bool LiveDebugValues::ExtendRanges(MachineFunction &MF) {
+   // To solve it, we perform join() and transfer() using the two worklist method
+   // until the ranges converge.
+   // Ranges have converged when both worklists are empty.
+  SmallPtrSet<const MachineBasicBlock *, 16> Visited;
+   while (!Worklist.empty() || !Pending.empty()) {
+     // We track what is on the pending worklist to avoid inserting the same
+     // thing twice.  We could avoid this with a custom priority queue, but this
+@@ -471,8 +485,8 @@ bool LiveDebugValues::ExtendRanges(MachineFunction &MF) {
+     while (!Worklist.empty()) {
+       MachineBasicBlock *MBB = OrderToBB[Worklist.top()];
+       Worklist.pop();
+-      MBBJoined = join(*MBB, OutLocs, InLocs, VarLocIDs);
+-
+      MBBJoined = join(*MBB, OutLocs, InLocs, VarLocIDs, Visited);
+      Visited.insert(MBB);
+       if (MBBJoined) {
+         MBBJoined = false;
+         Changed = true;
+diff --git a/test/CodeGen/ARM/dbg-range-extension.mir b/test/CodeGen/ARM/dbg-range-extension.mir
+new file mode 100644
+index 000000000000..b18f56197948
+--- /dev/null
+++ b/test/CodeGen/ARM/dbg-range-extension.mir
+@@ -0,0 +1,282 @@
+# RUN: llc -mtriple=arm-eabi -run-pass=livedebugvalues %s -o - | FileCheck %s
+#
+# Check that the debug information for variables are propagated into the correct blocks.
+#
+# Generated from the C source:
+#
+# int func2(int,  int);
+# void func(int a) {
+#   int b = func2(10, 11);
+#   if (a) {
+#     int c = func2(12, 13);
+#     for(int i = 1; i < a; i++) {
+#       func2(i, i+b);
+#     }
+#     func2(b,c);
+#   }
+#   func2(b,a);
+# }
+
+# CHECK: [[VAR_A:![0-9]+]] = !DILocalVariable(name: "a",
+# CHECK: [[VAR_B:![0-9]+]] = !DILocalVariable(name: "b",
+# CHECK: [[VAR_C:![0-9]+]] = !DILocalVariable(name: "c",
+# CHECK: [[VAR_I:![0-9]+]] = !DILocalVariable(name: "i",
+
+# CHECK: bb.0.entry
+# CHECK: DBG_VALUE debug-use %r0, debug-use _, [[VAR_A]]
+# CHECK: DBG_VALUE debug-use [[REG_A:%r[0-9]+]], debug-use _, [[VAR_A]]
+# CHECK: DBG_VALUE debug-use [[REG_B:%r[0-9]+]], debug-use _, [[VAR_B]]
+
+# CHECK: bb.1.if.then
+# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use _, [[VAR_B]]
+# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use _, [[VAR_A]]
+# CHECK: DBG_VALUE debug-use [[REG_C:%r[0-9]+]], debug-use _, [[VAR_C]]
+# CHECK: DBG_VALUE 1, 0, [[VAR_I]]
+
+# CHECK: bb.2.for.body
+# CHECK: DBG_VALUE debug-use [[REG_I:%r[0-9]+]], debug-use _, [[VAR_I]]
+# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use _, [[VAR_C]]
+# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use _, [[VAR_B]]
+# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use _, [[VAR_A]]
+# CHECK: DBG_VALUE debug-use [[REG_I]], debug-use _, [[VAR_I]]
+
+# CHECK: bb.3.for.cond
+# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use _, [[VAR_C]]
+# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use _, [[VAR_B]]
+# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use _, [[VAR_A]]
+# CHECK: DBG_VALUE debug-use [[REG_I]], debug-use _, [[VAR_I]]
+
+# CHECK: bb.4.for.cond.cleanup
+# CHECK: DBG_VALUE debug-use [[REG_I]], debug-use _, [[VAR_I]]
+# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use _, [[VAR_C]]
+# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use _, [[VAR_B]]
+# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use _, [[VAR_A]]
+
+# CHECK: bb.5.if.end
+# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use _, [[VAR_B]]
+# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use _, [[VAR_A]]
+--- |
+  ; ModuleID = '/data/kwalker/work/OpenSource-llvm/llvm/test/CodeGen/ARM/dbg-range-extension.ll'
+  source_filename = "/data/kwalker/work/OpenSource-llvm/llvm/test/CodeGen/ARM/dbg-range-extension.ll"
+  target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+  target triple = "arm---eabi"
+  
+  ; Function Attrs: minsize nounwind optsize
+  define void @func(i32 %a) local_unnamed_addr #0 !dbg !8 {
+  entry:
+    tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !13, metadata !20), !dbg !21
+    %call = tail call i32 @func2(i32 10, i32 11) #0, !dbg !22
+    tail call void @llvm.dbg.value(metadata i32 %call, i64 0, metadata !14, metadata !20), !dbg !23
+    %tobool = icmp eq i32 %a, 0, !dbg !24
+    br i1 %tobool, label %if.end, label %if.then, !dbg !25
+  
+  if.then:                                          ; preds = %entry
+    %call1 = tail call i32 @func2(i32 12, i32 13) #0, !dbg !26
+    tail call void @llvm.dbg.value(metadata i32 %call1, i64 0, metadata !15, metadata !20), !dbg !27
+    tail call void @llvm.dbg.value(metadata i32 1, i64 0, metadata !18, metadata !20), !dbg !28
+    br label %for.cond, !dbg !29
+  
+  for.cond:                                         ; preds = %for.body, %if.then
+    %i.0 = phi i32 [ 1, %if.then ], [ %inc, %for.body ]
+    tail call void @llvm.dbg.value(metadata i32 %i.0, i64 0, metadata !18, metadata !20), !dbg !28
+    %cmp = icmp slt i32 %i.0, %a, !dbg !30
+    br i1 %cmp, label %for.body, label %for.cond.cleanup, !dbg !33
+  
+  for.cond.cleanup:                                 ; preds = %for.cond
+    %call3 = tail call i32 @func2(i32 %call, i32 %call1) #0, !dbg !34
+    br label %if.end, !dbg !35
+  
+  for.body:                                         ; preds = %for.cond
+    %0 = add i32 %call, %i.0, !dbg !36
+    %call2 = tail call i32 @func2(i32 %i.0, i32 %0) #0, !dbg !36
+    %inc = add nuw nsw i32 %i.0, 1, !dbg !38
+    tail call void @llvm.dbg.value(metadata i32 %inc, i64 0, metadata !18, metadata !20), !dbg !28
+    br label %for.cond, !dbg !40, !llvm.loop !41
+  
+  if.end:                                           ; preds = %for.cond.cleanup, %entry
+    %call4 = tail call i32 @func2(i32 %call, i32 %a) #0, !dbg !43
+    ret void, !dbg !44
+  }
+  
+  ; Function Attrs: minsize optsize
+  declare i32 @func2(i32, i32) local_unnamed_addr #1
+  
+  ; Function Attrs: nounwind readnone
+  declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2
+  
+  ; Function Attrs: nounwind
+  declare void @llvm.stackprotector(i8*, i8**) #3
+  
+  attributes #0 = { minsize nounwind optsize }
+  attributes #1 = { minsize optsize }
+  attributes #2 = { nounwind readnone }
+  attributes #3 = { nounwind }
+  
+  !llvm.dbg.cu = !{!0}
+  !llvm.module.flags = !{!3, !4, !5, !6}
+  !llvm.ident = !{!7}
+  
+  !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
+  !1 = !DIFile(filename: "loop.c", directory: "/tmp")
+  !2 = !{}
+  !3 = !{i32 2, !"Dwarf Version", i32 4}
+  !4 = !{i32 2, !"Debug Info Version", i32 3}
+  !5 = !{i32 1, !"wchar_size", i32 4}
+  !6 = !{i32 1, !"min_enum_size", i32 4}
+  !7 = !{!"clang version 4.0.0 (http://llvm.org/git/clang.git b8f10df3679b36f51e1de7c4351b82d297825089) (http://llvm.org/git/llvm.git c2a5d16d1e3b8c49f5bbb1ff87a76ac4f88edb89)"}
+  !8 = distinct !DISubprogram(name: "func", scope: !1, file: !1, line: 2, type: !9, isLocal: false, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, unit: !0, variables: !12)
+  !9 = !DISubroutineType(types: !10)
+  !10 = !{null, !11}
+  !11 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+  !12 = !{!13, !14, !15, !18}
+  !13 = !DILocalVariable(name: "a", arg: 1, scope: !8, file: !1, line: 2, type: !11)
+  !14 = !DILocalVariable(name: "b", scope: !8, file: !1, line: 3, type: !11)
+  !15 = !DILocalVariable(name: "c", scope: !16, file: !1, line: 5, type: !11)
+  !16 = distinct !DILexicalBlock(scope: !17, file: !1, line: 4, column: 9)
+  !17 = distinct !DILexicalBlock(scope: !8, file: !1, line: 4, column: 6)
+  !18 = !DILocalVariable(name: "i", scope: !19, file: !1, line: 6, type: !11)
+  !19 = distinct !DILexicalBlock(scope: !16, file: !1, line: 6, column: 3)
+  !20 = !DIExpression()
+  !21 = !DILocation(line: 2, column: 15, scope: !8)
+  !22 = !DILocation(line: 3, column: 17, scope: !8)
+  !23 = !DILocation(line: 3, column: 13, scope: !8)
+  !24 = !DILocation(line: 4, column: 6, scope: !17)
+  !25 = !DILocation(line: 4, column: 6, scope: !8)
+  !26 = !DILocation(line: 5, column: 11, scope: !16)
+  !27 = !DILocation(line: 5, column: 7, scope: !16)
+  !28 = !DILocation(line: 6, column: 11, scope: !19)
+  !29 = !DILocation(line: 6, column: 7, scope: !19)
+  !30 = !DILocation(line: 6, column: 20, scope: !31)
+  !31 = !DILexicalBlockFile(scope: !32, file: !1, discriminator: 1)
+  !32 = distinct !DILexicalBlock(scope: !19, file: !1, line: 6, column: 3)
+  !33 = !DILocation(line: 6, column: 3, scope: !31)
+  !34 = !DILocation(line: 9, column: 3, scope: !16)
+  !35 = !DILocation(line: 10, column: 2, scope: !16)
+  !36 = !DILocation(line: 7, column: 4, scope: !37)
+  !37 = distinct !DILexicalBlock(scope: !32, file: !1, line: 6, column: 30)
+  !38 = !DILocation(line: 6, column: 26, scope: !39)
+  !39 = !DILexicalBlockFile(scope: !32, file: !1, discriminator: 3)
+  !40 = !DILocation(line: 6, column: 3, scope: !39)
+  !41 = distinct !{!41, !42}
+  !42 = !DILocation(line: 6, column: 3, scope: !16)
+  !43 = !DILocation(line: 11, column: 2, scope: !8)
+  !44 = !DILocation(line: 12, column: 1, scope: !8)
+
+...
+---
+name:            func
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: false
+liveins:         
+  - { reg: '%r0' }
+calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13', 
+                        '%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4', 
+                        '%r5', '%r6', '%r7', '%r8', '%r9', '%r10', '%r11', 
+                        '%s16', '%s17', '%s18', '%s19', '%s20', '%s21', 
+                        '%s22', '%s23', '%s24', '%s25', '%s26', '%s27', 
+                        '%s28', '%s29', '%s30', '%s31', '%d8_d10', '%d9_d11', 
+                        '%d10_d12', '%d11_d13', '%d12_d14', '%d13_d15', 
+                        '%q4_q5', '%q5_q6', '%q6_q7', '%q4_q5_q6_q7', '%r4_r5', 
+                        '%r6_r7', '%r8_r9', '%r10_r11', '%d8_d9_d10', '%d9_d10_d11', 
+                        '%d10_d11_d12', '%d11_d12_d13', '%d12_d13_d14', 
+                        '%d13_d14_d15', '%d8_d10_d12', '%d9_d11_d13', '%d10_d12_d14', 
+                        '%d11_d13_d15', '%d8_d10_d12_d14', '%d9_d11_d13_d15', 
+                        '%d9_d10', '%d11_d12', '%d13_d14', '%d9_d10_d11_d12', 
+                        '%d11_d12_d13_d14' ]
+frameInfo:       
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       24
+  offsetAdjustment: 0
+  maxAlignment:    4
+  adjustsStack:    true
+  hasCalls:        true
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+stack:           
+  - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr' }
+  - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r11' }
+  - { id: 2, type: spill-slot, offset: -12, size: 4, alignment: 4, callee-saved-register: '%r7' }
+  - { id: 3, type: spill-slot, offset: -16, size: 4, alignment: 4, callee-saved-register: '%r6' }
+  - { id: 4, type: spill-slot, offset: -20, size: 4, alignment: 4, callee-saved-register: '%r5' }
+  - { id: 5, type: spill-slot, offset: -24, size: 4, alignment: 4, callee-saved-register: '%r4' }
+body:             |
+  bb.0.entry:
+    successors: %bb.5.if.end, %bb.1.if.then
+    liveins: %r0, %r4, %r5, %r6, %r7, %r11, %lr
+  
+    %sp = frame-setup STMDB_UPD %sp, 14, _, killed %r4, killed %r5, killed %r6, killed %r7, killed %r11, killed %lr
+    frame-setup CFI_INSTRUCTION def_cfa_offset 24
+    frame-setup CFI_INSTRUCTION offset %lr, -4
+    frame-setup CFI_INSTRUCTION offset %r11, -8
+    frame-setup CFI_INSTRUCTION offset %r7, -12
+    frame-setup CFI_INSTRUCTION offset %r6, -16
+    frame-setup CFI_INSTRUCTION offset %r5, -20
+    frame-setup CFI_INSTRUCTION offset %r4, -24
+    DBG_VALUE debug-use %r0, debug-use _, !13, !20, debug-location !21
+    %r4 = MOVr killed %r0, 14, _, _
+    DBG_VALUE debug-use %r4, debug-use _, !13, !20, debug-location !21
+    %r0 = MOVi 10, 14, _, _, debug-location !22
+    %r1 = MOVi 11, 14, _, _, debug-location !22
+    BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def %r0, debug-location !22
+    %r5 = MOVr killed %r0, 14, _, _, debug-location !22
+    DBG_VALUE debug-use %r5, debug-use _, !14, !20, debug-location !23
+    CMPri %r4, 0, 14, _, implicit-def %cpsr, debug-location !25
+    Bcc %bb.5.if.end, 0, killed %cpsr
+  
+  bb.1.if.then:
+    successors: %bb.3.for.cond
+    liveins: %r4, %r5
+  
+    %r0 = MOVi 12, 14, _, _, debug-location !26
+    %r1 = MOVi 13, 14, _, _, debug-location !26
+    BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def %r0, debug-location !26
+    %r6 = MOVr killed %r0, 14, _, _, debug-location !26
+    DBG_VALUE debug-use %r6, debug-use _, !15, !20, debug-location !27
+    %r7 = MOVi 1, 14, _, _
+    DBG_VALUE 1, 0, !18, !20, debug-location !28
+    B %bb.3.for.cond
+  
+  bb.2.for.body:
+    successors: %bb.3.for.cond
+    liveins: %r4, %r5, %r6, %r7
+  
+    %r1 = ADDrr %r5, %r7, 14, _, _, debug-location !36
+    %r0 = MOVr %r7, 14, _, _, debug-location !36
+    BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def dead %r0, debug-location !36
+    %r7 = ADDri killed %r7, 1, 14, _, _, debug-location !38
+    DBG_VALUE debug-use %r7, debug-use _, !18, !20, debug-location !28
+  
+  bb.3.for.cond:
+    successors: %bb.2.for.body, %bb.4.for.cond.cleanup
+    liveins: %r4, %r5, %r6, %r7
+  
+    DBG_VALUE debug-use %r7, debug-use _, !18, !20, debug-location !28
+    CMPrr %r7, %r4, 14, _, implicit-def %cpsr, debug-location !33
+    Bcc %bb.2.for.body, 11, killed %cpsr, debug-location !33
+  
+  bb.4.for.cond.cleanup:
+    successors: %bb.5.if.end
+    liveins: %r4, %r5, %r6
+  
+    %r0 = MOVr %r5, 14, _, _, debug-location !34
+    %r1 = MOVr killed %r6, 14, _, _, debug-location !34
+    BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def dead %r0, debug-location !34
+  
+  bb.5.if.end:
+    liveins: %r4, %r5
+  
+    %r0 = MOVr killed %r5, 14, _, _, debug-location !43
+    %r1 = MOVr killed %r4, 14, _, _, debug-location !43
+    %sp = LDMIA_UPD %sp, 14, _, def %r4, def %r5, def %r6, def %r7, def %r11, def %lr, debug-location !43
+    TAILJMPd @func2, implicit %sp, implicit %sp, implicit killed %r0, implicit killed %r1, debug-location !43
+
+...
+-- 
+2.7.4
+
+From 8a0fc26559123bb6eab3ceae93d5a2c94943614b Mon Sep 17 00:00:00 2001
+From: Adrian Prantl <aprantl@apple.com>
+Date: Wed, 28 Sep 2016 17:51:14 +0000
+Subject: [rust-lang/llvm#53 2/2] Teach LiveDebugValues about lexical scopes.
+
+This addresses PR26055 LiveDebugValues is very slow.
+
+Contrary to the old LiveDebugVariables pass LiveDebugValues currently
+doesn't look at the lexical scopes before inserting a DBG_VALUE
+intrinsic. This means that we often propagate DBG_VALUEs much further
+down than necessary. This is especially noticeable in large C++
+functions with many inlined method calls that all use the same
+"this"-pointer.
+
+For example, in the following code it makes no sense to propagate the
+inlined variable a from the first inlined call to f() into any of the
+subsequent basic blocks, because the variable will always be out of
+scope:
+
+void sink(int a);
+void __attribute((always_inline)) f(int a) { sink(a); }
+void foo(int i) {
+   f(i);
+   if (i)
+     f(i);
+   f(i);
+}
+
+This patch reuses the LexicalScopes infrastructure we have for
+LiveDebugVariables to take this into account.
+
+The effect on compile time and memory consumption is quite noticeable:
+I tested a benchmark that is a large C++ source with an enormous
+amount of inlined "this"-pointers that would previously eat >24GiB
+(most of them for DBG_VALUE intrinsics) and whose compile time was
+dominated by LiveDebugValues. With this patch applied the memory
+consumption is 1GiB and 1.7% of the time is spent in LiveDebugValues.
+
+https://reviews.llvm.org/D24994
+Thanks to Daniel Berlin and Keith Walker for reviewing!
+
+git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282611 91177308-0d34-0410-b5e6-96231b3b80d8
+---
+ lib/CodeGen/LiveDebugValues.cpp                  |  51 ++++-
+ test/CodeGen/ARM/dbg-range-extension.mir         |   1 -
+ test/DebugInfo/COFF/register-variables.ll        |   8 +-
+ test/DebugInfo/MIR/X86/livedebugvalues-limit.mir | 228 +++++++++++++++++++++++
+ test/DebugInfo/X86/fission-ranges.ll             |   6 +-
+ 5 files changed, 278 insertions(+), 16 deletions(-)
+ create mode 100644 test/DebugInfo/MIR/X86/livedebugvalues-limit.mir
+
+diff --git a/lib/CodeGen/LiveDebugValues.cpp b/lib/CodeGen/LiveDebugValues.cpp
+index 4cadd5855ed5..969944eb24a2 100644
+--- a/lib/CodeGen/LiveDebugValues.cpp
+++ b/lib/CodeGen/LiveDebugValues.cpp
+@@ -23,6 +23,7 @@
+ #include "llvm/ADT/SparseBitVector.h"
+ #include "llvm/ADT/Statistic.h"
+ #include "llvm/ADT/UniqueVector.h"
+#include "llvm/CodeGen/LexicalScopes.h"
+ #include "llvm/CodeGen/MachineFunction.h"
+ #include "llvm/CodeGen/MachineFunctionPass.h"
+ #include "llvm/CodeGen/MachineInstrBuilder.h"
+@@ -60,6 +61,26 @@ class LiveDebugValues : public MachineFunctionPass {
+ private:
+   const TargetRegisterInfo *TRI;
+   const TargetInstrInfo *TII;
+  LexicalScopes LS;
+
+  /// Keeps track of lexical scopes associated with a user value's source
+  /// location.
+  class UserValueScopes {
+    DebugLoc DL;
+    LexicalScopes &LS;
+    SmallPtrSet<const MachineBasicBlock *, 4> LBlocks;
+
+  public:
+    UserValueScopes(DebugLoc D, LexicalScopes &L) : DL(std::move(D)), LS(L) {}
+
+    /// Return true if current scope dominates at least one machine
+    /// instruction in a given machine basic block.
+    bool dominates(MachineBasicBlock *MBB) {
+      if (LBlocks.empty())
+        LS.getMachineBasicBlocks(DL, LBlocks);
+      return LBlocks.count(MBB) != 0 || LS.dominates(DL, MBB);
+    }
+  };
+ 
+   /// Based on std::pair so it can be used as an index into a DenseMap.
+   typedef std::pair<const DILocalVariable *, const DILocation *>
+@@ -83,7 +104,7 @@ private:
+   struct VarLoc {
+     const DebugVariable Var;
+     const MachineInstr &MI; ///< Only used for cloning a new DBG_VALUE.
+-
+    mutable UserValueScopes UVS;
+     enum { InvalidKind = 0, RegisterKind } Kind;
+ 
+     /// The value location. Stored separately to avoid repeatedly
+@@ -96,9 +117,9 @@ private:
+       uint64_t Hash;
+     } Loc;
+ 
+-    VarLoc(const MachineInstr &MI)
+    VarLoc(const MachineInstr &MI, LexicalScopes &LS)
+         : Var(MI.getDebugVariable(), MI.getDebugLoc()->getInlinedAt()), MI(MI),
+-          Kind(InvalidKind) {
+          UVS(MI.getDebugLoc(), LS), Kind(InvalidKind) {
+       static_assert((sizeof(Loc) == sizeof(uint64_t)),
+                     "hash does not cover all members of Loc");
+       assert(MI.isDebugValue() && "not a DBG_VALUE");
+@@ -125,6 +146,10 @@ private:
+       return 0;
+     }
+ 
+    /// Determine whether the lexical scope of this value's debug location
+    /// dominates MBB.
+    bool dominates(MachineBasicBlock &MBB) const { return UVS.dominates(&MBB); }
+
+     void dump() const { MI.dump(); }
+ 
+     bool operator==(const VarLoc &Other) const {
+@@ -229,6 +254,7 @@ public:
+   /// Calculate the liveness information for the given machine function.
+   bool runOnMachineFunction(MachineFunction &MF) override;
+ };
+
+ } // namespace
+ 
+ //===----------------------------------------------------------------------===//
+@@ -295,7 +321,7 @@ void LiveDebugValues::transferDebugValue(const MachineInstr &MI,
+   // Add the VarLoc to OpenRanges from this DBG_VALUE.
+   // TODO: Currently handles DBG_VALUE which has only reg as location.
+   if (isDbgValueDescribedByReg(MI)) {
+-    VarLoc VL(MI);
+    VarLoc VL(MI, LS);
+     unsigned ID = VarLocIDs.insert(VL);
+     OpenRanges.insert(ID, VL.Var);
+   }
+@@ -399,6 +425,13 @@ bool LiveDebugValues::join(MachineBasicBlock &MBB, VarLocInMBB &OutLocs,
+     NumVisited++;
+   }
+ 
+  // Filter out DBG_VALUES that are out of scope.
+  VarLocSet KillSet;
+  for (auto ID : InLocsT)
+    if (!VarLocIDs[ID].dominates(MBB))
+      KillSet.set(ID);
+  InLocsT.intersectWithComplement(KillSet);
+
+   // As we are processing blocks in reverse post-order we
+   // should have processed at least one predecessor, unless it
+   // is the entry block which has no predecessor.
+@@ -519,12 +552,14 @@ bool LiveDebugValues::ExtendRanges(MachineFunction &MF) {
+ }
+ 
+ bool LiveDebugValues::runOnMachineFunction(MachineFunction &MF) {
+  if (!MF.getFunction()->getSubprogram())
+    // LiveDebugValues will already have removed all DBG_VALUEs.
+    return false;
+
+   TRI = MF.getSubtarget().getRegisterInfo();
+   TII = MF.getSubtarget().getInstrInfo();
+  LS.initialize(MF);
+ 
+-  bool Changed = false;
+-
+-  Changed |= ExtendRanges(MF);
+-
+  bool Changed = ExtendRanges(MF);
+   return Changed;
+ }
+diff --git a/test/CodeGen/ARM/dbg-range-extension.mir b/test/CodeGen/ARM/dbg-range-extension.mir
+index b18f56197948..466f69396948 100644
+--- a/test/CodeGen/ARM/dbg-range-extension.mir
+++ b/test/CodeGen/ARM/dbg-range-extension.mir
+@@ -47,7 +47,6 @@
+ # CHECK: DBG_VALUE debug-use [[REG_I]], debug-use _, [[VAR_I]]
+ 
+ # CHECK: bb.4.for.cond.cleanup
+-# CHECK: DBG_VALUE debug-use [[REG_I]], debug-use _, [[VAR_I]]
+ # CHECK: DBG_VALUE debug-use [[REG_C]], debug-use _, [[VAR_C]]
+ # CHECK: DBG_VALUE debug-use [[REG_B]], debug-use _, [[VAR_B]]
+ # CHECK: DBG_VALUE debug-use [[REG_A]], debug-use _, [[VAR_A]]
+diff --git a/test/DebugInfo/COFF/register-variables.ll b/test/DebugInfo/COFF/register-variables.ll
+index 9bb782853a3d..08246fef9603 100644
+--- a/test/DebugInfo/COFF/register-variables.ll
+++ b/test/DebugInfo/COFF/register-variables.ll
+@@ -37,8 +37,8 @@
+ ; ASM:         #DEBUG_VALUE: c <- %EAX
+ ; ASM:         testl   %esi, %esi
+ ; ASM:         je      .LBB0_2
+; ASM: [[after_je:\.Ltmp.*]]:
+ ; ASM: # BB#1:                                 # %if.then
+-; ASM-DAG:     #DEBUG_VALUE: c <- %EAX
+ ; ASM-DAG:     #DEBUG_VALUE: inlineinc:a <- %EAX
+ ; ASM-DAG:     #DEBUG_VALUE: a <- %EAX
+ ; ASM-DAG:     #DEBUG_VALUE: f:p <- %ESI
+@@ -65,7 +65,7 @@
+ ; ASM:         .cv_def_range    [[after_getint]] [[after_inc_eax]], "A\021\021\000\000\000"
+ ; ASM:         .short  4414                    # Record kind: S_LOCAL
+ ; ASM:         .asciz  "c"
+-; ASM:         .cv_def_range    [[after_getint]] [[after_inc_eax]], "A\021\021\000\000\000"
+; ASM:         .cv_def_range    [[after_getint]] [[after_je]], "A\021\021\000\000\000"
+ ; ASM:         .short  4414                    # Record kind: S_LOCAL
+ ; ASM:         .asciz  "b"
+ ; ASM:         .cv_def_range    [[after_inc_eax]] [[after_if]], "A\021\021\000\000\000"
+@@ -132,7 +132,7 @@
+ ; OBJ:     LocalVariableAddrRange {
+ ; OBJ:       OffsetStart: .text+0xC
+ ; OBJ:       ISectStart: 0x0
+-; OBJ:       Range: 0x6
+; OBJ:       Range: 0x4
+ ; OBJ:     }
+ ; OBJ:   }
+ ; OBJ:   Local {
+@@ -143,7 +143,7 @@
+ ; OBJ:   }
+ ; OBJ:   DefRangeRegister {
+ ; OBJ:     Register: 17
+-; OBJ:     LocalVariableAddrRange {
+; OBJ:     MayHaveNoName: 0
+ ; OBJ:       OffsetStart: .text+0x12
+ ; OBJ:       ISectStart: 0x0
+ ; OBJ:       Range: 0x6
+diff --git a/test/DebugInfo/MIR/X86/livedebugvalues-limit.mir b/test/DebugInfo/MIR/X86/livedebugvalues-limit.mir
+new file mode 100644
+index 000000000000..4c87543636d5
+--- /dev/null
+++ b/test/DebugInfo/MIR/X86/livedebugvalues-limit.mir
+@@ -0,0 +1,228 @@
+--- |
+  ; RUN: llc -run-pass=livedebugvalues -march=x86-64 -o - %s | FileCheck %s
+  ; Created from:
+  ; void sink(int a);
+  ; void __attribute((always_inline)) f(int a) { sink(a); }
+  ; void foo(int i) {
+  ;   f(i);
+  ;   if (i)
+  ;     f(i);
+  ;   f(i);
+  ; }
+  ;
+  ; This test verifies that LiveDebugValues doesn't propagate DBG_VALUEs into
+  ; basic blocks that are beyond the scope of the source variable.
+  ;
+  ; CHECK:  bb.1.if.then:
+  ; CHECK:      DBG_VALUE debug-use %ebx, debug-use _, !19, !13, debug-location !20
+  ; CHECK-NOT:  DBG_VALUE debug-use %ebx, debug-use _, !12, !13, debug-location !21
+  ; CHECK:      DBG_VALUE debug-use %ebx, debug-use _, !12, !13, debug-location !27
+  ; CHECK: bb.2.if.end:
+  ; CHECK:     DBG_VALUE debug-use %ebx, debug-use _, !19, !13, debug-location !20
+  ; CHECK-NOT: DBG_VALUE debug-use %ebx, debug-use _, !12, !13, debug-location !21
+  ; CHECK:     DBG_VALUE debug-use %ebx, debug-use _, !12, !13, debug-location !31
+  ;
+  ; ModuleID = 'livedebugvalues-limit.ll'
+  source_filename = "livedebugvalues-limit.c"
+  target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+  target triple = "x86_64-apple-macosx"
+  
+  ; Function Attrs: alwaysinline nounwind ssp uwtable
+  define void @f(i32 %a) local_unnamed_addr #0 !dbg !7 {
+  entry:
+    tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !12, metadata !13), !dbg !14
+    tail call void @sink(i32 %a) #4, !dbg !15
+    ret void, !dbg !16
+  }
+  
+  declare void @sink(i32) local_unnamed_addr
+  
+  ; Function Attrs: nounwind ssp uwtable
+  define void @foo(i32 %i) local_unnamed_addr #2 !dbg !17 {
+  entry:
+    tail call void @llvm.dbg.value(metadata i32 %i, i64 0, metadata !19, metadata !13), !dbg !20
+    tail call void @llvm.dbg.value(metadata i32 %i, i64 0, metadata !12, metadata !13) #4, !dbg !21
+    tail call void @sink(i32 %i) #4, !dbg !23
+    %tobool = icmp eq i32 %i, 0, !dbg !24
+    br i1 %tobool, label %if.end, label %if.then, !dbg !26
+  
+  if.then:                                          ; preds = %entry
+    tail call void @llvm.dbg.value(metadata i32 %i, i64 0, metadata !12, metadata !13) #4, !dbg !27
+    tail call void @sink(i32 %i) #4, !dbg !29
+    br label %if.end, !dbg !30
+  
+  if.end:                                           ; preds = %if.then, %entry
+    tail call void @llvm.dbg.value(metadata i32 %i, i64 0, metadata !12, metadata !13) #4, !dbg !31
+    tail call void @sink(i32 %i) #4, !dbg !33
+    ret void, !dbg !34
+  }
+  
+  ; Function Attrs: nounwind readnone
+  declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #3
+  
+  ; Function Attrs: nounwind
+  declare void @llvm.stackprotector(i8*, i8**) #4
+  
+  attributes #0 = { alwaysinline nounwind ssp uwtable }
+  attributes #2 = { nounwind ssp uwtable }
+  attributes #3 = { nounwind readnone }
+  attributes #4 = { nounwind }
+  
+  !llvm.dbg.cu = !{!0}
+  !llvm.module.flags = !{!3, !4, !5}
+  !llvm.ident = !{!6}
+  
+  !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 4.0.0 (trunk 281923) (llvm/trunk 281916)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
+  !1 = !DIFile(filename: "livedebugvalues-limit.c", directory: "/Volumes/Fusion/Data/llvm")
+  !2 = !{}
+  !3 = !{i32 2, !"Dwarf Version", i32 4}
+  !4 = !{i32 2, !"Debug Info Version", i32 3}
+  !5 = !{i32 1, !"PIC Level", i32 2}
+  !6 = !{!"clang version 4.0.0 (trunk 281923) (llvm/trunk 281916)"}
+  !7 = distinct !DISubprogram(name: "f", scope: !1, file: !1, line: 3, type: !8, isLocal: false, isDefinition: true, scopeLine: 3, flags: DIFlagPrototyped, isOptimized: true, unit: !0, variables: !11)
+  !8 = !DISubroutineType(types: !9)
+  !9 = !{null, !10}
+  !10 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+  !11 = !{!12}
+  !12 = !DILocalVariable(name: "a", arg: 1, scope: !7, file: !1, line: 3, type: !10)
+  !13 = !DIExpression()
+  !14 = !DILocation(line: 3, column: 41, scope: !7)
+  !15 = !DILocation(line: 3, column: 46, scope: !7)
+  !16 = !DILocation(line: 3, column: 55, scope: !7)
+  !17 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 4, type: !8, isLocal: false, isDefinition: true, scopeLine: 4, flags: DIFlagPrototyped, isOptimized: true, unit: !0, variables: !18)
+  !18 = !{!19}
+  !19 = !DILocalVariable(name: "i", arg: 1, scope: !17, file: !1, line: 4, type: !10)
+  !20 = !DILocation(line: 4, column: 14, scope: !17)
+  !21 = !DILocation(line: 3, column: 41, scope: !7, inlinedAt: !22)
+  !22 = distinct !DILocation(line: 5, column: 3, scope: !17)
+  !23 = !DILocation(line: 3, column: 46, scope: !7, inlinedAt: !22)
+  !24 = !DILocation(line: 6, column: 7, scope: !25)
+  !25 = distinct !DILexicalBlock(scope: !17, file: !1, line: 6, column: 7)
+  !26 = !DILocation(line: 6, column: 7, scope: !17)
+  !27 = !DILocation(line: 3, column: 41, scope: !7, inlinedAt: !28)
+  !28 = distinct !DILocation(line: 7, column: 5, scope: !25)
+  !29 = !DILocation(line: 3, column: 46, scope: !7, inlinedAt: !28)
+  !30 = !DILocation(line: 7, column: 5, scope: !25)
+  !31 = !DILocation(line: 3, column: 41, scope: !7, inlinedAt: !32)
+  !32 = distinct !DILocation(line: 8, column: 3, scope: !17)
+  !33 = !DILocation(line: 3, column: 46, scope: !7, inlinedAt: !32)
+  !34 = !DILocation(line: 9, column: 1, scope: !17)
+
+...
+---
+name:            f
+alignment:       4
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:         
+  - { reg: '%edi' }
+calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx', 
+                        '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15', 
+                        '%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d', 
+                        '%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ]
+frameInfo:       
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       8
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+fixedStack:      
+  - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
+body:             |
+  bb.0.entry:
+    liveins: %edi, %rbp
+  
+    frame-setup PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp
+    CFI_INSTRUCTION def_cfa_offset 16
+    CFI_INSTRUCTION offset %rbp, -16
+    %rbp = frame-setup MOV64rr %rsp
+    CFI_INSTRUCTION def_cfa_register %rbp
+    DBG_VALUE debug-use %edi, debug-use _, !12, !13, debug-location !14
+    %rbp = POP64r implicit-def %rsp, implicit %rsp, debug-location !15
+    TAILJMPd64 @sink, csr_64, implicit %rsp, implicit %rsp, implicit %edi, debug-location !15
+
+...
+---
+name:            foo
+alignment:       4
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:         
+  - { reg: '%edi' }
+calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx', 
+                        '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15', 
+                        '%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d', 
+                        '%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ]
+frameInfo:       
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       24
+  offsetAdjustment: -8
+  maxAlignment:    0
+  adjustsStack:    true
+  hasCalls:        true
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+fixedStack:      
+  - { id: 0, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '%rbx' }
+  - { id: 1, type: spill-slot, offset: -16, size: 8, alignment: 16 }
+body:             |
+  bb.0.entry:
+    successors: %bb.2.if.end, %bb.1.if.then
+    liveins: %edi, %rbx, %rbp
+  
+    frame-setup PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp
+    CFI_INSTRUCTION def_cfa_offset 16
+    CFI_INSTRUCTION offset %rbp, -16
+    %rbp = frame-setup MOV64rr %rsp
+    CFI_INSTRUCTION def_cfa_register %rbp
+    frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
+    frame-setup PUSH64r undef %rax, implicit-def %rsp, implicit %rsp
+    CFI_INSTRUCTION offset %rbx, -24
+    DBG_VALUE debug-use %edi, debug-use _, !19, !13, debug-location !20
+    %ebx = MOV32rr %edi
+    DBG_VALUE debug-use %ebx, debug-use _, !12, !13, debug-location !21
+    DBG_VALUE debug-use %ebx, debug-use _, !19, !13, debug-location !20
+    CALL64pcrel32 @sink, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, debug-location !23
+    TEST32rr %ebx, %ebx, implicit-def %eflags, debug-location !24
+    JE_1 %bb.2.if.end, implicit %eflags
+  
+  bb.1.if.then:
+    successors: %bb.2.if.end
+    liveins: %ebx, %rbp
+  
+    DBG_VALUE debug-use %ebx, debug-use _, !19, !13, debug-location !20
+    DBG_VALUE debug-use %ebx, debug-use _, !12, !13, debug-location !27
+    %edi = MOV32rr %ebx, debug-location !29
+    CALL64pcrel32 @sink, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, debug-location !29
+  
+  bb.2.if.end:
+    liveins: %ebx, %rbp
+  
+    DBG_VALUE debug-use %ebx, debug-use _, !19, !13, debug-location !20
+    %edi = MOV32rr killed %ebx, debug-location !33
+    %rsp = ADD64ri8 %rsp, 8, implicit-def dead %eflags, debug-location !33
+    DBG_VALUE debug-use %ebx, debug-use _, !12, !13, debug-location !31
+    %rbx = POP64r implicit-def %rsp, implicit %rsp, debug-location !33
+    %rbp = POP64r implicit-def %rsp, implicit %rsp, debug-location !33
+    TAILJMPd64 @sink, csr_64, implicit %rsp, implicit %rsp, implicit %edi, debug-location !33
+
+...
+diff --git a/test/DebugInfo/X86/fission-ranges.ll b/test/DebugInfo/X86/fission-ranges.ll
+index 3c05f223ee79..0dfb13ab66b7 100644
+--- a/test/DebugInfo/X86/fission-ranges.ll
+++ b/test/DebugInfo/X86/fission-ranges.ll
+@@ -32,13 +32,13 @@
+ ; CHECK-NEXT:                    Length: 25
+ ; CHECK-NEXT:      Location description: 50 93 04
+ ; CHECK: [[E]]: Beginning address index: 4
+-; CHECK-NEXT:                    Length: 23
+; CHECK-NEXT:                    Length: 19
+ ; CHECK-NEXT:      Location description: 50 93 04
+ ; CHECK: [[B]]: Beginning address index: 5
+-; CHECK-NEXT:                    Length: 21
+; CHECK-NEXT:                    Length: 17
+ ; CHECK-NEXT:      Location description: 50 93 04
+ ; CHECK: [[D]]: Beginning address index: 6
+-; CHECK-NEXT:                    Length: 21
+; CHECK-NEXT:                    Length: 17
+ ; CHECK-NEXT:      Location description: 50 93 04
+ 
+ ; Make sure we don't produce any relocations in any .dwo section (though in particular, debug_info.dwo)
+-- 
+2.7.4
+
--- a/rust-lang-llvm-pr54.patch
+++ b/rust-lang-llvm-pr54.patch
@ -0,0 +1,103 @@
+From 9b74379db3f9e30516f053138fd3697d42b23164 Mon Sep 17 00:00:00 2001
+From: David Majnemer <david.majnemer@gmail.com>
+Date: Fri, 7 Oct 2016 01:38:35 +0000
+Subject: [rust-lang/llvm#54] [SimplifyCFG] Correctly test for unconditional
+ branches in GetCaseResults
+
+GetCaseResults assumed that a terminator with one successor was an
+unconditional branch.  This is not necessarily the case, it could be a
+cleanupret.
+
+Strengthen the check by querying whether or not the terminator is
+exceptional.
+
+git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283517 91177308-0d34-0410-b5e6-96231b3b80d8
+---
+ lib/Transforms/Utils/SimplifyCFG.cpp               |  2 +-
+ .../SimplifyCFG/X86/switch_to_lookup_table.ll      | 60 ++++++++++++++++++++++
+ 2 files changed, 61 insertions(+), 1 deletion(-)
+
+diff --git a/lib/Transforms/Utils/SimplifyCFG.cpp b/lib/Transforms/Utils/SimplifyCFG.cpp
+index c197317ac771..d274f97296dc 100644
+--- a/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/lib/Transforms/Utils/SimplifyCFG.cpp
+@@ -4228,7 +4228,7 @@ GetCaseResults(SwitchInst *SI, ConstantInt *CaseVal, BasicBlock *CaseDest,
+        ++I) {
+     if (TerminatorInst *T = dyn_cast<TerminatorInst>(I)) {
+       // If the terminator is a simple branch, continue to the next block.
+-      if (T->getNumSuccessors() != 1)
+      if (T->getNumSuccessors() != 1 || T->isExceptional())
+         return false;
+       Pred = CaseDest;
+       CaseDest = T->getSuccessor(0);
+diff --git a/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll b/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll
+index bae8c1dc5a4b..77e355a00528 100644
+--- a/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll
+++ b/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll
+@@ -1334,3 +1334,63 @@ cleanup4:
+   br label %while.body
+ }
+ 
+declare void @throw(i1)
+
+define void @wineh_test(i64 %val) personality i32 (...)* @__CxxFrameHandler3 {
+entry:
+  invoke void @throw(i1 false)
+          to label %unreachable unwind label %cleanup1
+
+unreachable:
+  unreachable
+
+cleanup1:
+  %cleanuppad1 = cleanuppad within none []
+  switch i64 %val, label %cleanupdone2 [
+    i64 0, label %cleanupdone1
+    i64 1, label %cleanupdone1
+    i64 6, label %cleanupdone1
+  ]
+
+cleanupdone1:
+  cleanupret from %cleanuppad1 unwind label %cleanup2
+
+cleanupdone2:
+  cleanupret from %cleanuppad1 unwind label %cleanup2
+
+cleanup2:
+  %phi = phi i1 [ true, %cleanupdone1 ], [ false, %cleanupdone2 ]
+  %cleanuppad2 = cleanuppad within none []
+  call void @throw(i1 %phi) [ "funclet"(token %cleanuppad2) ]
+  unreachable
+}
+
+; CHECK-LABEL: @wineh_test(
+; CHECK: entry:
+; CHECK:   invoke void @throw(i1 false)
+; CHECK:           to label %[[unreachable:.*]] unwind label %[[cleanup1:.*]]
+
+; CHECK: [[unreachable]]:
+; CHECK:   unreachable
+
+; CHECK: [[cleanup1]]:
+; CHECK:   %[[cleanuppad1:.*]] = cleanuppad within none []
+; CHECK:   switch i64 %val, label %[[cleanupdone2:.*]] [
+; CHECK:     i64 0, label %[[cleanupdone1:.*]]
+; CHECK:     i64 1, label %[[cleanupdone1]]
+; CHECK:     i64 6, label %[[cleanupdone1]]
+; CHECK:   ]
+
+; CHECK: [[cleanupdone1]]:
+; CHECK:   cleanupret from %[[cleanuppad1]] unwind label %[[cleanup2:.*]]
+
+; CHECK: [[cleanupdone2]]:
+; CHECK:   cleanupret from %[[cleanuppad1]] unwind label %[[cleanup2]]
+
+; CHECK: [[cleanup2]]:
+; CHECK:   %[[phi:.*]] = phi i1 [ true, %[[cleanupdone1]] ], [ false, %[[cleanupdone2]] ]
+; CHECK:   %[[cleanuppad2:.*]] = cleanuppad within none []
+; CHECK:   call void @throw(i1 %[[phi]]) [ "funclet"(token %[[cleanuppad2]]) ]
+; CHECK:   unreachable
+
+declare i32 @__CxxFrameHandler3(...)
+-- 
+2.7.4
+
--- a/rust-lang-llvm-pr55.patch
+++ b/rust-lang-llvm-pr55.patch
@ -0,0 +1,85 @@
+From eff5dc809ed54701f2bb3e15c58d01881299cedf Mon Sep 17 00:00:00 2001
+From: David Majnemer <david.majnemer@gmail.com>
+Date: Tue, 11 Oct 2016 01:00:45 +0000
+Subject: [rust-lang/llvm#55] [InstCombine] Transform !range metadata to
+ !nonnull when combining loads
+
+When combining an integer load with !range metadata that does not include 0 to a pointer load, make sure emit !nonnull metadata on the newly-created pointer load. This prevents the !nonnull metadata from being dropped during a ptrtoint/inttoptr pair.
+
+This fixes PR30597.
+
+Patch by Ariel Ben-Yehuda!
+
+Differential Revision: https://reviews.llvm.org/D25215
+
+git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283836 91177308-0d34-0410-b5e6-96231b3b80d8
+---
+ .../InstCombine/InstCombineLoadStoreAlloca.cpp     | 12 ++++++--
+ test/Transforms/InstCombine/PR30597.ll             | 32 ++++++++++++++++++++++
+ 2 files changed, 42 insertions(+), 2 deletions(-)
+ create mode 100644 test/Transforms/InstCombine/PR30597.ll
+
+diff --git a/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp b/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
+index d312983ed51b..26f4e764501a 100644
+--- a/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
+++ b/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
+@@ -380,8 +380,16 @@ static LoadInst *combineLoadToNewType(InstCombiner &IC, LoadInst &LI, Type *NewT
+       break;
+     case LLVMContext::MD_range:
+       // FIXME: It would be nice to propagate this in some way, but the type
+-      // conversions make it hard. If the new type is a pointer, we could
+-      // translate it to !nonnull metadata.
+      // conversions make it hard.
+
+      // If it's a pointer now and the range does not contain 0, make it !nonnull.
+      if (NewTy->isPointerTy()) {
+        unsigned BitWidth = IC.getDataLayout().getTypeSizeInBits(NewTy);
+        if (!getConstantRangeFromMetadata(*N).contains(APInt(BitWidth, 0))) {
+          MDNode *NN = MDNode::get(LI.getContext(), None);
+          NewLoad->setMetadata(LLVMContext::MD_nonnull, NN);
+        }
+      }
+       break;
+     }
+   }
+diff --git a/test/Transforms/InstCombine/PR30597.ll b/test/Transforms/InstCombine/PR30597.ll
+new file mode 100644
+index 000000000000..c0803ed71204
+--- /dev/null
+++ b/test/Transforms/InstCombine/PR30597.ll
+@@ -0,0 +1,32 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+; Function Attrs: readonly uwtable
+define i1 @dot_ref_s(i32** noalias nocapture readonly dereferenceable(8)) {
+entry-block:
+  %loadedptr = load i32*, i32** %0, align 8, !nonnull !0
+  %ptrtoint = ptrtoint i32* %loadedptr to i64
+  %inttoptr = inttoptr i64 %ptrtoint to i32*
+  %switchtmp = icmp eq i32* %inttoptr, null
+  ret i1 %switchtmp
+
+; CHECK-LABEL: @dot_ref_s
+; CHECK-NEXT: entry-block:
+; CHECK-NEXT: ret i1 false
+}
+
+; Function Attrs: readonly uwtable
+define i64* @function(i64* noalias nocapture readonly dereferenceable(8)) {
+entry-block:
+  %loaded = load i64, i64* %0, align 8, !range !1
+  %inttoptr = inttoptr i64 %loaded to i64*
+  ret i64* %inttoptr
+; CHECK-LABEL: @function
+; CHECK: %{{.+}} = load i64*, i64** %{{.+}}, align 8, !nonnull
+}
+
+
+!0 = !{}
+!1 = !{i64 1, i64 140737488355327}
+-- 
+2.9.3
+
--- a/rust-lang-llvm-pr57.patch
+++ b/rust-lang-llvm-pr57.patch
@ -0,0 +1,118 @@
+From 5ac4f80be3e8b5d42475aeaba246455e0016c7ef Mon Sep 17 00:00:00 2001
+From: Anthony Ramine <n.oxyde@gmail.com>
+Date: Sun, 27 Nov 2016 16:28:12 +0100
+Subject: [rust-lang/llvm#57] Backport rL277331
+
+---
+ lib/Target/AArch64/AArch64InstrInfo.cpp            |  3 +
+ .../MIR/AArch64/inst-size-tlsdesc-callseq.mir      | 84 ++++++++++++++++++++++
+ 2 files changed, 87 insertions(+)
+ create mode 100644 test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir
+
+diff --git a/lib/Target/AArch64/AArch64InstrInfo.cpp b/lib/Target/AArch64/AArch64InstrInfo.cpp
+index 0aa4708f35ac..d39542a8e4eb 100644
+--- a/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/lib/Target/AArch64/AArch64InstrInfo.cpp
+@@ -56,6 +56,9 @@ unsigned AArch64InstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const {
+   case TargetOpcode::IMPLICIT_DEF:
+   case TargetOpcode::KILL:
+     return 0;
+  case AArch64::TLSDESC_CALLSEQ:
+    // This gets lowered to an instruction sequence which takes 16 bytes
+    return 16;
+   }
+ 
+   llvm_unreachable("GetInstSizeInBytes()- Unable to determin insn size");
+diff --git a/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir b/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir
+new file mode 100644
+index 000000000000..2d966ece768e
+--- /dev/null
+++ b/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir
+@@ -0,0 +1,84 @@
+# RUN: llc -mtriple=aarch64-unknown -run-pass aarch64-branch-relax -aarch64-tbz-offset-bits=4 %s -o - | FileCheck %s
+--- |
+  ; ModuleID = 'test.ll'
+  source_filename = "test.ll"
+  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+  target triple = "aarch64-unknown"
+
+  @ThreadLocalGlobal = external thread_local local_unnamed_addr global i32, align 8
+
+  define i32 @test_tlsdesc_callseq_length(i32 %in) {
+    %val = and i32 %in, 1
+    %tst = icmp eq i32 %val, 0
+    br i1 %tst, label %true, label %false
+
+  true:                                             ; preds = %0
+    %1 = load i32, i32* @ThreadLocalGlobal, align 8
+    ret i32 %1
+
+  false:                                            ; preds = %0
+    ret i32 0
+  }
+
+...
+---
+# CHECK-LABEL: name:{{.*}}test_tlsdesc_callseq_length
+# If the size of TLSDESC_CALLSEQ is computed correctly, that will push
+# the bb.2.false block too far away from the TBNZW, so the branch will
+# have to be relaxed (note that we're using -aarch64-tbz-offset-bits to
+# constrain the range that can be reached with the TBNZW to something smaller
+# than what TLSDESC_CALLSEQ is lowered to).
+# CHECK: TBZW killed %w0, 0, %bb.1.true
+# CHECK: B %bb.2.false
+name:            test_tlsdesc_callseq_length
+alignment:       2
+exposesReturnsTwice: false
+hasInlineAsm:    false
+allVRegsAllocated: true
+isSSA:           false
+tracksRegLiveness: false
+tracksSubRegLiveness: false
+liveins:
+  - { reg: '%w0' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       16
+  offsetAdjustment: 0
+  maxAlignment:    16
+  adjustsStack:    false
+  hasCalls:        true
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+stack:
+  - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%lr' }
+body:             |
+  bb.0 (%ir-block.0):
+    successors: %bb.1.true, %bb.2.false
+    liveins: %w0, %lr
+
+    TBNZW killed %w0, 0, %bb.2.false
+
+  bb.1.true:
+    liveins: %lr
+
+    early-clobber %sp = frame-setup STRXpre killed %lr, %sp, -16 :: (store 8 into %stack.0)
+    frame-setup CFI_INSTRUCTION def_cfa_offset 16
+    frame-setup CFI_INSTRUCTION offset %w30, -16
+    TLSDESC_CALLSEQ target-flags(aarch64-tls) @ThreadLocalGlobal, implicit-def dead %lr, implicit-def %x0, implicit-def dead %x1
+    %x8 = MRS 56962
+    %w0 = LDRWroX killed %x8, killed %x0, 0, 0 :: (load 4 from @ThreadLocalGlobal, align 8)
+    early-clobber %sp, %lr = LDRXpost %sp, 16 :: (load 8 from %stack.0)
+    RET killed %lr, implicit killed %w0
+
+  bb.2.false:
+    liveins: %lr
+
+    %w0 = ORRWrs %wzr, %wzr, 0
+    RET killed %lr, implicit killed %w0
+
+...
+-- 
+2.9.3
+
--- a/rust-lang-llvm-pr67.patch
+++ b/rust-lang-llvm-pr67.patch
@ -0,0 +1,70 @@
+From a6fa10c14649c18d299cddf3e823b032460cb6f5 Mon Sep 17 00:00:00 2001
+From: Pirama Arumuga Nainar <pirama@google.com>
+Date: Thu, 23 Mar 2017 16:47:47 +0000
+Subject: [PATCH] Fix computeKnownBits for ARMISD::CMOV
+
+Summary:
+The true and false operands for the CMOV are operands 0 and 1.
+ARMISelLowering.cpp::computeKnownBits was looking at operands 1 and 2
+instead.  This can cause CMOV instructions to be incorrectly folded into
+BFI if value set by the CMOV is another CMOV, whose known bits are
+computed incorrectly.
+
+This patch fixes the issue and adds a test case.
+
+Reviewers: kristof.beyls, jmolloy
+
+Subscribers: llvm-commits, aemerson, srhines, rengolin
+
+Differential Revision: https://reviews.llvm.org/D31265
+
+git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298624 91177308-0d34-0410-b5e6-96231b3b80d8
+---
+ lib/Target/ARM/ARMISelLowering.cpp |  4 ++--
+ test/CodeGen/ARM/no-cmov2bfi.ll    | 19 +++++++++++++++++++
+ 2 files changed, 21 insertions(+), 2 deletions(-)
+ create mode 100644 test/CodeGen/ARM/no-cmov2bfi.ll
+
+diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
+index 4a227a3cd7b1..cf98e60c0657 100644
+--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
+@@ -10806,8 +10806,8 @@ static void computeKnownBits(SelectionDAG &DAG, SDValue Op, APInt &KnownZero,
+   if (Op.getOpcode() == ARMISD::CMOV) {
+     APInt KZ2(KnownZero.getBitWidth(), 0);
+     APInt KO2(KnownOne.getBitWidth(), 0);
+-    computeKnownBits(DAG, Op.getOperand(1), KnownZero, KnownOne);
+-    computeKnownBits(DAG, Op.getOperand(2), KZ2, KO2);
+    computeKnownBits(DAG, Op.getOperand(0), KnownZero, KnownOne);
+    computeKnownBits(DAG, Op.getOperand(1), KZ2, KO2);
+ 
+     KnownZero &= KZ2;
+     KnownOne &= KO2;
+diff --git a/test/CodeGen/ARM/no-cmov2bfi.ll b/test/CodeGen/ARM/no-cmov2bfi.ll
+new file mode 100644
+index 000000000000..c8b512048905
+--- /dev/null
+++ b/test/CodeGen/ARM/no-cmov2bfi.ll
+@@ -0,0 +1,19 @@
+; RUN: llc < %s -mtriple=thumbv7 | FileCheck --check-prefix=CHECK-NOBFI %s
+
+declare zeroext i1 @dummy()
+
+define i8 @test(i8 %a1, i1 %c) {
+; CHECK-NOBFI-NOT: bfi
+; CHECK-NOBFI: bl      dummy
+; CHECK-NOBFI: cmp     r0, #0
+; CHECK-NOBFI: it      ne
+; CHECK-NOBFI: orrne   [[REG:r[0-9]+]], [[REG]], #8
+; CHECK-NOBFI: mov     r0, [[REG]]
+
+  %1 = and i8 %a1, -9
+  %2 = select i1 %c, i8 %1, i8 %a1
+  %3 = tail call zeroext i1 @dummy()
+  %4 = or i8 %2, 8
+  %ret = select i1 %3, i8 %4, i8 %2
+  ret i8 %ret
+}
+-- 
+2.9.3
+
--- a/3
+++ b/3
@ -1,2 +1 @@
-SHA512 (llvm-10.0.0.src.tar.xz) = 7dc961aacee3a01ecc002ff2b688a2ef50661856d2abd5ecc90566ffcad7566e4976736cd339ea96592e452cd5a17aaceba9712b2effec805661cca8ff020ee7
-SHA512 (llvm-10.0.0.src.tar.xz.sig) = 2e4c61af5d84db4bc7a8ab51367210c529ae02e401b7a73a449f79bf9d92654ccf36fdef0f552c8850df0e94bcafce2359180ad0cdf720be7c874a782a936878
+SHA512 (llvm-3.9.1.src.tar.xz) = 50cbe8ee911080f586e77861c442348701bd02e2de0c090c54c34f82ac275ecfcd712af0f41e387c33b4a6057778a4258a27554292fe68ab4af3fd9dd6d90683
--- a/tests/.fmf/version
+++ b/tests/.fmf/version
@ -1 +0,0 @@
-1
--- a/tests/build-compat/runtest.sh
+++ b/tests/build-compat/runtest.sh
@ -1,16 +0,0 @@
-#!/bin/bash
-
-set -ex
-
-dnf download --disablerepo=* --enablerepo=test-llvm --source llvm
-
-# The src.rpm is available in the directory the test run from.
-set +e
-mock --resultdir=. --old-chroot --with compat_build --rebuild *.src.rpm
-if [ $? -ne 0 ]; then
-  cat root.log
-  cat build.log
-  exit 1
-fi
-
-exit 0
--- a/tests/provision.fmf
+++ b/tests/provision.fmf
@ -1,5 +0,0 @@
---
-
-standard-inventory-qcow2:
-  qemu:
-    m: 2G
--- a/tests/tests.yml
+++ b/tests/tests.yml
@ -1,30 +0,0 @@
- hosts: localhost
-  roles:
-  - role: standard-test-basic
-    tags:
-      - classic
-    required_packages:
-      - llvm-test
-      - rust
-      - cargo
-    tests:
-      - regression-tests:
-          dir: ./
-          run: /usr/libexec/tests/llvm/run-lit-tests --threads 1
-      - rust-sanity:
-          dir: ./
-          run: cargo new hello && cd hello && cargo run
-      # There is a bug in the build process when it runs out of disk space
-      # while stripping binaries, which causes the strip to fail, but does
-      # not fail the build.  This results in a libLLVM.so that is over 2GB
-      # which breaks the nightly compose.  So this test checks that libLLVM.so
-      # is less than 100MB to ensure it was successfully stripped.
-      # https://bugzilla.redhat.com/show_bug.cgi?id=1793250
-      - libllvm-size:
-        dir: ./
-        run: test `stat -L -c %s /usr/lib64/libLLVM.so` -lt 100000000
-      # This test ensures that the spec file still builds correctly with
-      # %global compat_build 1
-      # FIXME: This fails, because the CI system has a hard-coded timeout of 4
-      # hours.
-      #- build-compat
--- a/tests/testsllvm-devel.yml
+++ b/tests/testsllvm-devel.yml
@ -1,31 +0,0 @@
- hosts: localhost
-  pre_tasks:
-  # Make sure we uninstall all sub-packages, so we can test that the cmake files
-  # in llvm-devel are useable when only llvm-devel is installed.
-  - name: Uninstall llvm sub-packages
-    package:
-      name: "{{ item }}"
-      state: absent
-    tags: classic
-    with_items:
-      - llvm
-      - llvm-devel
-      - llvm-doc
-      - llvm-googletest
-      - llvm-libs
-      - llvm-static
-      - llvm-test
-  roles:
-  - role: standard-test-basic
-    tags: classic
-    required_packages:
-      - llvm-devel
-      - cmake
-      - ninja-build
-      - gcc
-      - gcc-c++
-    repositories:
-      - repo: "https://src.fedoraproject.org/tests/llvm.git"
-        dest: "llvm"
-    tests:
-      - llvm/llvm-devel-cmake
Author	SHA1	Message	Date
Tom Stellard	ba5828ebf4	Backport r291084 (rhbz1435545)	2017-08-25 18:57:25 +00:00
Tom Stellard	55141ad131	Fix %postun step for -devel package (rhbz 1403539)	2017-08-25 13:42:30 +00:00
Josh Stone	148867a9bd	Fix computeKnownBits for ARMISD::CMOV (rust-lang/llvm#67 )	2017-04-18 15:03:45 -07:00
Peter Robinson	1375e73fbd	Fix missing mask on relocation for aarch64 (rhbz 1429050), Disable failing tests on ARM.	2017-03-17 20:05:54 +00:00
Dave Airlie	3f05135289	Merge branch 'master' into f25 Bring in 3.9.1	2017-03-01 15:46:03 +10:00
Josh Stone	210cd876b6	disable sphinx warnings-as-errors	2017-01-06 17:56:22 -08:00
Josh Stone	74fef128e4	Support s390x atomic fence	2017-01-06 17:39:56 -08:00