Compare commits
7 Commits
| Author | SHA1 | Date |
|---|---|---|
Tom Stellard
|
ba5828ebf4 | |
|
Tom Stellard
|
55141ad131 | |
Josh Stone
|
148867a9bd | |
Peter Robinson
|
1375e73fbd | |
Dave Airlie
|
3f05135289 | |
|
Josh Stone
|
210cd876b6 | |
|
Josh Stone
|
74fef128e4 |
|
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@ -0,0 +1,435 @@
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From 29cf3bd00fe84ddab138c9311fe288bb9da8a273 Mon Sep 17 00:00:00 2001
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From: root <root@mammon-seattle-raw.austin.arm.com>
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Date: Thu, 9 Mar 2017 12:22:48 -0600
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Subject: [PATCH] Fix R_AARCH64_MOVW_UABS_G3 relocation
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|
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Summary: The relocation is missing mask so an address that
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has non-zero bits in 47:43 may overwrite the register
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number. (Frequently shows up as target register changed
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to xzr....)
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Reviewers: t.p.northover, lhames
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Subscribers: davide, aemerson, rengolin, llvm-commits
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Differential Revision: https://reviews.llvm.org/D27609
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---
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llvm-3.9.1.src/include/llvm/Object/ELFObjectFile.h | 2 +-
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llvm-3.9.1.src/include/llvm/Object/RelocVisitor.h | 1 +
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.../ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp | 67 +++++++++-----
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.../RuntimeDyld/AArch64/ELF_ARM64_BE-relocations.s | 102 +++++++++++++++++++++
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.../RuntimeDyld/AArch64/ELF_ARM64_relocations.s | 99 ++++++++++++++++++++
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5 files changed, 249 insertions(+), 22 deletions(-)
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create mode 100644 llvm-3.9.1.src/test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_BE-relocations.s
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create mode 100644 llvm-3.9.1.src/test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_relocations.s
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diff --git a/llvm-3.9.1.src/include/llvm/Object/ELFObjectFile.h b/llvm-3.9.1.src/include/llvm/Object/ELFObjectFile.h
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index 07c6364..d3b83f9 100644
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--- a/llvm-3.9.1.src/include/llvm/Object/ELFObjectFile.h
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+++ b/llvm-3.9.1.src/include/llvm/Object/ELFObjectFile.h
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@@ -907,7 +907,7 @@ unsigned ELFObjectFile<ELFT>::getArch() const {
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case ELF::EM_X86_64:
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return Triple::x86_64;
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case ELF::EM_AARCH64:
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- return Triple::aarch64;
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+ return IsLittleEndian ? Triple::aarch64 : Triple::aarch64_be;
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case ELF::EM_ARM:
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return Triple::arm;
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case ELF::EM_AVR:
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diff --git a/llvm-3.9.1.src/include/llvm/Object/RelocVisitor.h b/llvm-3.9.1.src/include/llvm/Object/RelocVisitor.h
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index 5e0df98..b59e8ec 100644
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--- a/llvm-3.9.1.src/include/llvm/Object/RelocVisitor.h
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+++ b/llvm-3.9.1.src/include/llvm/Object/RelocVisitor.h
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@@ -86,6 +86,7 @@ private:
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return RelocToApply();
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}
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case Triple::aarch64:
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+ case Triple::aarch64_be:
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switch (RelocType) {
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case llvm::ELF::R_AARCH64_ABS32:
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return visitELF_AARCH64_ABS32(R, Value);
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diff --git a/llvm-3.9.1.src/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp b/llvm-3.9.1.src/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
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index 9cbdb13..9e04b5d 100644
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--- a/llvm-3.9.1.src/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
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+++ b/llvm-3.9.1.src/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
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@@ -309,6 +309,8 @@ void RuntimeDyldELF::resolveAArch64Relocation(const SectionEntry &Section,
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uint32_t *TargetPtr =
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reinterpret_cast<uint32_t *>(Section.getAddressWithOffset(Offset));
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uint64_t FinalAddress = Section.getLoadAddressWithOffset(Offset);
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+ // Data should use target endian. Code should always use little endian.
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+ bool isBE = Arch == Triple::aarch64_be;
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DEBUG(dbgs() << "resolveAArch64Relocation, LocalAddress: 0x"
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<< format("%llx", Section.getAddressWithOffset(Offset))
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@@ -324,14 +326,22 @@ void RuntimeDyldELF::resolveAArch64Relocation(const SectionEntry &Section,
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case ELF::R_AARCH64_ABS64: {
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uint64_t *TargetPtr =
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reinterpret_cast<uint64_t *>(Section.getAddressWithOffset(Offset));
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- *TargetPtr = Value + Addend;
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+ if (isBE)
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+ support::ubig64_t::ref{TargetPtr} = Value + Addend;
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+ else
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+ support::ulittle64_t::ref{TargetPtr} = Value + Addend;
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break;
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}
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case ELF::R_AARCH64_PREL32: {
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uint64_t Result = Value + Addend - FinalAddress;
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assert(static_cast<int64_t>(Result) >= INT32_MIN &&
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static_cast<int64_t>(Result) <= UINT32_MAX);
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- *TargetPtr = static_cast<uint32_t>(Result & 0xffffffffU);
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+ if (isBE)
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+ support::ubig32_t::ref{TargetPtr} =
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+ static_cast<uint32_t>(Result & 0xffffffffU);
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+ else
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+ support::ulittle32_t::ref{TargetPtr} =
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+ static_cast<uint32_t>(Result & 0xffffffffU);
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break;
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||||
}
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case ELF::R_AARCH64_CALL26: // fallthrough
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@@ -339,6 +349,7 @@ void RuntimeDyldELF::resolveAArch64Relocation(const SectionEntry &Section,
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||||
// Operation: S+A-P. Set Call or B immediate value to bits fff_fffc of the
|
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// calculation.
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uint64_t BranchImm = Value + Addend - FinalAddress;
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+ uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
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// "Check that -2^27 <= result < 2^27".
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assert(isInt<28>(BranchImm));
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@@ -352,91 +363,105 @@ void RuntimeDyldELF::resolveAArch64Relocation(const SectionEntry &Section,
|
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}
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case ELF::R_AARCH64_MOVW_UABS_G3: {
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uint64_t Result = Value + Addend;
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+ uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
|
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// AArch64 code is emitted with .rela relocations. The data already in any
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// bits affected by the relocation on entry is garbage.
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- *TargetPtr &= 0xffe0001fU;
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+ TargetValue &= 0xffe0001fU;
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// Immediate goes in bits 20:5 of MOVZ/MOVK instruction
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- *TargetPtr |= Result >> (48 - 5);
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+ TargetValue |= ((Result & 0xffff000000000000ULL) >> (48 - 5));
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// Shift must be "lsl #48", in bits 22:21
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- assert((*TargetPtr >> 21 & 0x3) == 3 && "invalid shift for relocation");
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+ assert((TargetValue >> 21 & 0x3) == 3 && "invalid shift for relocation");
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+ support::ulittle32_t::ref{TargetPtr} = TargetValue;
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break;
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}
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case ELF::R_AARCH64_MOVW_UABS_G2_NC: {
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uint64_t Result = Value + Addend;
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+ uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
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// AArch64 code is emitted with .rela relocations. The data already in any
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// bits affected by the relocation on entry is garbage.
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- *TargetPtr &= 0xffe0001fU;
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+ TargetValue &= 0xffe0001fU;
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||||
// Immediate goes in bits 20:5 of MOVZ/MOVK instruction
|
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- *TargetPtr |= ((Result & 0xffff00000000ULL) >> (32 - 5));
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+ TargetValue |= ((Result & 0xffff00000000ULL) >> (32 - 5));
|
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// Shift must be "lsl #32", in bits 22:21
|
||||
- assert((*TargetPtr >> 21 & 0x3) == 2 && "invalid shift for relocation");
|
||||
+ assert((TargetValue >> 21 & 0x3) == 2 && "invalid shift for relocation");
|
||||
+ support::ulittle32_t::ref{TargetPtr} = TargetValue;
|
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break;
|
||||
}
|
||||
case ELF::R_AARCH64_MOVW_UABS_G1_NC: {
|
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uint64_t Result = Value + Addend;
|
||||
+ uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
|
||||
|
||||
// AArch64 code is emitted with .rela relocations. The data already in any
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||||
// bits affected by the relocation on entry is garbage.
|
||||
- *TargetPtr &= 0xffe0001fU;
|
||||
+ TargetValue &= 0xffe0001fU;
|
||||
// Immediate goes in bits 20:5 of MOVZ/MOVK instruction
|
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- *TargetPtr |= ((Result & 0xffff0000U) >> (16 - 5));
|
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+ TargetValue |= ((Result & 0xffff0000U) >> (16 - 5));
|
||||
// Shift must be "lsl #16", in bits 22:2
|
||||
- assert((*TargetPtr >> 21 & 0x3) == 1 && "invalid shift for relocation");
|
||||
+ assert((TargetValue >> 21 & 0x3) == 1 && "invalid shift for relocation");
|
||||
+ support::ulittle32_t::ref{TargetPtr} = TargetValue;
|
||||
break;
|
||||
}
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case ELF::R_AARCH64_MOVW_UABS_G0_NC: {
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uint64_t Result = Value + Addend;
|
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+ uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
|
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|
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// AArch64 code is emitted with .rela relocations. The data already in any
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// bits affected by the relocation on entry is garbage.
|
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- *TargetPtr &= 0xffe0001fU;
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+ TargetValue &= 0xffe0001fU;
|
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// Immediate goes in bits 20:5 of MOVZ/MOVK instruction
|
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- *TargetPtr |= ((Result & 0xffffU) << 5);
|
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+ TargetValue |= ((Result & 0xffffU) << 5);
|
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// Shift must be "lsl #0", in bits 22:21.
|
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- assert((*TargetPtr >> 21 & 0x3) == 0 && "invalid shift for relocation");
|
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+ assert((TargetValue >> 21 & 0x3) == 0 && "invalid shift for relocation");
|
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+ support::ulittle32_t::ref{TargetPtr} = TargetValue;
|
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break;
|
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}
|
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case ELF::R_AARCH64_ADR_PREL_PG_HI21: {
|
||||
// Operation: Page(S+A) - Page(P)
|
||||
uint64_t Result =
|
||||
((Value + Addend) & ~0xfffULL) - (FinalAddress & ~0xfffULL);
|
||||
+ uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
|
||||
|
||||
// Check that -2^32 <= X < 2^32
|
||||
assert(isInt<33>(Result) && "overflow check failed for relocation");
|
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|
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// AArch64 code is emitted with .rela relocations. The data already in any
|
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// bits affected by the relocation on entry is garbage.
|
||||
- *TargetPtr &= 0x9f00001fU;
|
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+ TargetValue &= 0x9f00001fU;
|
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// Immediate goes in bits 30:29 + 5:23 of ADRP instruction, taken
|
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// from bits 32:12 of X.
|
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- *TargetPtr |= ((Result & 0x3000U) << (29 - 12));
|
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- *TargetPtr |= ((Result & 0x1ffffc000ULL) >> (14 - 5));
|
||||
+ TargetValue |= ((Result & 0x3000U) << (29 - 12));
|
||||
+ TargetValue |= ((Result & 0x1ffffc000ULL) >> (14 - 5));
|
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+ support::ulittle32_t::ref{TargetPtr} = TargetValue;
|
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break;
|
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}
|
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case ELF::R_AARCH64_LDST32_ABS_LO12_NC: {
|
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// Operation: S + A
|
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uint64_t Result = Value + Addend;
|
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+ uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
|
||||
|
||||
// AArch64 code is emitted with .rela relocations. The data already in any
|
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// bits affected by the relocation on entry is garbage.
|
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- *TargetPtr &= 0xffc003ffU;
|
||||
+ TargetValue &= 0xffc003ffU;
|
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// Immediate goes in bits 21:10 of LD/ST instruction, taken
|
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// from bits 11:2 of X
|
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- *TargetPtr |= ((Result & 0xffc) << (10 - 2));
|
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+ TargetValue |= ((Result & 0xffc) << (10 - 2));
|
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+ support::ulittle32_t::ref{TargetPtr} = TargetValue;
|
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break;
|
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}
|
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case ELF::R_AARCH64_LDST64_ABS_LO12_NC: {
|
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// Operation: S + A
|
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uint64_t Result = Value + Addend;
|
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+ uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
|
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|
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// AArch64 code is emitted with .rela relocations. The data already in any
|
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// bits affected by the relocation on entry is garbage.
|
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- *TargetPtr &= 0xffc003ffU;
|
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+ TargetValue &= 0xffc003ffU;
|
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// Immediate goes in bits 21:10 of LD/ST instruction, taken
|
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// from bits 11:3 of X
|
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- *TargetPtr |= ((Result & 0xff8) << (10 - 3));
|
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+ TargetValue |= ((Result & 0xff8) << (10 - 3));
|
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+ support::ulittle32_t::ref{TargetPtr} = TargetValue;
|
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break;
|
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}
|
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}
|
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diff --git a/llvm-3.9.1.src/test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_BE-relocations.s b/llvm-3.9.1.src/test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_BE-relocations.s
|
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new file mode 100644
|
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index 0000000..01d01e5
|
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--- /dev/null
|
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+++ b/llvm-3.9.1.src/test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_BE-relocations.s
|
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@@ -0,0 +1,102 @@
|
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+# RUN: llvm-mc -triple=aarch64_be-none-linux-gnu -filetype=obj -o %T/be-reloc.o %s
|
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+# RUN: llvm-rtdyld -triple=aarch64_be-none-linux-gnu -verify -dummy-extern f=0x0123456789abcdef -check=%s %T/be-reloc.o
|
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+
|
||||
+ .text
|
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+ .globl g
|
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+ .p2align 2
|
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+ .type g,@function
|
||||
+g:
|
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+# R_AARCH64_MOVW_UABS_G3
|
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+ movz x0, #:abs_g3:f
|
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+# R_AARCH64_MOVW_UABS_G2_NC
|
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+ movk x0, #:abs_g2_nc:f
|
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+# R_AARCH64_MOVW_UABS_G1_NC
|
||||
+ movk x0, #:abs_g1_nc:f
|
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+# R_AARCH64_MOVW_UABS_G0_NC
|
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+ movk x0, #:abs_g0_nc:f
|
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+ ret
|
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+ .Lfunc_end0:
|
||||
+ .size g, .Lfunc_end0-g
|
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+
|
||||
+ .type k,@object
|
||||
+ .data
|
||||
+ .globl k
|
||||
+ .p2align 3
|
||||
+k:
|
||||
+ .xword f
|
||||
+ .size k, 8
|
||||
+
|
||||
+# LE instructions read as BE
|
||||
+# rtdyld-check: *{4}(g) = 0x6024e0d2
|
||||
+# rtdyld-check: *{4}(g + 4) = 0xe0acc8f2
|
||||
+# rtdyld-check: *{4}(g + 8) = 0x6035b1f2
|
||||
+# rtdyld-check: *{4}(g + 12) = 0xe0bd99f2
|
||||
+# rtdyld-check: *{8}k = f
|
||||
+# RUN: llvm-mc -triple=aarch64_be-none-linux-gnu -filetype=obj -o %T/be-reloc.o %s
|
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+# RUN: llvm-rtdyld -triple=aarch64_be-none-linux-gnu -verify -dummy-extern f=0x0123456789abcdef -check=%s %T/be-reloc.o
|
||||
+
|
||||
+ .text
|
||||
+ .globl g
|
||||
+ .p2align 2
|
||||
+ .type g,@function
|
||||
+g:
|
||||
+# R_AARCH64_MOVW_UABS_G3
|
||||
+ movz x0, #:abs_g3:f
|
||||
+# R_AARCH64_MOVW_UABS_G2_NC
|
||||
+ movk x0, #:abs_g2_nc:f
|
||||
+# R_AARCH64_MOVW_UABS_G1_NC
|
||||
+ movk x0, #:abs_g1_nc:f
|
||||
+# R_AARCH64_MOVW_UABS_G0_NC
|
||||
+ movk x0, #:abs_g0_nc:f
|
||||
+ ret
|
||||
+ .Lfunc_end0:
|
||||
+ .size g, .Lfunc_end0-g
|
||||
+
|
||||
+ .type k,@object
|
||||
+ .data
|
||||
+ .globl k
|
||||
+ .p2align 3
|
||||
+k:
|
||||
+ .xword f
|
||||
+ .size k, 8
|
||||
+
|
||||
+# LE instructions read as BE
|
||||
+# rtdyld-check: *{4}(g) = 0x6024e0d2
|
||||
+# rtdyld-check: *{4}(g + 4) = 0xe0acc8f2
|
||||
+# rtdyld-check: *{4}(g + 8) = 0x6035b1f2
|
||||
+# rtdyld-check: *{4}(g + 12) = 0xe0bd99f2
|
||||
+# rtdyld-check: *{8}k = f
|
||||
+# RUN: llvm-mc -triple=aarch64_be-none-linux-gnu -filetype=obj -o %T/be-reloc.o %s
|
||||
+# RUN: llvm-rtdyld -triple=aarch64_be-none-linux-gnu -verify -dummy-extern f=0x0123456789abcdef -check=%s %T/be-reloc.o
|
||||
+
|
||||
+ .text
|
||||
+ .globl g
|
||||
+ .p2align 2
|
||||
+ .type g,@function
|
||||
+g:
|
||||
+# R_AARCH64_MOVW_UABS_G3
|
||||
+ movz x0, #:abs_g3:f
|
||||
+# R_AARCH64_MOVW_UABS_G2_NC
|
||||
+ movk x0, #:abs_g2_nc:f
|
||||
+# R_AARCH64_MOVW_UABS_G1_NC
|
||||
+ movk x0, #:abs_g1_nc:f
|
||||
+# R_AARCH64_MOVW_UABS_G0_NC
|
||||
+ movk x0, #:abs_g0_nc:f
|
||||
+ ret
|
||||
+ .Lfunc_end0:
|
||||
+ .size g, .Lfunc_end0-g
|
||||
+
|
||||
+ .type k,@object
|
||||
+ .data
|
||||
+ .globl k
|
||||
+ .p2align 3
|
||||
+k:
|
||||
+ .xword f
|
||||
+ .size k, 8
|
||||
+
|
||||
+# LE instructions read as BE
|
||||
+# rtdyld-check: *{4}(g) = 0x6024e0d2
|
||||
+# rtdyld-check: *{4}(g + 4) = 0xe0acc8f2
|
||||
+# rtdyld-check: *{4}(g + 8) = 0x6035b1f2
|
||||
+# rtdyld-check: *{4}(g + 12) = 0xe0bd99f2
|
||||
+# rtdyld-check: *{8}k = f
|
||||
diff --git a/llvm-3.9.1.src/test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_relocations.s b/llvm-3.9.1.src/test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_relocations.s
|
||||
new file mode 100644
|
||||
index 0000000..e07fa97
|
||||
--- /dev/null
|
||||
+++ b/llvm-3.9.1.src/test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_relocations.s
|
||||
@@ -0,0 +1,99 @@
|
||||
+# RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj -o %T/reloc.o %s
|
||||
+# RUN: llvm-rtdyld -triple=arm64-none-linux-gnu -verify -dummy-extern f=0x0123456789abcdef -check=%s %T/reloc.o
|
||||
+
|
||||
+ .text
|
||||
+ .globl g
|
||||
+ .p2align 2
|
||||
+ .type g,@function
|
||||
+g:
|
||||
+# R_AARCH64_MOVW_UABS_G3
|
||||
+ movz x0, #:abs_g3:f
|
||||
+# R_AARCH64_MOVW_UABS_G2_NC
|
||||
+ movk x0, #:abs_g2_nc:f
|
||||
+# R_AARCH64_MOVW_UABS_G1_NC
|
||||
+ movk x0, #:abs_g1_nc:f
|
||||
+# R_AARCH64_MOVW_UABS_G0_NC
|
||||
+ movk x0, #:abs_g0_nc:f
|
||||
+ ret
|
||||
+ .Lfunc_end0:
|
||||
+ .size g, .Lfunc_end0-g
|
||||
+
|
||||
+ .type k,@object
|
||||
+ .data
|
||||
+ .globl k
|
||||
+ .p2align 3
|
||||
+k:
|
||||
+ .xword f
|
||||
+ .size k, 8
|
||||
+
|
||||
+# rtdyld-check: *{4}(g) = 0xd2e02460
|
||||
+# rtdyld-check: *{4}(g + 4) = 0xf2c8ace0
|
||||
+# rtdyld-check: *{4}(g + 8) = 0xf2b13560
|
||||
+# rtdyld-check: *{4}(g + 12) = 0xf299bde0
|
||||
+# rtdyld-check: *{8}k = f
|
||||
+# RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj -o %T/reloc.o %s
|
||||
+# RUN: llvm-rtdyld -triple=arm64-none-linux-gnu -verify -dummy-extern f=0x0123456789abcdef -check=%s %T/reloc.o
|
||||
+
|
||||
+ .text
|
||||
+ .globl g
|
||||
+ .p2align 2
|
||||
+ .type g,@function
|
||||
+g:
|
||||
+# R_AARCH64_MOVW_UABS_G3
|
||||
+ movz x0, #:abs_g3:f
|
||||
+# R_AARCH64_MOVW_UABS_G2_NC
|
||||
+ movk x0, #:abs_g2_nc:f
|
||||
+# R_AARCH64_MOVW_UABS_G1_NC
|
||||
+ movk x0, #:abs_g1_nc:f
|
||||
+# R_AARCH64_MOVW_UABS_G0_NC
|
||||
+ movk x0, #:abs_g0_nc:f
|
||||
+ ret
|
||||
+ .Lfunc_end0:
|
||||
+ .size g, .Lfunc_end0-g
|
||||
+
|
||||
+ .type k,@object
|
||||
+ .data
|
||||
+ .globl k
|
||||
+ .p2align 3
|
||||
+k:
|
||||
+ .xword f
|
||||
+ .size k, 8
|
||||
+
|
||||
+# rtdyld-check: *{4}(g) = 0xd2e02460
|
||||
+# rtdyld-check: *{4}(g + 4) = 0xf2c8ace0
|
||||
+# rtdyld-check: *{4}(g + 8) = 0xf2b13560
|
||||
+# rtdyld-check: *{4}(g + 12) = 0xf299bde0
|
||||
+# rtdyld-check: *{8}k = f
|
||||
+# RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj -o %T/reloc.o %s
|
||||
+# RUN: llvm-rtdyld -triple=arm64-none-linux-gnu -verify -dummy-extern f=0x0123456789abcdef -check=%s %T/reloc.o
|
||||
+
|
||||
+ .text
|
||||
+ .globl g
|
||||
+ .p2align 2
|
||||
+ .type g,@function
|
||||
+g:
|
||||
+# R_AARCH64_MOVW_UABS_G3
|
||||
+ movz x0, #:abs_g3:f
|
||||
+# R_AARCH64_MOVW_UABS_G2_NC
|
||||
+ movk x0, #:abs_g2_nc:f
|
||||
+# R_AARCH64_MOVW_UABS_G1_NC
|
||||
+ movk x0, #:abs_g1_nc:f
|
||||
+# R_AARCH64_MOVW_UABS_G0_NC
|
||||
+ movk x0, #:abs_g0_nc:f
|
||||
+ ret
|
||||
+ .Lfunc_end0:
|
||||
+ .size g, .Lfunc_end0-g
|
||||
+
|
||||
+ .type k,@object
|
||||
+ .data
|
||||
+ .globl k
|
||||
+ .p2align 3
|
||||
+k:
|
||||
+ .xword f
|
||||
+ .size k, 8
|
||||
+
|
||||
+# rtdyld-check: *{4}(g) = 0xd2e02460
|
||||
+# rtdyld-check: *{4}(g + 4) = 0xf2c8ace0
|
||||
+# rtdyld-check: *{4}(g + 8) = 0xf2b13560
|
||||
+# rtdyld-check: *{4}(g + 12) = 0xf299bde0
|
||||
+# rtdyld-check: *{8}k = f
|
||||
--
|
||||
2.12.0
|
||||
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
From 6974a461b485113b4e6c6ffc668b8fbc9ce45c6e Mon Sep 17 00:00:00 2001
|
||||
From: Craig Topper <craig.topper@gmail.com>
|
||||
Date: Thu, 5 Jan 2017 05:47:29 +0000
|
||||
Subject: [PATCH] [X86] Change getHostCPUName to report Intel model 0x4e as
|
||||
"skylake" instead of "skylake-avx512". Add the proper 0x55 model for
|
||||
"skylake-avx512".
|
||||
|
||||
Summary:
|
||||
Intel's i5-6300U CPU is reporting to have a model id of 78 (4e).
|
||||
The Host detection assumes that to be Skylake Xeon (with AVX512 support),
|
||||
instead of a normal Skylake machine.
|
||||
|
||||
Patch by: Valentin Churavy
|
||||
|
||||
Reviewers: nalimilan, craig.topper
|
||||
|
||||
Subscribers: hfinkel, tkelman, craig.topper, nalimilan, llvm-commits
|
||||
|
||||
Differential Revision: https://reviews.llvm.org/D28221
|
||||
|
||||
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291084 91177308-0d34-0410-b5e6-96231b3b80d8
|
||||
---
|
||||
lib/Support/Host.cpp | 14 +++++++++++---
|
||||
1 file changed, 11 insertions(+), 3 deletions(-)
|
||||
|
||||
diff --git a/lib/Support/Host.cpp b/lib/Support/Host.cpp
|
||||
index 49d0ed5..7593cfc 100644
|
||||
--- a/lib/Support/Host.cpp
|
||||
+++ b/lib/Support/Host.cpp
|
||||
@@ -475,14 +475,22 @@ getIntelProcessorTypeAndSubtype(unsigned int Family, unsigned int Model,
|
||||
|
||||
// Skylake:
|
||||
case 0x4e:
|
||||
- *Type = INTEL_COREI7; // "skylake-avx512"
|
||||
- *Subtype = INTEL_COREI7_SKYLAKE_AVX512;
|
||||
- break;
|
||||
case 0x5e:
|
||||
*Type = INTEL_COREI7; // "skylake"
|
||||
*Subtype = INTEL_COREI7_SKYLAKE;
|
||||
break;
|
||||
|
||||
+ // Skylake Xeon:
|
||||
+ case 0x55:
|
||||
+ *Type = INTEL_COREI7;
|
||||
+ // Check that we really have AVX512
|
||||
+ if (Features & (1 << FEATURE_AVX512)) {
|
||||
+ *Subtype = INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512"
|
||||
+ } else {
|
||||
+ *Subtype = INTEL_COREI7_SKYLAKE; // "skylake"
|
||||
+ }
|
||||
+ break;
|
||||
+
|
||||
case 0x1c: // Most 45 nm Intel Atom processors
|
||||
case 0x26: // 45 nm Atom Lincroft
|
||||
case 0x27: // 32 nm Atom Medfield
|
||||
--
|
||||
1.8.3.1
|
||||
|
||||
|
|
@ -0,0 +1,169 @@
|
|||
Index: llvm/trunk/lib/Target/SystemZ/SystemZAsmPrinter.cpp
|
||||
===================================================================
|
||||
--- llvm/trunk/lib/Target/SystemZ/SystemZAsmPrinter.cpp
|
||||
+++ llvm/trunk/lib/Target/SystemZ/SystemZAsmPrinter.cpp
|
||||
@@ -260,6 +260,11 @@
|
||||
.addImm(15).addReg(SystemZ::R0D);
|
||||
break;
|
||||
|
||||
+ // Emit nothing here but a comment if we can.
|
||||
+ case SystemZ::MemBarrier:
|
||||
+ OutStreamer->emitRawComment("MEMBARRIER");
|
||||
+ return;
|
||||
+
|
||||
default:
|
||||
Lower.lower(MI, LoweredMI);
|
||||
break;
|
||||
Index: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h
|
||||
===================================================================
|
||||
--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h
|
||||
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h
|
||||
@@ -146,6 +146,9 @@
|
||||
// Perform a serialization operation. (BCR 15,0 or BCR 14,0.)
|
||||
SERIALIZE,
|
||||
|
||||
+ // Compiler barrier only; generate a no-op.
|
||||
+ MEMBARRIER,
|
||||
+
|
||||
// Transaction begin. The first operand is the chain, the second
|
||||
// the TDB pointer, and the third the immediate control field.
|
||||
// Returns chain and glue.
|
||||
@@ -479,6 +482,7 @@
|
||||
SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
|
||||
+ SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
|
||||
Index: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
|
||||
===================================================================
|
||||
--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
|
||||
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
|
||||
@@ -216,6 +216,8 @@
|
||||
setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);
|
||||
setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
|
||||
|
||||
+ setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
|
||||
+
|
||||
// z10 has instructions for signed but not unsigned FP conversion.
|
||||
// Handle unsigned 32-bit types as signed 64-bit types.
|
||||
if (!Subtarget.hasFPExtension()) {
|
||||
@@ -3118,6 +3120,25 @@
|
||||
return Op;
|
||||
}
|
||||
|
||||
+SDValue SystemZTargetLowering::lowerATOMIC_FENCE(SDValue Op,
|
||||
+ SelectionDAG &DAG) const {
|
||||
+ SDLoc DL(Op);
|
||||
+ AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
|
||||
+ cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
|
||||
+ SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
|
||||
+ cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
|
||||
+
|
||||
+ // The only fence that needs an instruction is a sequentially-consistent
|
||||
+ // cross-thread fence.
|
||||
+ if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
|
||||
+ return SDValue(DAG.getMachineNode(SystemZ::Serialize, DL, MVT::Other,
|
||||
+ Op.getOperand(0)), 0);
|
||||
+ }
|
||||
+
|
||||
+ // MEMBARRIER is a compiler barrier; it codegens to a no-op.
|
||||
+ return DAG.getNode(SystemZISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
|
||||
+}
|
||||
+
|
||||
// Op is an atomic load. Lower it into a normal volatile load.
|
||||
SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
|
||||
SelectionDAG &DAG) const {
|
||||
@@ -4444,6 +4465,8 @@
|
||||
case ISD::CTTZ_ZERO_UNDEF:
|
||||
return DAG.getNode(ISD::CTTZ, SDLoc(Op),
|
||||
Op.getValueType(), Op.getOperand(0));
|
||||
+ case ISD::ATOMIC_FENCE:
|
||||
+ return lowerATOMIC_FENCE(Op, DAG);
|
||||
case ISD::ATOMIC_SWAP:
|
||||
return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_SWAPW);
|
||||
case ISD::ATOMIC_STORE:
|
||||
@@ -4547,6 +4570,7 @@
|
||||
OPCODE(SEARCH_STRING);
|
||||
OPCODE(IPM);
|
||||
OPCODE(SERIALIZE);
|
||||
+ OPCODE(MEMBARRIER);
|
||||
OPCODE(TBEGIN);
|
||||
OPCODE(TBEGIN_NOFLOAT);
|
||||
OPCODE(TEND);
|
||||
@@ -5307,6 +5331,7 @@
|
||||
MachineBasicBlock *
|
||||
SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
|
||||
MachineBasicBlock *MBB) const {
|
||||
+
|
||||
MachineFunction &MF = *MBB->getParent();
|
||||
const SystemZInstrInfo *TII =
|
||||
static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
|
||||
Index: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
|
||||
===================================================================
|
||||
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
|
||||
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
|
||||
@@ -1231,6 +1231,10 @@
|
||||
let hasSideEffects = 1 in
|
||||
def Serialize : Alias<2, (outs), (ins), [(z_serialize)]>;
|
||||
|
||||
+// A pseudo instruction that serves as a compiler barrier.
|
||||
+let hasSideEffects = 1 in
|
||||
+def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>;
|
||||
+
|
||||
let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in {
|
||||
def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_32, GR32>;
|
||||
def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_64, GR64>;
|
||||
Index: llvm/trunk/lib/Target/SystemZ/SystemZOperators.td
|
||||
===================================================================
|
||||
--- llvm/trunk/lib/Target/SystemZ/SystemZOperators.td
|
||||
+++ llvm/trunk/lib/Target/SystemZ/SystemZOperators.td
|
||||
@@ -188,6 +188,8 @@
|
||||
|
||||
def z_serialize : SDNode<"SystemZISD::SERIALIZE", SDTNone,
|
||||
[SDNPHasChain, SDNPMayStore]>;
|
||||
+def z_membarrier : SDNode<"SystemZISD::MEMBARRIER", SDTNone,
|
||||
+ [SDNPHasChain, SDNPSideEffect]>;
|
||||
|
||||
// Defined because the index is an i32 rather than a pointer.
|
||||
def z_vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
|
||||
Index: llvm/trunk/test/CodeGen/SystemZ/atomic-fence-01.ll
|
||||
===================================================================
|
||||
--- llvm/trunk/test/CodeGen/SystemZ/atomic-fence-01.ll
|
||||
+++ llvm/trunk/test/CodeGen/SystemZ/atomic-fence-01.ll
|
||||
@@ -0,0 +1,16 @@
|
||||
+; Test (fast) serialization.
|
||||
+;
|
||||
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s --check-prefix=Z10
|
||||
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s --check-prefix=Z196
|
||||
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s --check-prefix=ZEC12
|
||||
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s --check-prefix=Z13
|
||||
+
|
||||
+define void @test() {
|
||||
+; Z10: bcr 15, %r0
|
||||
+; Z196: bcr 14, %r0
|
||||
+; ZEC12: bcr 14, %r0
|
||||
+; Z13: bcr 14, %r0
|
||||
+ fence seq_cst
|
||||
+ ret void
|
||||
+}
|
||||
+
|
||||
Index: llvm/trunk/test/CodeGen/SystemZ/atomic-fence-02.ll
|
||||
===================================================================
|
||||
--- llvm/trunk/test/CodeGen/SystemZ/atomic-fence-02.ll
|
||||
+++ llvm/trunk/test/CodeGen/SystemZ/atomic-fence-02.ll
|
||||
@@ -0,0 +1,13 @@
|
||||
+; Serialization is emitted only for fence seq_cst.
|
||||
+;
|
||||
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
|
||||
+
|
||||
+define void @test() {
|
||||
+; CHECK: #MEMBARRIER
|
||||
+ fence acquire
|
||||
+; CHECK: #MEMBARRIER
|
||||
+ fence release
|
||||
+; CHECK: #MEMBARRIER
|
||||
+ fence acq_rel
|
||||
+ ret void
|
||||
+}
|
||||
70
llvm.spec
70
llvm.spec
|
|
@ -7,7 +7,7 @@
|
|||
|
||||
Name: llvm
|
||||
Version: 3.9.1
|
||||
Release: 3%{?dist}
|
||||
Release: 5%{?dist}
|
||||
Summary: The Low Level Virtual Machine
|
||||
|
||||
License: NCSA
|
||||
|
|
@ -16,9 +16,6 @@ Source0: http://llvm.org/releases/%{version}/%{name}-%{version}.src.tar.xz
|
|||
|
||||
Source100: llvm-config.h
|
||||
|
||||
# recognize s390 as SystemZ when configuring build
|
||||
Patch0: llvm-3.7.1-cmake-s390.patch
|
||||
|
||||
Patch1: 0001-This-code-block-breaks-the-docs-build-http-lab.llvm..patch
|
||||
Patch2: 0001-fix-docs-2.patch
|
||||
Patch3: 0001-fix-docs-3.patch
|
||||
|
|
@ -30,6 +27,10 @@ Patch5: 0001-cmake-Install-CheckAtomic.cmake-needed-by-lldb.patch
|
|||
Patch6: llvm-r294646.patch
|
||||
# This fix caused regressions
|
||||
Patch7: 0001-Revert-Merging-r280589.patch
|
||||
# https://reviews.llvm.org/D27609
|
||||
Patch8: 0001-Fix-R_AARCH64_MOVW_UABS_G3-relocation.patch
|
||||
# rhbz1435545
|
||||
Patch9: 0001-X86-Change-getHostCPUName-to-report-Intel-model-0x4e.patch
|
||||
|
||||
# backports cribbed from https://github.com/rust-lang/llvm/
|
||||
Patch47: rust-lang-llvm-pr47.patch
|
||||
|
|
@ -37,6 +38,7 @@ Patch53: rust-lang-llvm-pr53.patch
|
|||
Patch54: rust-lang-llvm-pr54.patch
|
||||
Patch55: rust-lang-llvm-pr55.patch
|
||||
Patch57: rust-lang-llvm-pr57.patch
|
||||
Patch67: rust-lang-llvm-pr67.patch
|
||||
|
||||
BuildRequires: cmake
|
||||
BuildRequires: zlib-devel
|
||||
|
|
@ -59,8 +61,8 @@ tools as well as libraries with equivalent functionality.
|
|||
%package devel
|
||||
Summary: Libraries and header files for LLVM
|
||||
Requires: %{name}%{?_isa} = %{version}-%{release}
|
||||
Requires(posttrans): %{_sbindir}/alternatives
|
||||
Requires(posttrans): %{_sbindir}/alternatives
|
||||
Requires(post): %{_sbindir}/alternatives
|
||||
Requires(postun): %{_sbindir}/alternatives
|
||||
|
||||
%description devel
|
||||
This package contains library and header files needed to develop new native
|
||||
|
|
@ -88,7 +90,6 @@ Static libraries for the LLVM compiler infrastructure.
|
|||
|
||||
%prep
|
||||
%setup -q -n %{name}-%{version}.src
|
||||
%patch0 -p1 -b .s390
|
||||
%patch1 -p1 -b .sphinx
|
||||
%patch2 -p1 -b .docs2
|
||||
%patch3 -p1 -b .docs3
|
||||
|
|
@ -96,11 +97,20 @@ Static libraries for the LLVM compiler infrastructure.
|
|||
%patch5 -p1 -b .lldbfix
|
||||
%patch6 -p0 -b .doc-lit
|
||||
%patch7 -p1 -b .amdfix
|
||||
%patch8 -p2 -b .arm64
|
||||
%patch47 -p1 -b .rust47
|
||||
%patch53 -p1 -b .rust53
|
||||
%patch54 -p1 -b .rust54
|
||||
%patch55 -p1 -b .rust55
|
||||
%patch57 -p1 -b .rust57
|
||||
%patch67 -p1 -b .rust67
|
||||
|
||||
%ifarch armv7hl
|
||||
|
||||
# These tests are marked as XFAIL, but they still run and hang on ARM.
|
||||
for f in `grep -Rl 'XFAIL.\+arm' test/ExecutionEngine `; do rm $f; done
|
||||
|
||||
%endif
|
||||
|
||||
%build
|
||||
mkdir -p _build
|
||||
|
|
@ -185,7 +195,9 @@ make check-all || :
|
|||
%{_sbindir}/update-alternatives --install %{_bindir}/llvm-config llvm-config %{_bindir}/llvm-config-%{__isa_bits} %{__isa_bits}
|
||||
|
||||
%postun devel
|
||||
[ $1 -eq 0 ] && %{_sbindir}/update-alternatives --remove llvm-config %{_bindir}/llvm-config-%{__isa_bits}
|
||||
if [ $1 -eq 0 ]; then
|
||||
%{_sbindir}/update-alternatives --remove llvm-config %{_bindir}/llvm-config-%{__isa_bits}
|
||||
fi
|
||||
|
||||
%files
|
||||
%{_bindir}/*
|
||||
|
|
@ -217,40 +229,24 @@ make check-all || :
|
|||
%{_libdir}/*.a
|
||||
|
||||
%changelog
|
||||
* Wed Mar 01 2017 Dave Airlie <airlied@redhat.com> - 3.9.1-3
|
||||
- revert upstream radeonsi breaking change.
|
||||
* Fri Aug 25 2017 Tom Stellard <tstellar@redhat.com> - 3.9.1-5
|
||||
- Backport r291084 (rhbz1435545)
|
||||
|
||||
* Thu Feb 23 2017 Josh Stone <jistone@redhat.com> - 3.9.1-2
|
||||
- disable sphinx warnings-as-errors
|
||||
* Thu Aug 24 2017 tstellar@redhat.com - 3.9.1-4
|
||||
- Fix %postun step for -devel package (rhbz 1403539).
|
||||
|
||||
* Fri Feb 10 2017 Orion Poplawski <orion@cora.nwra.com> - 3.9.1-1
|
||||
- llvm 3.9.1
|
||||
* Tue Apr 18 2017 Josh Stone <jistone@redhat.com> - 3.9.1-3
|
||||
- Fix computeKnownBits for ARMISD::CMOV (rust-lang/llvm#67)
|
||||
|
||||
* Fri Feb 10 2017 Fedora Release Engineering <releng@fedoraproject.org> - 3.9.0-8
|
||||
- Rebuilt for https://fedoraproject.org/wiki/Fedora_26_Mass_Rebuild
|
||||
* Fri Mar 17 2017 Peter Robinson <pbrobinson@fedoraproject.org> 3.9.1-2
|
||||
- Fix missing mask on relocation for aarch64 (rhbz 1429050)
|
||||
- Disable failing tests on ARM.
|
||||
|
||||
* Tue Nov 29 2016 Josh Stone <jistone@redhat.com> - 3.9.0-7
|
||||
- Apply backports from rust-lang/llvm#55, #57
|
||||
* Wed Mar 01 2017 Dave Airlie <airlied@redhat.com> - 3.9.1-1
|
||||
- llvm 3.9.1 (master merge)
|
||||
|
||||
* Tue Nov 01 2016 Dave Airlie <airlied@gmail.com - 3.9.0-6
|
||||
- rebuild for new arches
|
||||
|
||||
* Wed Oct 26 2016 Dave Airlie <airlied@redhat.com> - 3.9.0-5
|
||||
- apply the patch from -4
|
||||
|
||||
* Wed Oct 26 2016 Dave Airlie <airlied@redhat.com> - 3.9.0-4
|
||||
- add fix for lldb out-of-tree build
|
||||
|
||||
* Mon Oct 17 2016 Josh Stone <jistone@redhat.com> - 3.9.0-3
|
||||
- Apply backports from rust-lang/llvm#47, #48, #53, #54
|
||||
|
||||
* Sat Oct 15 2016 Josh Stone <jistone@redhat.com> - 3.9.0-2
|
||||
- Apply an InstCombine backport via rust-lang/llvm#51
|
||||
|
||||
* Wed Sep 07 2016 Dave Airlie <airlied@redhat.com> - 3.9.0-1
|
||||
- llvm 3.9.0
|
||||
- upstream moved where cmake files are packaged.
|
||||
- upstream dropped CppBackend
|
||||
* Sat Jan 07 2017 Josh Stone <jistone@redhat.com> - 3.8.1-2
|
||||
- Support s390x atomic fence
|
||||
|
||||
* Wed Jul 13 2016 Adam Jackson <ajax@redhat.com> - 3.8.1-1
|
||||
- llvm 3.8.1
|
||||
|
|
|
|||
|
|
@ -0,0 +1,70 @@
|
|||
From a6fa10c14649c18d299cddf3e823b032460cb6f5 Mon Sep 17 00:00:00 2001
|
||||
From: Pirama Arumuga Nainar <pirama@google.com>
|
||||
Date: Thu, 23 Mar 2017 16:47:47 +0000
|
||||
Subject: [PATCH] Fix computeKnownBits for ARMISD::CMOV
|
||||
|
||||
Summary:
|
||||
The true and false operands for the CMOV are operands 0 and 1.
|
||||
ARMISelLowering.cpp::computeKnownBits was looking at operands 1 and 2
|
||||
instead. This can cause CMOV instructions to be incorrectly folded into
|
||||
BFI if value set by the CMOV is another CMOV, whose known bits are
|
||||
computed incorrectly.
|
||||
|
||||
This patch fixes the issue and adds a test case.
|
||||
|
||||
Reviewers: kristof.beyls, jmolloy
|
||||
|
||||
Subscribers: llvm-commits, aemerson, srhines, rengolin
|
||||
|
||||
Differential Revision: https://reviews.llvm.org/D31265
|
||||
|
||||
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298624 91177308-0d34-0410-b5e6-96231b3b80d8
|
||||
---
|
||||
lib/Target/ARM/ARMISelLowering.cpp | 4 ++--
|
||||
test/CodeGen/ARM/no-cmov2bfi.ll | 19 +++++++++++++++++++
|
||||
2 files changed, 21 insertions(+), 2 deletions(-)
|
||||
create mode 100644 test/CodeGen/ARM/no-cmov2bfi.ll
|
||||
|
||||
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
|
||||
index 4a227a3cd7b1..cf98e60c0657 100644
|
||||
--- a/lib/Target/ARM/ARMISelLowering.cpp
|
||||
+++ b/lib/Target/ARM/ARMISelLowering.cpp
|
||||
@@ -10806,8 +10806,8 @@ static void computeKnownBits(SelectionDAG &DAG, SDValue Op, APInt &KnownZero,
|
||||
if (Op.getOpcode() == ARMISD::CMOV) {
|
||||
APInt KZ2(KnownZero.getBitWidth(), 0);
|
||||
APInt KO2(KnownOne.getBitWidth(), 0);
|
||||
- computeKnownBits(DAG, Op.getOperand(1), KnownZero, KnownOne);
|
||||
- computeKnownBits(DAG, Op.getOperand(2), KZ2, KO2);
|
||||
+ computeKnownBits(DAG, Op.getOperand(0), KnownZero, KnownOne);
|
||||
+ computeKnownBits(DAG, Op.getOperand(1), KZ2, KO2);
|
||||
|
||||
KnownZero &= KZ2;
|
||||
KnownOne &= KO2;
|
||||
diff --git a/test/CodeGen/ARM/no-cmov2bfi.ll b/test/CodeGen/ARM/no-cmov2bfi.ll
|
||||
new file mode 100644
|
||||
index 000000000000..c8b512048905
|
||||
--- /dev/null
|
||||
+++ b/test/CodeGen/ARM/no-cmov2bfi.ll
|
||||
@@ -0,0 +1,19 @@
|
||||
+; RUN: llc < %s -mtriple=thumbv7 | FileCheck --check-prefix=CHECK-NOBFI %s
|
||||
+
|
||||
+declare zeroext i1 @dummy()
|
||||
+
|
||||
+define i8 @test(i8 %a1, i1 %c) {
|
||||
+; CHECK-NOBFI-NOT: bfi
|
||||
+; CHECK-NOBFI: bl dummy
|
||||
+; CHECK-NOBFI: cmp r0, #0
|
||||
+; CHECK-NOBFI: it ne
|
||||
+; CHECK-NOBFI: orrne [[REG:r[0-9]+]], [[REG]], #8
|
||||
+; CHECK-NOBFI: mov r0, [[REG]]
|
||||
+
|
||||
+ %1 = and i8 %a1, -9
|
||||
+ %2 = select i1 %c, i8 %1, i8 %a1
|
||||
+ %3 = tail call zeroext i1 @dummy()
|
||||
+ %4 = or i8 %2, 8
|
||||
+ %ret = select i1 %3, i8 %4, i8 %2
|
||||
+ ret i8 %ret
|
||||
+}
|
||||
--
|
||||
2.9.3
|
||||
|
||||
Loading…
Reference in New Issue