Fix computeKnownBits for ARMISD::CMOV (rust-lang/llvm#67)

llvm-d18644-systemz-atomic-fence.patch

@@ -0,0 +1,169 @@
+Index: llvm/trunk/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+===================================================================
+--- llvm/trunk/lib/Target/SystemZ/SystemZAsmPrinter.cpp
++++ llvm/trunk/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+@@ -260,6 +260,11 @@
+         .addImm(15).addReg(SystemZ::R0D);
+     break;
+ 
++  // Emit nothing here but a comment if we can.
++  case SystemZ::MemBarrier:
++    OutStreamer->emitRawComment("MEMBARRIER");
++    return;
++
+   default:
+     Lower.lower(MI, LoweredMI);
+     break;
+Index: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h
+===================================================================
+--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h
++++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h
+@@ -146,6 +146,9 @@
+   // Perform a serialization operation.  (BCR 15,0 or BCR 14,0.)
+   SERIALIZE,
+ 
++  // Compiler barrier only; generate a no-op.
++  MEMBARRIER,
++
+   // Transaction begin.  The first operand is the chain, the second
+   // the TDB pointer, and the third the immediate control field.
+   // Returns chain and glue.
+@@ -479,6 +482,7 @@
+   SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
+   SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
+   SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
++  SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
+   SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
+   SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
+   SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
+Index: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
+===================================================================
+--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
++++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
+@@ -216,6 +216,8 @@
+   setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);
+   setOperationAction(ISD::ATOMIC_CMP_SWAP,  MVT::i32, Custom);
+ 
++  setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
++
+   // z10 has instructions for signed but not unsigned FP conversion.
+   // Handle unsigned 32-bit types as signed 64-bit types.
+   if (!Subtarget.hasFPExtension()) {
+@@ -3118,6 +3120,25 @@
+   return Op;
+ }
+ 
++SDValue SystemZTargetLowering::lowerATOMIC_FENCE(SDValue Op,
++                                                 SelectionDAG &DAG) const {
++  SDLoc DL(Op);
++  AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
++    cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
++  SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
++    cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
++
++  // The only fence that needs an instruction is a sequentially-consistent
++  // cross-thread fence.
++  if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
++    return SDValue(DAG.getMachineNode(SystemZ::Serialize, DL, MVT::Other,
++                                      Op.getOperand(0)), 0);
++  }
++
++  // MEMBARRIER is a compiler barrier; it codegens to a no-op.
++  return DAG.getNode(SystemZISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
++}
++
+ // Op is an atomic load.  Lower it into a normal volatile load.
+ SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
+                                                 SelectionDAG &DAG) const {
+@@ -4444,6 +4465,8 @@
+   case ISD::CTTZ_ZERO_UNDEF:
+     return DAG.getNode(ISD::CTTZ, SDLoc(Op),
+                        Op.getValueType(), Op.getOperand(0));
++  case ISD::ATOMIC_FENCE:
++    return lowerATOMIC_FENCE(Op, DAG);
+   case ISD::ATOMIC_SWAP:
+     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_SWAPW);
+   case ISD::ATOMIC_STORE:
+@@ -4547,6 +4570,7 @@
+     OPCODE(SEARCH_STRING);
+     OPCODE(IPM);
+     OPCODE(SERIALIZE);
++    OPCODE(MEMBARRIER);
+     OPCODE(TBEGIN);
+     OPCODE(TBEGIN_NOFLOAT);
+     OPCODE(TEND);
+@@ -5307,6 +5331,7 @@
+ MachineBasicBlock *
+ SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
+                                           MachineBasicBlock *MBB) const {
++
+   MachineFunction &MF = *MBB->getParent();
+   const SystemZInstrInfo *TII =
+       static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
+Index: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
+===================================================================
+--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
++++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
+@@ -1231,6 +1231,10 @@
+ let hasSideEffects = 1 in
+ def Serialize : Alias<2, (outs), (ins), [(z_serialize)]>;
+ 
++// A pseudo instruction that serves as a compiler barrier.
++let hasSideEffects = 1 in
++def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>;
++
+ let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in {
+   def LAA   : LoadAndOpRSY<"laa",   0xEBF8, atomic_load_add_32, GR32>;
+   def LAAG  : LoadAndOpRSY<"laag",  0xEBE8, atomic_load_add_64, GR64>;
+Index: llvm/trunk/lib/Target/SystemZ/SystemZOperators.td
+===================================================================
+--- llvm/trunk/lib/Target/SystemZ/SystemZOperators.td
++++ llvm/trunk/lib/Target/SystemZ/SystemZOperators.td
+@@ -188,6 +188,8 @@
+ 
+ def z_serialize         : SDNode<"SystemZISD::SERIALIZE", SDTNone,
+                                  [SDNPHasChain, SDNPMayStore]>;
++def z_membarrier        : SDNode<"SystemZISD::MEMBARRIER", SDTNone,
++                                 [SDNPHasChain, SDNPSideEffect]>;
+ 
+ // Defined because the index is an i32 rather than a pointer.
+ def z_vector_insert     : SDNode<"ISD::INSERT_VECTOR_ELT",
+Index: llvm/trunk/test/CodeGen/SystemZ/atomic-fence-01.ll
+===================================================================
+--- llvm/trunk/test/CodeGen/SystemZ/atomic-fence-01.ll
++++ llvm/trunk/test/CodeGen/SystemZ/atomic-fence-01.ll
+@@ -0,0 +1,16 @@
++; Test (fast) serialization.
++;
++; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s --check-prefix=Z10
++; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196  | FileCheck %s --check-prefix=Z196
++; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s --check-prefix=ZEC12
++; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13   | FileCheck %s --check-prefix=Z13
++
++define void @test() {
++; Z10:   bcr 15, %r0
++; Z196:  bcr 14, %r0
++; ZEC12: bcr 14, %r0
++; Z13:   bcr 14, %r0
++  fence seq_cst
++  ret void
++}
++
+Index: llvm/trunk/test/CodeGen/SystemZ/atomic-fence-02.ll
+===================================================================
+--- llvm/trunk/test/CodeGen/SystemZ/atomic-fence-02.ll
++++ llvm/trunk/test/CodeGen/SystemZ/atomic-fence-02.ll
+@@ -0,0 +1,13 @@
++; Serialization is emitted only for fence seq_cst.
++;
++; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
++
++define void @test() {
++; CHECK: #MEMBARRIER
++  fence acquire
++; CHECK: #MEMBARRIER
++  fence release
++; CHECK: #MEMBARRIER
++  fence acq_rel
++  ret void
++}

llvm.spec

@@ -7,7 +7,7 @@
 
 Name:		llvm
 Version:	3.8.1
-Release:	1%{?dist}
+Release:	3%{?dist}
 Summary:	The Low Level Virtual Machine
 
 License:	NCSA
@@ -19,6 +19,12 @@ Source100:	llvm-config.h
 # recognize s390 as SystemZ when configuring build
 Patch0:		llvm-3.7.1-cmake-s390.patch
 
+# backport D18644 [SystemZ] Support ATOMIC_FENCE
+Patch1:		llvm-d18644-systemz-atomic-fence.patch
+
+# backports cribbed from https://github.com/rust-lang/llvm/
+Patch67:	rust-lang-llvm-pr67.patch
+
 BuildRequires:	cmake
 BuildRequires:	zlib-devel
 BuildRequires:  libffi-devel
@@ -70,6 +76,8 @@ Static libraries for the LLVM compiler infrastructure.
 %prep
 %setup -q -n %{name}-%{version}.src
 %patch0 -p1 -b .s390
+%patch1 -p2 -b .s390-fence
+%patch67 -p1 -b .rust67
 
 %build
 mkdir -p _build
@@ -129,6 +137,7 @@ cd _build
 	-DLLVM_BUILD_EXTERNAL_COMPILER_RT:BOOL=ON \
 	-DLLVM_INSTALL_TOOLCHAIN_ONLY:BOOL=OFF \
 	\
+	-DSPHINX_WARNINGS_AS_ERRORS=OFF \
 	-DSPHINX_EXECUTABLE=%{_bindir}/sphinx-build-3
 
 make %{?_smp_mflags}
@@ -185,6 +194,12 @@ make check-all || :
 %{_libdir}/*.a
 
 %changelog
+* Tue Apr 18 2017 Josh Stone <jistone@redhat.com> - 3.8.1-3
+- Fix computeKnownBits for ARMISD::CMOV (rust-lang/llvm#67)
+
+* Sat Jan 07 2017 Josh Stone <jistone@redhat.com> - 3.8.1-2
+- Support s390x atomic fence
+
 * Wed Jul 13 2016 Adam Jackson <ajax@redhat.com> - 3.8.1-1
 - llvm 3.8.1
 - Add mips target

rust-lang-llvm-pr67.patch

@@ -0,0 +1,70 @@
+From a6fa10c14649c18d299cddf3e823b032460cb6f5 Mon Sep 17 00:00:00 2001
+From: Pirama Arumuga Nainar <pirama@google.com>
+Date: Thu, 23 Mar 2017 16:47:47 +0000
+Subject: [PATCH] Fix computeKnownBits for ARMISD::CMOV
+
+Summary:
+The true and false operands for the CMOV are operands 0 and 1.
+ARMISelLowering.cpp::computeKnownBits was looking at operands 1 and 2
+instead.  This can cause CMOV instructions to be incorrectly folded into
+BFI if value set by the CMOV is another CMOV, whose known bits are
+computed incorrectly.
+
+This patch fixes the issue and adds a test case.
+
+Reviewers: kristof.beyls, jmolloy
+
+Subscribers: llvm-commits, aemerson, srhines, rengolin
+
+Differential Revision: https://reviews.llvm.org/D31265
+
+git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298624 91177308-0d34-0410-b5e6-96231b3b80d8
+---
+ lib/Target/ARM/ARMISelLowering.cpp |  4 ++--
+ test/CodeGen/ARM/no-cmov2bfi.ll    | 19 +++++++++++++++++++
+ 2 files changed, 21 insertions(+), 2 deletions(-)
+ create mode 100644 test/CodeGen/ARM/no-cmov2bfi.ll
+
+diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
+index 4a227a3cd7b1..cf98e60c0657 100644
+--- a/lib/Target/ARM/ARMISelLowering.cpp
++++ b/lib/Target/ARM/ARMISelLowering.cpp
+@@ -10806,8 +10806,8 @@ static void computeKnownBits(SelectionDAG &DAG, SDValue Op, APInt &KnownZero,
+   if (Op.getOpcode() == ARMISD::CMOV) {
+     APInt KZ2(KnownZero.getBitWidth(), 0);
+     APInt KO2(KnownOne.getBitWidth(), 0);
+-    computeKnownBits(DAG, Op.getOperand(1), KnownZero, KnownOne);
+-    computeKnownBits(DAG, Op.getOperand(2), KZ2, KO2);
++    computeKnownBits(DAG, Op.getOperand(0), KnownZero, KnownOne);
++    computeKnownBits(DAG, Op.getOperand(1), KZ2, KO2);
+ 
+     KnownZero &= KZ2;
+     KnownOne &= KO2;
+diff --git a/test/CodeGen/ARM/no-cmov2bfi.ll b/test/CodeGen/ARM/no-cmov2bfi.ll
+new file mode 100644
+index 000000000000..c8b512048905
+--- /dev/null
++++ b/test/CodeGen/ARM/no-cmov2bfi.ll
+@@ -0,0 +1,19 @@
++; RUN: llc < %s -mtriple=thumbv7 | FileCheck --check-prefix=CHECK-NOBFI %s
++
++declare zeroext i1 @dummy()
++
++define i8 @test(i8 %a1, i1 %c) {
++; CHECK-NOBFI-NOT: bfi
++; CHECK-NOBFI: bl      dummy
++; CHECK-NOBFI: cmp     r0, #0
++; CHECK-NOBFI: it      ne
++; CHECK-NOBFI: orrne   [[REG:r[0-9]+]], [[REG]], #8
++; CHECK-NOBFI: mov     r0, [[REG]]
++
++  %1 = and i8 %a1, -9
++  %2 = select i1 %c, i8 %1, i8 %a1
++  %3 = tail call zeroext i1 @dummy()
++  %4 = or i8 %2, 8
++  %ret = select i1 %3, i8 %4, i8 %2
++  ret i8 %ret
++}
+-- 
+2.9.3
+