From c6efc8ed9ca389a8d268268ad8fa96f361530079 Mon Sep 17 00:00:00 2001
From: David Abdurachmanov <david.abdurachmanov@gmail.com>
Date: Sun, 12 Aug 2018 09:09:51 +0300
Subject: [PATCH] Move RISCV to experimental targets

Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
---
 llvm.spec | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/llvm.spec b/llvm.spec
index 644f3d5..a5e379a 100644
--- a/llvm.spec
+++ b/llvm.spec
@@ -29,7 +29,7 @@
 %global llvm_targets ARM;BPF
 %endif
 %ifarch riscv64
-%global llvm_targets RISCV;AMDGPU;BPF
+%global llvm_targets AMDGPU;BPF
 %endif
 
 %if 0%{?compat_build}
@@ -164,6 +164,9 @@ export LDFLAGS="${LDFLAGS} -latomic %{__global_ldflags}"
 %endif
 	\
 	-DLLVM_TARGETS_TO_BUILD="%{llvm_targets}" \
+%ifarch riscv64
+    -DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD="RISCV" \
+%endif
 	-DLLVM_ENABLE_LIBCXX:BOOL=OFF \
 	-DLLVM_ENABLE_ZLIB:BOOL=ON \
 	-DLLVM_ENABLE_FFI:BOOL=ON \