Backport r296811, r297001, and r327651 from trunk. rhbz#1554349
This commit is contained in:
Tom Stellard
parent
48a8b21ef0
commit
b3f19ed18b
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@ -0,0 +1,77 @@
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From 66e43b0a8e5616a4762eedee9bd030a49b9d6545 Mon Sep 17 00:00:00 2001
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From: Guozhi Wei <carrot@google.com>
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Date: Thu, 2 Mar 2017 21:07:59 +0000
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Subject: [PATCH 1/3] [PPC] Fix code generation for bswap(int32) followed by
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store16
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This patch fixes pr32063.
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Current code in PPCTargetLowering::PerformDAGCombine can transform
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bswap
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store
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into a single PPCISD::STBRX instruction. but it doesn't consider the case that the operand size of bswap may be larger than store size. When it occurs, we need 2 modifications,
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1 For the last operand of PPCISD::STBRX, we should not use DAG.getValueType(N->getOperand(1).getValueType()), instead we should use cast<StoreSDNode>(N)->getMemoryVT().
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2 Before PPCISD::STBRX, we need to shift the original operand of bswap to the right side.
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Differential Revision: https://reviews.llvm.org/D30362
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296811 91177308-0d34-0410-b5e6-96231b3b80d8
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---
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lib/Target/PowerPC/PPCISelLowering.cpp | 12 ++++++++++--
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test/CodeGen/PowerPC/pr32063.ll | 16 ++++++++++++++++
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2 files changed, 26 insertions(+), 2 deletions(-)
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create mode 100644 test/CodeGen/PowerPC/pr32063.ll
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diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
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index 6313082..c8eb6f1 100644
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--- a/lib/Target/PowerPC/PPCISelLowering.cpp
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+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
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@@ -11226,9 +11226,17 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
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if (BSwapOp.getValueType() == MVT::i16)
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BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
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+ // If the type of BSWAP operand is wider than stored memory width
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+ // it need to be shifted to the right side before STBRX.
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+ EVT mVT = cast<StoreSDNode>(N)->getMemoryVT();
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+ if (Op1VT.bitsGT(mVT)) {
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+ int shift = Op1VT.getSizeInBits() - mVT.getSizeInBits();
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+ BSwapOp = DAG.getNode(ISD::SRL, dl, Op1VT, BSwapOp,
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+ DAG.getConstant(shift, dl, MVT::i32));
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+ }
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+
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SDValue Ops[] = {
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- N->getOperand(0), BSwapOp, N->getOperand(2),
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- DAG.getValueType(N->getOperand(1).getValueType())
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+ N->getOperand(0), BSwapOp, N->getOperand(2), DAG.getValueType(mVT)
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};
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return
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DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
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diff --git a/test/CodeGen/PowerPC/pr32063.ll b/test/CodeGen/PowerPC/pr32063.ll
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new file mode 100644
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index 0000000..f031ec8
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--- /dev/null
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+++ b/test/CodeGen/PowerPC/pr32063.ll
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@@ -0,0 +1,16 @@
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+; RUN: llc -O2 < %s | FileCheck %s
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+target triple = "powerpc64le-linux-gnu"
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+
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+define void @foo(i32 %v, i16* %p) {
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+ %1 = and i32 %v, -65536
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+ %2 = tail call i32 @llvm.bswap.i32(i32 %1)
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+ %conv = trunc i32 %2 to i16
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+ store i16 %conv, i16* %p
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+ ret void
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+
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+; CHECK: srwi
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+; CHECK: sthbrx
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+; CHECK-NOT: stwbrx
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+}
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+
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+declare i32 @llvm.bswap.i32(i32)
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--
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1.8.3.1
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@ -0,0 +1,107 @@
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From 88e57f376eabc375cd9f374369cf9e8e4dcb90af Mon Sep 17 00:00:00 2001
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From: Nemanja Ivanovic <nemanja.i.ibm@gmail.com>
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Date: Mon, 6 Mar 2017 07:32:13 +0000
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Subject: [PATCH 2/3] [PowerPC] Fix failure with STBRX when store is narrower
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than the bswap
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Fixes a crash caused by r296811 by truncating the input of the STBRX node
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when the bswap is wider than i32.
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Fixes https://bugs.llvm.org/show_bug.cgi?id=32140
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Differential Revision: https://reviews.llvm.org/D30615
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297001 91177308-0d34-0410-b5e6-96231b3b80d8
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---
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lib/Target/PowerPC/PPCISelLowering.cpp | 7 ++--
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test/CodeGen/PowerPC/pr32140.ll | 59 ++++++++++++++++++++++++++++++++++
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2 files changed, 64 insertions(+), 2 deletions(-)
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create mode 100644 test/CodeGen/PowerPC/pr32140.ll
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diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
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index c8eb6f1..521bb32 100644
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--- a/lib/Target/PowerPC/PPCISelLowering.cpp
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+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
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@@ -11230,9 +11230,12 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
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// it need to be shifted to the right side before STBRX.
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EVT mVT = cast<StoreSDNode>(N)->getMemoryVT();
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if (Op1VT.bitsGT(mVT)) {
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- int shift = Op1VT.getSizeInBits() - mVT.getSizeInBits();
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+ int Shift = Op1VT.getSizeInBits() - mVT.getSizeInBits();
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BSwapOp = DAG.getNode(ISD::SRL, dl, Op1VT, BSwapOp,
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- DAG.getConstant(shift, dl, MVT::i32));
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+ DAG.getConstant(Shift, dl, MVT::i32));
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+ // Need to truncate if this is a bswap of i64 stored as i32/i16.
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+ if (Op1VT == MVT::i64)
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+ BSwapOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BSwapOp);
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}
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SDValue Ops[] = {
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diff --git a/test/CodeGen/PowerPC/pr32140.ll b/test/CodeGen/PowerPC/pr32140.ll
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new file mode 100644
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index 0000000..827a904
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--- /dev/null
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+++ b/test/CodeGen/PowerPC/pr32140.ll
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@@ -0,0 +1,59 @@
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+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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+; RUN: llc -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
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+; RUN: llc -mtriple=powerpc64-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
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+
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+@as = common local_unnamed_addr global i16 0, align 2
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+@bs = common local_unnamed_addr global i16 0, align 2
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+@ai = common local_unnamed_addr global i32 0, align 4
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+@bi = common local_unnamed_addr global i32 0, align 4
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+
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+define void @bswapStorei64Toi32() {
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+; CHECK-LABEL: bswapStorei64Toi32:
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+; CHECK: # BB#0: # %entry
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+; CHECK: lwa 3, 0(3)
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+; CHECK-NEXT: rldicl 3, 3, 32, 32
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+; CHECK-NEXT: stwbrx 3, 0, 4
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+; CHECK-NEXT: blr
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+entry:
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+ %0 = load i32, i32* @ai, align 4
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+ %conv.i = sext i32 %0 to i64
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+ %or26.i = tail call i64 @llvm.bswap.i64(i64 %conv.i)
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+ %conv = trunc i64 %or26.i to i32
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+ store i32 %conv, i32* @bi, align 4
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+ ret void
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+}
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+
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+define void @bswapStorei32Toi16() {
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+; CHECK-LABEL: bswapStorei32Toi16:
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+; CHECK: # BB#0: # %entry
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+; CHECK: lha 3, 0(3)
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+; CHECK-NEXT: srwi 3, 3, 16
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+; CHECK-NEXT: sthbrx 3, 0, 4
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+; CHECK-NEXT: blr
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+entry:
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+ %0 = load i16, i16* @as, align 2
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+ %conv.i = sext i16 %0 to i32
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+ %or26.i = tail call i32 @llvm.bswap.i32(i32 %conv.i)
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+ %conv = trunc i32 %or26.i to i16
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+ store i16 %conv, i16* @bs, align 2
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+ ret void
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+}
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+
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+define void @bswapStorei64Toi16() {
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+; CHECK-LABEL: bswapStorei64Toi16:
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+; CHECK: # BB#0: # %entry
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+; CHECK: lha 3, 0(3)
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+; CHECK-NEXT: rldicl 3, 3, 16, 48
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+; CHECK-NEXT: sthbrx 3, 0, 4
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+; CHECK-NEXT: blr
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+entry:
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+ %0 = load i16, i16* @as, align 2
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+ %conv.i = sext i16 %0 to i64
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+ %or26.i = tail call i64 @llvm.bswap.i64(i64 %conv.i)
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+ %conv = trunc i64 %or26.i to i16
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+ store i16 %conv, i16* @bs, align 2
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+ ret void
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+}
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+
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+declare i32 @llvm.bswap.i32(i32)
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+declare i64 @llvm.bswap.i64(i64)
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--
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1.8.3.1
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@ -0,0 +1,69 @@
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From 8578ad1fb9aa7ebc7e6da266371b8fd58e67633f Mon Sep 17 00:00:00 2001
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From: Guozhi Wei <carrot@google.com>
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Date: Thu, 15 Mar 2018 17:49:12 +0000
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Subject: [PATCH 3/3] [PPC] Avoid non-simple MVT in STBRX optimization
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PR35402 triggered this case. It bswap and stores a 48bit value, current STBRX optimization transforms it into STBRX. Unfortunately 48bit is not a simple MVT, there is no PPC instruction to support it, and it can't be automatically expanded by llvm, so caused a crash.
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This patch detects the non-simple MVT and returns early.
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Differential Revision: https://reviews.llvm.org/D44500
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327651 91177308-0d34-0410-b5e6-96231b3b80d8
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---
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lib/Target/PowerPC/PPCISelLowering.cpp | 6 +++++-
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test/CodeGen/PowerPC/pr35402.ll | 18 ++++++++++++++++++
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2 files changed, 23 insertions(+), 1 deletion(-)
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create mode 100644 test/CodeGen/PowerPC/pr35402.ll
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diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
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index 521bb32..3c37306 100644
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--- a/lib/Target/PowerPC/PPCISelLowering.cpp
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+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
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@@ -11221,6 +11221,11 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
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N->getOperand(1).getValueType() == MVT::i16 ||
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(Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
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N->getOperand(1).getValueType() == MVT::i64))) {
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+ // STBRX can only handle simple types.
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+ EVT mVT = cast<StoreSDNode>(N)->getMemoryVT();
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+ if (mVT.isExtended())
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+ break;
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+
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SDValue BSwapOp = N->getOperand(1).getOperand(0);
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// Do an any-extend to 32-bits if this is a half-word input.
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if (BSwapOp.getValueType() == MVT::i16)
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@@ -11228,7 +11233,6 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
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// If the type of BSWAP operand is wider than stored memory width
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// it need to be shifted to the right side before STBRX.
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- EVT mVT = cast<StoreSDNode>(N)->getMemoryVT();
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if (Op1VT.bitsGT(mVT)) {
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int Shift = Op1VT.getSizeInBits() - mVT.getSizeInBits();
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BSwapOp = DAG.getNode(ISD::SRL, dl, Op1VT, BSwapOp,
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diff --git a/test/CodeGen/PowerPC/pr35402.ll b/test/CodeGen/PowerPC/pr35402.ll
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new file mode 100644
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index 0000000..06e6d96
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--- /dev/null
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+++ b/test/CodeGen/PowerPC/pr35402.ll
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@@ -0,0 +1,18 @@
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+; RUN: llc -O2 < %s | FileCheck %s
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+target triple = "powerpc64le-linux-gnu"
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+
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+define void @test(i8* %p, i64 %data) {
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+entry:
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+ %0 = tail call i64 @llvm.bswap.i64(i64 %data)
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+ %ptr = bitcast i8* %p to i48*
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+ %val = trunc i64 %0 to i48
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+ store i48 %val, i48* %ptr, align 1
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+ ret void
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+
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+; CHECK: sth
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+; CHECK: stw
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+; CHECK-NOT: stdbrx
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+
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+}
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+
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+declare i64 @llvm.bswap.i64(i64)
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--
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1.8.3.1
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@ -9,7 +9,7 @@
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Name: llvm
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Version: 4.0.1
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Release: 2%{?dist}
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Release: 3%{?dist}
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Summary: The Low Level Virtual Machine
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License: NCSA
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@ -24,6 +24,9 @@ Patch4: 0001-Revert-Revert-CMake-Move-sphinx-detection-into-AddSp.patch
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Patch5: 0001-CMake-Fix-docs-llvm-man-target-when-clang-llvm-is-in.patch
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Patch6: 0001-CMake-Add-LLVM_UTILS_INSTALL_DIR-option.patch
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Patch7: 0001-DebugInfo-Fix-potential-CU-mismatch-for-SubprogramSc.patch
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Patch8: 0001-PPC-Fix-code-generation-for-bswap-int32-followed-by-.patch
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Patch9: 0002-PowerPC-Fix-failure-with-STBRX-when-store-is-narrowe.patch
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Patch10: 0003-PPC-Avoid-non-simple-MVT-in-STBRX-optimization.patch
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BuildRequires: cmake
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BuildRequires: zlib-devel
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@ -205,6 +208,9 @@ fi
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%{_libdir}/cmake/llvm/LLVMStaticExports.cmake
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%changelog
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* Mon Mar 19 2018 Tom Stellard <tstellar@redhat.com> - 4.0.1-3
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- Backport r296811, r297001, and r327651 from trunk. rhbz#1554349
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* Tue Nov 21 2017 Tom Stellard <tstellar@redhat.com> - 4.0.1-2
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- Backport r318289 to fix a debuginfo issue with rust.
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