Support s390x atomic fence
This commit is contained in:
Josh Stone
parent
3c6edb0d6b
commit
74fef128e4
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@ -0,0 +1,169 @@
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Index: llvm/trunk/lib/Target/SystemZ/SystemZAsmPrinter.cpp
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===================================================================
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--- llvm/trunk/lib/Target/SystemZ/SystemZAsmPrinter.cpp
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+++ llvm/trunk/lib/Target/SystemZ/SystemZAsmPrinter.cpp
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@@ -260,6 +260,11 @@
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.addImm(15).addReg(SystemZ::R0D);
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break;
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+ // Emit nothing here but a comment if we can.
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+ case SystemZ::MemBarrier:
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+ OutStreamer->emitRawComment("MEMBARRIER");
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+ return;
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+
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default:
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Lower.lower(MI, LoweredMI);
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break;
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Index: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h
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===================================================================
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--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h
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+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h
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@@ -146,6 +146,9 @@
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// Perform a serialization operation. (BCR 15,0 or BCR 14,0.)
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SERIALIZE,
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+ // Compiler barrier only; generate a no-op.
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+ MEMBARRIER,
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+
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// Transaction begin. The first operand is the chain, the second
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// the TDB pointer, and the third the immediate control field.
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// Returns chain and glue.
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@@ -479,6 +482,7 @@
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SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
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+ SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
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Index: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
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===================================================================
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--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
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+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
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@@ -216,6 +216,8 @@
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setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);
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setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
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+ setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
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+
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// z10 has instructions for signed but not unsigned FP conversion.
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// Handle unsigned 32-bit types as signed 64-bit types.
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if (!Subtarget.hasFPExtension()) {
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@@ -3118,6 +3120,25 @@
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return Op;
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}
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+SDValue SystemZTargetLowering::lowerATOMIC_FENCE(SDValue Op,
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+ SelectionDAG &DAG) const {
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+ SDLoc DL(Op);
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+ AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
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+ cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
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+ SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
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+ cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
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+
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+ // The only fence that needs an instruction is a sequentially-consistent
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+ // cross-thread fence.
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+ if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
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+ return SDValue(DAG.getMachineNode(SystemZ::Serialize, DL, MVT::Other,
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+ Op.getOperand(0)), 0);
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+ }
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+
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+ // MEMBARRIER is a compiler barrier; it codegens to a no-op.
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+ return DAG.getNode(SystemZISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
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+}
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+
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// Op is an atomic load. Lower it into a normal volatile load.
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SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
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SelectionDAG &DAG) const {
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@@ -4444,6 +4465,8 @@
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case ISD::CTTZ_ZERO_UNDEF:
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return DAG.getNode(ISD::CTTZ, SDLoc(Op),
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Op.getValueType(), Op.getOperand(0));
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+ case ISD::ATOMIC_FENCE:
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+ return lowerATOMIC_FENCE(Op, DAG);
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case ISD::ATOMIC_SWAP:
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return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_SWAPW);
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case ISD::ATOMIC_STORE:
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@@ -4547,6 +4570,7 @@
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OPCODE(SEARCH_STRING);
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OPCODE(IPM);
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OPCODE(SERIALIZE);
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+ OPCODE(MEMBARRIER);
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OPCODE(TBEGIN);
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OPCODE(TBEGIN_NOFLOAT);
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OPCODE(TEND);
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@@ -5307,6 +5331,7 @@
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MachineBasicBlock *
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SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
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MachineBasicBlock *MBB) const {
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+
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MachineFunction &MF = *MBB->getParent();
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const SystemZInstrInfo *TII =
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static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
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Index: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
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===================================================================
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--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
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+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
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@@ -1231,6 +1231,10 @@
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let hasSideEffects = 1 in
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def Serialize : Alias<2, (outs), (ins), [(z_serialize)]>;
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+// A pseudo instruction that serves as a compiler barrier.
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+let hasSideEffects = 1 in
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+def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>;
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+
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let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in {
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def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_32, GR32>;
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def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_64, GR64>;
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Index: llvm/trunk/lib/Target/SystemZ/SystemZOperators.td
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===================================================================
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--- llvm/trunk/lib/Target/SystemZ/SystemZOperators.td
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+++ llvm/trunk/lib/Target/SystemZ/SystemZOperators.td
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@@ -188,6 +188,8 @@
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def z_serialize : SDNode<"SystemZISD::SERIALIZE", SDTNone,
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[SDNPHasChain, SDNPMayStore]>;
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+def z_membarrier : SDNode<"SystemZISD::MEMBARRIER", SDTNone,
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+ [SDNPHasChain, SDNPSideEffect]>;
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// Defined because the index is an i32 rather than a pointer.
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def z_vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
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Index: llvm/trunk/test/CodeGen/SystemZ/atomic-fence-01.ll
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===================================================================
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--- llvm/trunk/test/CodeGen/SystemZ/atomic-fence-01.ll
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+++ llvm/trunk/test/CodeGen/SystemZ/atomic-fence-01.ll
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@@ -0,0 +1,16 @@
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+; Test (fast) serialization.
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+;
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+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s --check-prefix=Z10
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+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s --check-prefix=Z196
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+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s --check-prefix=ZEC12
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+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s --check-prefix=Z13
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+
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+define void @test() {
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+; Z10: bcr 15, %r0
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+; Z196: bcr 14, %r0
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+; ZEC12: bcr 14, %r0
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+; Z13: bcr 14, %r0
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+ fence seq_cst
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+ ret void
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+}
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+
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Index: llvm/trunk/test/CodeGen/SystemZ/atomic-fence-02.ll
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===================================================================
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--- llvm/trunk/test/CodeGen/SystemZ/atomic-fence-02.ll
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+++ llvm/trunk/test/CodeGen/SystemZ/atomic-fence-02.ll
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@@ -0,0 +1,13 @@
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+; Serialization is emitted only for fence seq_cst.
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+;
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+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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+
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+define void @test() {
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+; CHECK: #MEMBARRIER
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+ fence acquire
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+; CHECK: #MEMBARRIER
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+ fence release
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+; CHECK: #MEMBARRIER
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+ fence acq_rel
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+ ret void
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+}
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@ -7,7 +7,7 @@
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Name: llvm
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Version: 3.8.1
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Release: 1%{?dist}
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Release: 2%{?dist}
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Summary: The Low Level Virtual Machine
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License: NCSA
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@ -19,6 +19,9 @@ Source100: llvm-config.h
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# recognize s390 as SystemZ when configuring build
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Patch0: llvm-3.7.1-cmake-s390.patch
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# backport D18644 [SystemZ] Support ATOMIC_FENCE
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Patch1: llvm-d18644-systemz-atomic-fence.patch
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BuildRequires: cmake
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BuildRequires: zlib-devel
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BuildRequires: libffi-devel
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@ -70,6 +73,7 @@ Static libraries for the LLVM compiler infrastructure.
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%prep
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%setup -q -n %{name}-%{version}.src
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%patch0 -p1 -b .s390
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%patch1 -p2 -b .s390-fence
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%build
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mkdir -p _build
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@ -185,6 +189,9 @@ make check-all || :
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%{_libdir}/*.a
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%changelog
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* Sat Jan 07 2017 Josh Stone <jistone@redhat.com> - 3.8.1-2
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- Support s390x atomic fence
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* Wed Jul 13 2016 Adam Jackson <ajax@redhat.com> - 3.8.1-1
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- llvm 3.8.1
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- Add mips target
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