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Backport r327651 from trunk rhbz#1554349

This commit is contained in:
Tom Stellard 2018-03-19 22:51:24 +00:00
parent 1afade5cd8
commit 699e7bbabc
2 changed files with 74 additions and 1 deletions
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69
0001-PPC-Avoid-non-simple-MVT-in-STBRX-optimization.patch Normal file
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@ -0,0 +1,69 @@
From 1a3f524e3c4da0393569f007ece81fe3ecb9352d Mon Sep 17 00:00:00 2001
From: Guozhi Wei <carrot@google.com>
Date: Thu, 15 Mar 2018 17:49:12 +0000
Subject: [PATCH] [PPC] Avoid non-simple MVT in STBRX optimization
PR35402 triggered this case. It bswap and stores a 48bit value, current STBRX optimization transforms it into STBRX. Unfortunately 48bit is not a simple MVT, there is no PPC instruction to support it, and it can't be automatically expanded by llvm, so caused a crash.
This patch detects the non-simple MVT and returns early.
Differential Revision: https://reviews.llvm.org/D44500
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327651 91177308-0d34-0410-b5e6-96231b3b80d8
---
lib/Target/PowerPC/PPCISelLowering.cpp | 6 +++++-
test/CodeGen/PowerPC/pr35402.ll | 18 ++++++++++++++++++
2 files changed, 23 insertions(+), 1 deletion(-)
create mode 100644 test/CodeGen/PowerPC/pr35402.ll
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index f9de65f..eeb1bf1 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -12221,6 +12221,11 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
N->getOperand(1).getValueType() == MVT::i16 ||
(Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
N->getOperand(1).getValueType() == MVT::i64))) {
+ // STBRX can only handle simple types.
+ EVT mVT = cast<StoreSDNode>(N)->getMemoryVT();
+ if (mVT.isExtended())
+ break;
+
SDValue BSwapOp = N->getOperand(1).getOperand(0);
// Do an any-extend to 32-bits if this is a half-word input.
if (BSwapOp.getValueType() == MVT::i16)
@@ -12228,7 +12233,6 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
// If the type of BSWAP operand is wider than stored memory width
// it need to be shifted to the right side before STBRX.
- EVT mVT = cast<StoreSDNode>(N)->getMemoryVT();
if (Op1VT.bitsGT(mVT)) {
int Shift = Op1VT.getSizeInBits() - mVT.getSizeInBits();
BSwapOp = DAG.getNode(ISD::SRL, dl, Op1VT, BSwapOp,
diff --git a/test/CodeGen/PowerPC/pr35402.ll b/test/CodeGen/PowerPC/pr35402.ll
new file mode 100644
index 0000000..06e6d96
--- /dev/null
+++ b/test/CodeGen/PowerPC/pr35402.ll
@@ -0,0 +1,18 @@
+; RUN: llc -O2 < %s | FileCheck %s
+target triple = "powerpc64le-linux-gnu"
+
+define void @test(i8* %p, i64 %data) {
+entry:
+ %0 = tail call i64 @llvm.bswap.i64(i64 %data)
+ %ptr = bitcast i8* %p to i48*
+ %val = trunc i64 %0 to i48
+ store i48 %val, i48* %ptr, align 1
+ ret void
+
+; CHECK: sth
+; CHECK: stw
+; CHECK-NOT: stdbrx
+
+}
+
+declare i64 @llvm.bswap.i64(i64)
--
1.8.3.1

6
llvm.spec
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@ -12,7 +12,7 @@
Name: llvm
Version: %{maj_ver}.%{min_ver}.%{patch_ver}
Release: 7%{?dist}
Release: 8%{?dist}
Summary: The Low Level Virtual Machine
License: NCSA
@ -25,6 +25,7 @@ Patch3: 0001-CMake-Split-static-library-exports-into-their-own-ex.patch
Patch5: 0001-DebugInfo-Discard-invalid-DBG_VALUE-instructions-in-.patch
Patch6: 0001-Fixup-for-rL326769-RegState-Debug-is-being-truncated.patch
Patch7: 0001-Filter-out-cxxflags-not-supported-by-clang.patch
Patch8: 0001-PPC-Avoid-non-simple-MVT-in-STBRX-optimization.patch
BuildRequires: cmake
BuildRequires: ninja-build
@ -216,6 +217,9 @@ fi
%{_libdir}/cmake/llvm/LLVMStaticExports.cmake
%changelog
* Mon Mar 19 2018 Tom Stellard <tstellar@redhat.com> - 6.0.0-8
- Backport r327651 from trunk rhbz#1554349
* Fri Mar 16 2018 Tom Stellard <tstellar@redhat.com> - 6.0.0-7
- Filter out cxxflags and cflags from llvm-config that aren't supported by clang
- rhbz#1556980