David Abdurachmanov
43dcced80c
- SECCOMP v2 was posted for review (one failing kernel selftest) - SiFive Ethernet driver is approved upstream and might land in 5.3 - SiFive CPUFreq support is WIP, but people reported it working Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
141 lines
3.7 KiB
Diff
141 lines
3.7 KiB
Diff
From 8d741d97eeb3a0c1b9aa09da15fbb1c5c7214fcd Mon Sep 17 00:00:00 2001
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From: Fedora Kernel Team <kernel-team@fedoraproject.org>
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Date: Sun, 25 Aug 2019 06:58:34 +0000
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Subject: [PATCH 2/2] SiFive Unleashed CPUFreq
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Signed-off-by: Fedora Kernel Team <kernel-team@fedoraproject.org>
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---
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arch/riscv/Kconfig | 8 +++++
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arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 +++
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.../boot/dts/sifive/hifive-unleashed-a00.dts | 34 +++++++++++++++++++
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arch/riscv/configs/defconfig | 5 +++
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4 files changed, 52 insertions(+)
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diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
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index 441e63f..ccd590c 100644
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--- a/arch/riscv/Kconfig
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+++ b/arch/riscv/Kconfig
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@@ -298,6 +298,14 @@ endchoice
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endmenu
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+menu "CPU Power Management"
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+
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+source "drivers/cpuidle/Kconfig"
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+
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+source "drivers/cpufreq/Kconfig"
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+
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+endmenu
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+
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menu "Power management options"
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source "kernel/power/Kconfig"
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diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
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index 42b5ec2..b07079f 100644
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--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
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+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
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@@ -29,6 +29,7 @@
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i-cache-size = <16384>;
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reg = <0>;
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riscv,isa = "rv64imac";
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+ clocks = <&prci PRCI_CLK_COREPLL>;
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status = "disabled";
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cpu0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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@@ -53,6 +54,7 @@
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reg = <1>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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+ clocks = <&prci PRCI_CLK_COREPLL>;
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cpu1_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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@@ -77,6 +79,7 @@
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reg = <2>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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+ clocks = <&prci PRCI_CLK_COREPLL>;
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cpu2_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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@@ -101,6 +104,7 @@
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reg = <3>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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+ clocks = <&prci PRCI_CLK_COREPLL>;
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cpu3_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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@@ -125,6 +129,7 @@
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reg = <4>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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+ clocks = <&prci PRCI_CLK_COREPLL>;
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cpu4_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
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index 54fc701..5b43bdf 100644
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--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
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+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
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@@ -40,6 +40,40 @@
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clock-frequency = <RTCCLK_FREQ>;
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clock-output-names = "rtcclk";
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};
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+
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+ fu540_c000_opp_table: opp-table {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp-350000000 {
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+ opp-hz = /bits/ 64 <350000000>;
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+ };
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+ opp-700000000 {
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+ opp-hz = /bits/ 64 <700000000>;
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+ };
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+ opp-999999999 {
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+ opp-hz = /bits/ 64 <999999999>;
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+ };
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+ opp-1400000000 {
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+ opp-hz = /bits/ 64 <1400000000>;
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+ };
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+ };
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+};
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+
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+&cpu0 {
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+ operating-points-v2 = <&fu540_c000_opp_table>;
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+};
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+&cpu1 {
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+ operating-points-v2 = <&fu540_c000_opp_table>;
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+};
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+&cpu2 {
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+ operating-points-v2 = <&fu540_c000_opp_table>;
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+};
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+&cpu3 {
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+ operating-points-v2 = <&fu540_c000_opp_table>;
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+};
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+&cpu4 {
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+ operating-points-v2 = <&fu540_c000_opp_table>;
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};
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&uart0 {
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diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
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index 3efff55..c9542a9 100644
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--- a/arch/riscv/configs/defconfig
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+++ b/arch/riscv/configs/defconfig
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@@ -16,6 +16,11 @@ CONFIG_EXPERT=y
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CONFIG_BPF_SYSCALL=y
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CONFIG_SOC_SIFIVE=y
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CONFIG_SMP=y
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+CONFIG_CPU_IDLE=y
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+CONFIG_CPU_FREQ=y
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+CONFIG_CPU_FREQ_STAT=y
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+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
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+CONFIG_CPUFREQ_DT=y
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CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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CONFIG_NET=y
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--
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2.23.0
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