kernel/0002-SiFive-Unleashed-CPUFreq.patch
David Abdurachmanov 43dcced80c
Update out-of-tree patches for RISC-V (riscv64)
- SECCOMP v2 was posted for review (one failing kernel selftest)
- SiFive Ethernet driver is approved upstream and might land in 5.3
- SiFive CPUFreq support is WIP, but people reported it working

Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
2019-08-25 00:03:31 -07:00

141 lines
3.7 KiB
Diff

From 8d741d97eeb3a0c1b9aa09da15fbb1c5c7214fcd Mon Sep 17 00:00:00 2001
From: Fedora Kernel Team <kernel-team@fedoraproject.org>
Date: Sun, 25 Aug 2019 06:58:34 +0000
Subject: [PATCH 2/2] SiFive Unleashed CPUFreq
Signed-off-by: Fedora Kernel Team <kernel-team@fedoraproject.org>
---
arch/riscv/Kconfig | 8 +++++
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 +++
.../boot/dts/sifive/hifive-unleashed-a00.dts | 34 +++++++++++++++++++
arch/riscv/configs/defconfig | 5 +++
4 files changed, 52 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 441e63f..ccd590c 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -298,6 +298,14 @@ endchoice
endmenu
+menu "CPU Power Management"
+
+source "drivers/cpuidle/Kconfig"
+
+source "drivers/cpufreq/Kconfig"
+
+endmenu
+
menu "Power management options"
source "kernel/power/Kconfig"
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index 42b5ec2..b07079f 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -29,6 +29,7 @@
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
+ clocks = <&prci PRCI_CLK_COREPLL>;
status = "disabled";
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -53,6 +54,7 @@
reg = <1>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&prci PRCI_CLK_COREPLL>;
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -77,6 +79,7 @@
reg = <2>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&prci PRCI_CLK_COREPLL>;
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -101,6 +104,7 @@
reg = <3>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&prci PRCI_CLK_COREPLL>;
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -125,6 +129,7 @@
reg = <4>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&prci PRCI_CLK_COREPLL>;
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
index 54fc701..5b43bdf 100644
--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
@@ -40,6 +40,40 @@
clock-frequency = <RTCCLK_FREQ>;
clock-output-names = "rtcclk";
};
+
+ fu540_c000_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-350000000 {
+ opp-hz = /bits/ 64 <350000000>;
+ };
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ };
+ opp-999999999 {
+ opp-hz = /bits/ 64 <999999999>;
+ };
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&fu540_c000_opp_table>;
+};
+&cpu1 {
+ operating-points-v2 = <&fu540_c000_opp_table>;
+};
+&cpu2 {
+ operating-points-v2 = <&fu540_c000_opp_table>;
+};
+&cpu3 {
+ operating-points-v2 = <&fu540_c000_opp_table>;
+};
+&cpu4 {
+ operating-points-v2 = <&fu540_c000_opp_table>;
};
&uart0 {
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 3efff55..c9542a9 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -16,6 +16,11 @@ CONFIG_EXPERT=y
CONFIG_BPF_SYSCALL=y
CONFIG_SOC_SIFIVE=y
CONFIG_SMP=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+CONFIG_CPUFREQ_DT=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_NET=y
--
2.23.0