48 lines
1.4 KiB
Diff
48 lines
1.4 KiB
Diff
From a4113791ab3f8a0723b7b8c6d3eedeac91858606 Mon Sep 17 00:00:00 2001
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From: chenshuo <chenshuo@eswincomputing.com>
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Date: Tue, 23 Jul 2024 14:38:55 +0800
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Subject: [PATCH 110/219] refactor:remove 1.5GHz~1.8GHz cpu freq
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Changelogs:
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remove 1.5GHz~1.8GHz from d0_cpu_opp_table because evb not support dynamic voltage regulation.
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Signed-off-by: chenshuo <chenshuo@eswincomputing.com>
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---
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.../dts/eswin/eswin-win2030-die0-soc.dtsi | 20 -------------------
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1 file changed, 20 deletions(-)
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diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
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index fea1f577fddc..3b2961f29389 100644
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--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
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+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
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@@ -103,26 +103,6 @@ opp-1400000000 {
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opp-microvolt = <800000>;
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clock-latency-ns = <70000>;
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};
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- opp-1500000000 {
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- opp-hz = /bits/ 64 <CLK_FREQ_1500M>;
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- opp-microvolt = <800000>;
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- clock-latency-ns = <70000>;
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- };
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- opp-1600000000 {
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- opp-hz = /bits/ 64 <CLK_FREQ_1600M>;
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- opp-microvolt = <800000>;
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- clock-latency-ns = <70000>;
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- };
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- opp-1700000000 {
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- opp-hz = /bits/ 64 <CLK_FREQ_1700M>;
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- opp-microvolt = <800000>;
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- clock-latency-ns = <70000>;
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- };
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- opp-1800000000 {
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- opp-hz = /bits/ 64 <CLK_FREQ_1800M>;
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- opp-microvolt = <800000>;
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- clock-latency-ns = <70000>;
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- };
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};
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};
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--
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2.47.0
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