91 lines
3.4 KiB
Diff
91 lines
3.4 KiB
Diff
From 17e45034166c22497ced74a71d0621c26a204b9f Mon Sep 17 00:00:00 2001
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From: Fedora Kernel Team <kernel-team@fedoraproject.org>
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Date: Thu, 6 Dec 2018 09:16:51 +0000
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Subject: [PATCH] riscv64 fixes
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---
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arch/riscv/Kconfig | 1 +
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arch/riscv/include/uapi/asm/syscalls.h | 29 ++++++++++++++++++++++++++
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arch/riscv/include/uapi/asm/unistd.h | 20 +-----------------
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3 files changed, 31 insertions(+), 19 deletions(-)
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create mode 100644 arch/riscv/include/uapi/asm/syscalls.h
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diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
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index 55da93f..e4e8bcd 100644
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--- a/arch/riscv/Kconfig
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+++ b/arch/riscv/Kconfig
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@@ -43,6 +43,7 @@ config RISCV
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select RISCV_TIMER
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select GENERIC_IRQ_MULTI_HANDLER
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select ARCH_HAS_PTE_SPECIAL
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+ select ARCH_HAS_SG_CHAIN
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config MMU
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def_bool y
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diff --git a/arch/riscv/include/uapi/asm/syscalls.h b/arch/riscv/include/uapi/asm/syscalls.h
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new file mode 100644
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index 0000000..206dc4b
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--- /dev/null
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+++ b/arch/riscv/include/uapi/asm/syscalls.h
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@@ -0,0 +1,29 @@
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+/* SPDX-License-Identifier: GPL-2.0 */
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+/*
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+ * Copyright (C) 2017-2018 SiFive
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+ */
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+
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+/*
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+ * There is explicitly no include guard here because this file is expected to
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+ * be included multiple times in order to define the syscall macros via
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+ * __SYSCALL.
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+ */
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+
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+/*
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+ * Allows the instruction cache to be flushed from userspace. Despite RISC-V
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+ * having a direct 'fence.i' instruction available to userspace (which we
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+ * can't trap!), that's not actually viable when running on Linux because the
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+ * kernel might schedule a process on another hart. There is no way for
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+ * userspace to handle this without invoking the kernel (as it doesn't know the
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+ * thread->hart mappings), so we've defined a RISC-V specific system call to
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+ * flush the instruction cache.
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+ *
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+ * __NR_riscv_flush_icache is defined to flush the instruction cache over an
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+ * address range, with the flush applying to either all threads or just the
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+ * caller. We don't currently do anything with the address range, that's just
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+ * in there for forwards compatibility.
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+ */
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+#ifndef __NR_riscv_flush_icache
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+#define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15)
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+#endif
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+__SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache)
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diff --git a/arch/riscv/include/uapi/asm/unistd.h b/arch/riscv/include/uapi/asm/unistd.h
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index 1f3bd3e..0610313 100644
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--- a/arch/riscv/include/uapi/asm/unistd.h
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+++ b/arch/riscv/include/uapi/asm/unistd.h
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@@ -20,22 +20,4 @@
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#endif /* __LP64__ */
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#include <asm-generic/unistd.h>
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-
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-/*
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- * Allows the instruction cache to be flushed from userspace. Despite RISC-V
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- * having a direct 'fence.i' instruction available to userspace (which we
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- * can't trap!), that's not actually viable when running on Linux because the
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- * kernel might schedule a process on another hart. There is no way for
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- * userspace to handle this without invoking the kernel (as it doesn't know the
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- * thread->hart mappings), so we've defined a RISC-V specific system call to
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- * flush the instruction cache.
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- *
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- * __NR_riscv_flush_icache is defined to flush the instruction cache over an
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- * address range, with the flush applying to either all threads or just the
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- * caller. We don't currently do anything with the address range, that's just
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- * in there for forwards compatibility.
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- */
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-#ifndef __NR_riscv_flush_icache
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-#define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15)
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-#endif
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-__SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache)
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+#include <asm/syscalls.h>
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--
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2.20.0.rc2
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