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kernel/0380-WIN2030-16969-fix-i2s-binding-DMA-channels.patch
Jason Montleon a8df14b44d Update to 6.6.80
2025-02-27 20:57:56 -05:00

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From ffc0e9973f0bab3878a272ef2205123d78c07246 Mon Sep 17 00:00:00 2001
From: denglei <denglei@eswincomputing.com>
Date: Thu, 9 Jan 2025 17:03:33 +0800
Subject: [PATCH 380/416] WIN2030-16969:fix:i2s binding DMA channels.
Changelogs:
i2s binding DMA channels.
Change-Id: Ib3e395d82202340d95f85a2751acaadfdea7ce38
Signed-off-by: denglei <denglei@eswincomputing.com>
---
.../dts/eswin/eswin-win2030-die0-soc.dtsi | 12 ++++-----
.../dts/eswin/eswin-win2030-die1-soc.dtsi | 14 +++++-----
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 27 ++++++++++++++++---
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 5 ++++
sound/soc/eswin/esw-dma.c | 8 ++++--
5 files changed, 47 insertions(+), 19 deletions(-)
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
index 720d8b672af2..f35057654baa 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
@@ -352,7 +352,7 @@ d0_aon_dmac: dma-controller-aon@0x518c0000 {
reg = <0x0 0x518c0000 0x0 0x10000>;
interrupt-parent = <&plic0>;
interrupts = <289>;
- #dma-cells = <2>; // change dma-cells value <1> to <2>, to support peripheral selection dma-controller,See the parameter dmas for details;
+ #dma-cells = <3>; // dma-cells <request channel id, handshake number, dma sel bit>;
clocks = <&d0_clock WIN2030_CLK_AONDMA_ACLK>,
<&d0_clock WIN2030_CLK_AONDMA_CFG>;
clock-names = "core-clk", "cfgr-clk";
@@ -381,7 +381,7 @@ d0_dmac0: dma-controller-hsp@0x50430000 {
reg = <0x0 0x50430000 0x0 0x10000>;
interrupt-parent = <&plic0>;
interrupts = <57>;
- #dma-cells = <2>; // change dma-cells value <1> to <2>, to support peripheral selection dma-controller,See the parameter dmas for details;
+ #dma-cells = <3>; // dma-cells <request channel id, handshake number, dma sel bit>;
clocks = <&d0_clock WIN2030_CLK_HSP_DMA0_CLK>,
<&d0_clock WIN2030_CLK_HSP_DMA0_CLK_TEST>;
clock-names = "core-clk", "cfgr-clk";
@@ -1486,7 +1486,7 @@ d0_aon_i2c0: i2c@51830000 {
* 41 : i2c0 aon dma handshake number
* 0xff : no need to select to dma controller
*/
- dmas = <&d0_aon_dmac 41 0xff>, <&d0_aon_dmac 42 0xff>;
+ dmas = <&d0_aon_dmac 10 41 0xff>, <&d0_aon_dmac 11 42 0xff>;
numa-node-id = <0>;
};
d0_aon_i2c1: i2c@51838000 {
@@ -1751,7 +1751,7 @@ d0_i2s0: i2s0@50200000 {
#sound-dai-cells = <0x00000000>;
reg = <0x0 0x50200000 0x0 0x10000>;
dma-names = "rx", "tx";
- dmas = <&d0_aon_dmac 4 0>, <&d0_aon_dmac 5 0>;
+ dmas = <&d0_aon_dmac 4 4 0>, <&d0_aon_dmac 5 5 0>;
vo_mclk_sel,syscrg = <&d0_sys_crg 0x1bc>;
resets = <&d0_reset VO_I2SRST_CTRL SW_VO_I2S_RSTN>,
<&d0_reset VO_I2SRST_CTRL SW_VO_I2S_PRSTN>,
@@ -1771,7 +1771,7 @@ d0_i2s1: i2s1@50210000 {
#sound-dai-cells = <0x00000000>;
reg = <0x0 0x50210000 0x0 0x10000>;
dma-names = "rx", "tx";
- dmas = <&d0_aon_dmac 2 1>, <&d0_aon_dmac 3 1>;
+ dmas = <&d0_aon_dmac 6 2 1>, <&d0_aon_dmac 7 3 1>;
vo_mclk_sel,syscrg = <&d0_sys_crg 0x1bc>;
resets = <&d0_reset VO_I2SRST_CTRL SW_VO_I2S_RSTN>,
<&d0_reset VO_I2SRST_CTRL SW_VO_I2S_PRSTN>,
@@ -1791,7 +1791,7 @@ d0_i2s2: i2s2@50220000 {
#sound-dai-cells = <0x00000000>;
reg = <0x0 0x50220000 0x0 0x10000>;
dma-names = "rx", "tx";
- dmas = <&d0_aon_dmac 0 2>, <&d0_aon_dmac 1 2>;
+ dmas = <&d0_aon_dmac 8 0 2>, <&d0_aon_dmac 9 1 2>;
vo_mclk_sel,syscrg = <&d0_sys_crg 0x1bc>;
resets = <&d0_reset VO_I2SRST_CTRL SW_VO_I2S_RSTN>,
<&d0_reset VO_I2SRST_CTRL SW_VO_I2S_PRSTN>,
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
index 96cf2b22d8d5..42978f4a4cdc 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
@@ -322,7 +322,7 @@ d1_aon_dmac: dma-controller-aon@0x718c0000 {
reg = <0x0 0x718c0000 0x0 0x10000>;
interrupt-parent = <&plic1>;
interrupts = <289>;
- #dma-cells = <2>; // change dma-cells value <1> to <2>, to support peripheral selection dma-controller,See the parameter dmas for details;
+ #dma-cells = <3>; // dma-cells <request channel id, handshake number, dma sel bit>;
clocks = <&d1_clock WIN2030_CLK_AONDMA_ACLK>,
<&d1_clock WIN2030_CLK_AONDMA_CFG>;
clock-names = "core-clk", "cfgr-clk";
@@ -351,7 +351,7 @@ d1_dmac0: dma-controller-hsp@0x70430000 {
reg = <0x0 0x70430000 0x0 0x10000>;
interrupt-parent = <&plic1>;
interrupts = <57>;
- #dma-cells = <2>; // change dma-cells value <1> to <2>, to support peripheral selection dma-controller,See the parameter dmas for details;
+ #dma-cells = <3>; // dma-cells <request channel id, handshake number, dma sel bit>;
clocks = <&d1_clock WIN2030_CLK_HSP_DMA0_CLK>,
<&d1_clock WIN2030_CLK_HSP_DMA0_CLK_TEST>;
clock-names = "core-clk", "cfgr-clk";
@@ -746,7 +746,7 @@ d1_i2c0: i2c@70950000 {
* 24 : i2c0 aon dma handshake number
* 6 : i2c0 dma controller sel bit in sys_son dma_cfg reg(offset 0x370)
*/
- dmas = <&d1_aon_dmac 24 6>, <&d1_aon_dmac 25 6>;
+ dmas = <&d1_aon_dmac 10 24 6>, <&d1_aon_dmac 11 25 6>;
numa-node-id = <1>;
};
d1_i2c1: i2c@70960000 {
@@ -920,7 +920,7 @@ d1_aon_i2c0: i2c@71830000 {
* 41 : i2c0 aon dma handshake number
* 0xff : no need to select to dma controller
*/
- dmas = <&d1_aon_dmac 41 0xff>, <&d1_aon_dmac 42 0xff>;
+ dmas = <&d1_aon_dmac 12 41 0xff>, <&d1_aon_dmac 13 42 0xff>;
numa-node-id = <1>;
};
d1_aon_i2c1: i2c@71838000 {
@@ -1253,7 +1253,7 @@ d1_i2s0: i2s0@70200000 {
#sound-dai-cells = <0x00000000>;
reg = <0x0 0x70200000 0x0 0x10000>;
dma-names = "rx", "tx";
- dmas = <&d1_aon_dmac 4 0>, <&d1_aon_dmac 5 0>;
+ dmas = <&d1_aon_dmac 4 4 0>, <&d1_aon_dmac 5 5 0>;
vo_mclk_sel,syscrg = <&d1_sys_crg 0x1bc>;
resets = <&d1_reset VO_I2SRST_CTRL SW_VO_I2S_RSTN>,
<&d1_reset VO_I2SRST_CTRL SW_VO_I2S_PRSTN>,
@@ -1273,7 +1273,7 @@ d1_i2s1: i2s1@70210000 {
#sound-dai-cells = <0x00000000>;
reg = <0x0 0x70210000 0x0 0x10000>;
dma-names = "rx", "tx";
- dmas = <&d1_aon_dmac 2 1>, <&d1_aon_dmac 3 1>;
+ dmas = <&d1_aon_dmac 6 2 1>, <&d1_aon_dmac 7 3 1>;
vo_mclk_sel,syscrg = <&d1_sys_crg 0x1bc>;
resets = <&d1_reset VO_I2SRST_CTRL SW_VO_I2S_RSTN>,
<&d1_reset VO_I2SRST_CTRL SW_VO_I2S_PRSTN>,
@@ -1293,7 +1293,7 @@ d1_i2s2: i2s@70220000 {
#sound-dai-cells = <0x00000000>;
reg = <0x0 0x70220000 0x0 0x10000>;
dma-names = "rx", "tx";
- dmas = <&d1_aon_dmac 0 2>, <&d1_aon_dmac 1 2>;
+ dmas = <&d1_aon_dmac 8 0 2>, <&d1_aon_dmac 9 1 2>;
vo_mclk_sel,syscrg = <&d1_sys_crg 0x1bc>;
resets = <&d1_reset VO_I2SRST_CTRL SW_VO_I2S_RSTN>,
<&d1_reset VO_I2SRST_CTRL SW_VO_I2S_PRSTN>,
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 152ef7167318..470f5d0e60dc 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -1415,23 +1415,42 @@ int win2030_dma_sel_cfg(struct axi_dma_chan *chan, u32 val)
return 0;
}
+static bool axi_dma_filter_fn(struct dma_chan *dchan, void *param)
+{
+ struct axi_dma_filter_data *fdata = param;
+
+ if (dchan->device->dev != fdata->dw_dma->dma.dev)
+ return false;
+
+ if (fdata->request != dchan->chan_id)
+ return false;
+
+ return true;
+}
+
static struct dma_chan *dw_axi_dma_of_xlate(struct of_phandle_args *dma_spec,
struct of_dma *ofdma)
{
struct dw_axi_dma *dw = ofdma->of_dma_data;
struct axi_dma_chan *chan;
struct dma_chan *dchan;
+ struct axi_dma_filter_data fdata;
- dchan = dma_get_any_slave_channel(&dw->dma);
- if (!dchan)
+ fdata.dw_dma = dw,
+ fdata.request = dma_spec->args[0];
+
+ dchan = dma_request_channel(dw->dma.cap_mask, axi_dma_filter_fn, &fdata);
+ if (!dchan) {
+ dev_err(dw->dma.dev, "request chan failed\n");
return NULL;
+ }
chan = dchan_to_axi_dma_chan(dchan);
- chan->hw_handshake_num = dma_spec->args[0];
+ chan->hw_handshake_num = dma_spec->args[1];
int flags = (uintptr_t)of_device_get_match_data(chan->chip->dev);
if (flags & AXI_DMA_FLAG_HAS_EIC7700) {
if (dma_spec->args_count > 1)
- win2030_dma_sel_cfg(chan, dma_spec->args[1]);
+ win2030_dma_sel_cfg(chan, dma_spec->args[2]);
}
return dchan;
}
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 738954532c93..bcbc75598af5 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -95,6 +95,11 @@ struct axi_dma_chip {
spinlock_t lock;
};
+struct axi_dma_filter_data {
+ struct dw_axi_dma *dw_dma;
+ int request;
+};
+
/* LLI == Linked List Item */
struct __packed axi_dma_lli {
__le64 sar;
diff --git a/sound/soc/eswin/esw-dma.c b/sound/soc/eswin/esw-dma.c
index 56de39b82b76..2fee4120acd2 100644
--- a/sound/soc/eswin/esw-dma.c
+++ b/sound/soc/eswin/esw-dma.c
@@ -429,6 +429,7 @@ int esw_pcm_dma_dai_register(struct i2s_dev *chip)
dev_warn(chip->dev, "request dma channel[%s] failed\n", channel_names0);
return -EPROBE_DEFER;
}
+ chip->chan[SNDRV_PCM_STREAM_PLAYBACK] = NULL;
dev_warn(chip->dev, "dma channel[%s] is NULL\n", channel_names0);
} else {
chip->chan[SNDRV_PCM_STREAM_PLAYBACK] = chan0;
@@ -448,6 +449,7 @@ int esw_pcm_dma_dai_register(struct i2s_dev *chip)
ret = -EPROBE_DEFER;
goto release_buf0;
}
+ chip->chan[SNDRV_PCM_STREAM_CAPTURE] = NULL;
dev_warn(chip->dev, "dma channel[%s] is NULL\n", channel_names1);
} else {
chip->chan[SNDRV_PCM_STREAM_CAPTURE] = chan1;
@@ -475,11 +477,13 @@ int esw_pcm_dma_dai_register(struct i2s_dev *chip)
release_buf1:
kfree(chip->conv_buf[1]);
release_chan1:
- dma_release_channel(chip->chan[1]);
+ if (chip->chan[1])
+ dma_release_channel(chip->chan[1]);
release_buf0:
kfree(chip->conv_buf[0]);
release_chan0:
- dma_release_channel(chip->chan[0]);
+ if (chip->chan[0])
+ dma_release_channel(chip->chan[0]);
return ret;
}
\ No newline at end of file
--
2.47.0
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