114 lines
3.8 KiB
Diff
114 lines
3.8 KiB
Diff
From f65eaefc7d96241df3471daed8f32af20eb6c6d9 Mon Sep 17 00:00:00 2001
|
|
From: ningyu <ningyu@eswincomputing.com>
|
|
Date: Wed, 6 Nov 2024 15:13:54 +0800
|
|
Subject: [PATCH 280/416] WIN2030-16035:fix:Fixbug double ddr controllers
|
|
driver
|
|
|
|
Changelogs:
|
|
1. Bugfix for support die0 and die1's ddr controller driver register
|
|
2. Set fan max speed default
|
|
|
|
Change-Id: I261987931c8c356688644553229e781bd6173341
|
|
Signed-off-by: ningyu <ningyu@eswincomputing.com>
|
|
---
|
|
.../boot/dts/eswin/eswin-win2030-die0-soc.dtsi | 4 ++--
|
|
.../boot/dts/eswin/eswin-win2030-die1-soc.dtsi | 4 ++--
|
|
drivers/edac/eswin_edac.c | 16 ++++++++--------
|
|
drivers/hwmon/eswin-fan-control.c | 2 +-
|
|
4 files changed, 13 insertions(+), 13 deletions(-)
|
|
|
|
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
|
|
index 0d217f5a9a58..dd1fedbdbabe 100644
|
|
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
|
|
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
|
|
@@ -2308,7 +2308,7 @@ d0_numa_sample:numa_sample@0 {
|
|
dma-noncoherent;
|
|
};
|
|
|
|
- ddr0: ddr-controller@0 {
|
|
+ ddr0: ddr-controller@52300000 {
|
|
compatible = "eswin,ddrc-1.20a";
|
|
interrupt-parent = <&plic0>;
|
|
interrupts = <10>;
|
|
@@ -2319,7 +2319,7 @@ ddr0: ddr-controller@0 {
|
|
status = "disabled";
|
|
};
|
|
|
|
- ddr1: ddr-controller@1 {
|
|
+ ddr1: ddr-controller@52380000 {
|
|
compatible = "eswin,ddrc-1.20a";
|
|
interrupt-parent = <&plic0>;
|
|
interrupts = <299>;
|
|
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
|
|
index e5580ff203fb..c05df53e7bf5 100644
|
|
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
|
|
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
|
|
@@ -2363,7 +2363,7 @@ d1_numa_sample:numa_sample@1 {
|
|
dma-noncoherent;
|
|
};
|
|
|
|
- d1_ddr0: ddr-controller@0 {
|
|
+ d1_ddr0: ddr-controller@72300000 {
|
|
compatible = "eswin,ddrc-1.20a";
|
|
interrupt-parent = <&plic1>;
|
|
interrupts = <10>;
|
|
@@ -2374,7 +2374,7 @@ d1_ddr0: ddr-controller@0 {
|
|
status = "disabled";
|
|
};
|
|
|
|
- d1_ddr1: ddr-controller@1 {
|
|
+ d1_ddr1: ddr-controller@72380000 {
|
|
compatible = "eswin,ddrc-1.20a";
|
|
interrupt-parent = <&plic1>;
|
|
interrupts = <299>;
|
|
diff --git a/drivers/edac/eswin_edac.c b/drivers/edac/eswin_edac.c
|
|
index 82d75406cc48..508010cf4434 100644
|
|
--- a/drivers/edac/eswin_edac.c
|
|
+++ b/drivers/edac/eswin_edac.c
|
|
@@ -1337,13 +1337,13 @@ static int mc_probe(struct platform_device *pdev)
|
|
goto free_edac_mc;
|
|
}
|
|
|
|
- rc = edac_mc_add_mc(mci);
|
|
- if (rc)
|
|
- {
|
|
- edac_printk(KERN_ERR, EDAC_MC,
|
|
- "Failed to register with EDAC core\n");
|
|
- goto free_edac_mc;
|
|
- }
|
|
+ // rc = edac_mc_add_mc(mci);
|
|
+ // if (rc)
|
|
+ // {
|
|
+ // edac_printk(KERN_ERR, EDAC_MC,
|
|
+ // "Failed to register with EDAC core\n");
|
|
+ // goto free_edac_mc;
|
|
+ // }
|
|
|
|
#ifdef CONFIG_EDAC_DEBUG
|
|
if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT)
|
|
@@ -1366,7 +1366,7 @@ static int mc_probe(struct platform_device *pdev)
|
|
*/
|
|
if (!(priv->p_data->quirks & DDR_ECC_INTR_SUPPORT))
|
|
writel(0x0, baseaddr + ECC_CTRL_OFST);
|
|
-
|
|
+ edac_printk(KERN_INFO, EDAC_MC, "%s init succ\n",pdev->name);
|
|
return rc;
|
|
|
|
free_edac_mc:
|
|
diff --git a/drivers/hwmon/eswin-fan-control.c b/drivers/hwmon/eswin-fan-control.c
|
|
index 01447e641fa3..b1b48b5ec94b 100644
|
|
--- a/drivers/hwmon/eswin-fan-control.c
|
|
+++ b/drivers/hwmon/eswin-fan-control.c
|
|
@@ -510,7 +510,7 @@ static int eswin_fan_control_probe(struct platform_device *pdev)
|
|
pwm_get_args(ctl->pwm, &pwm_args);
|
|
|
|
state.period = pwm_args.period;
|
|
- state.duty_cycle = state.period/2;
|
|
+ state.duty_cycle = state.period*99/100; /* default set max speed */
|
|
dev_err(&pdev->dev, "state.period: %d state.duty_cycle: %d\n",
|
|
state.period,state.duty_cycle);
|
|
ret = pwm_apply_might_sleep(ctl->pwm, &state);
|
|
--
|
|
2.47.0
|
|
|