485 lines
14 KiB
Diff
485 lines
14 KiB
Diff
From patchwork Fri Mar 7 03:04:42 2014
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: x86: new Intel Atom SoC power management controller driver
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From: "Li, Aubrey" <aubrey.li@linux.intel.com>
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X-Patchwork-Id: 3787341
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Message-Id: <5319374A.60308@linux.intel.com>
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To: Joe Perches <joe@perches.com>
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Cc: "H. Peter Anvin" <hpa@linux.intel.com>,
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Matthew Garrett <mjg59@srcf.ucam.org>, mingo@redhat.com,
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tglx@linutronix.de, linux-kernel@vger.kernel.org,
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"alan@linux.intel.com" <alan@linux.intel.com>
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Date: Fri, 07 Mar 2014 11:04:42 +0800
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On 2014/3/7 10:21, Joe Perches wrote:
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> On Fri, 2014-03-07 at 10:08 +0800, Li, Aubrey wrote:
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>
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>> The Power Management Controller (PMC) controls many of the power
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>> management features present in the SoC. This driver provides
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>> interface to configure the Power Management Controller (PMC).
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>
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> More trivial notes.
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>
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> Nothing really that should stop this from being applied.
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>
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All make sense to me. Welcome your more comments, Joe!
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Thanks,
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-Aubrey
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[PATCH] X86 platform: New Intel Atom SOC power management controller driver
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The Power Management Controller (PMC) controls many of the power
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management features present in the SoC. This driver provides
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interface to configure the Power Management Controller (PMC).
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This driver exposes PMC device state and sleep state residency
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via debugfs:
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/sys/kernel/debugfs/pmc_atom/dev_state
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/sys/kernel/debugfs/pmc_atom/sleep_state
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This driver also provides a native power off function via PMC PCI
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IO port.
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Signed-off-by: Aubrey Li <aubrey.li@intel.com>
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Reviewed-by: Joe Perches <joe@perches.com>
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---
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arch/x86/Kconfig | 4 +
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arch/x86/include/asm/pmc_atom.h | 91 ++++++++++++
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arch/x86/kernel/Makefile | 1 +
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arch/x86/kernel/pmc_atom.c | 297 +++++++++++++++++++++++++++++++++++++++
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4 files changed, 393 insertions(+)
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create mode 100644 arch/x86/include/asm/pmc_atom.h
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create mode 100644 arch/x86/kernel/pmc_atom.c
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diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
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index 0af5250..18f7d38 100644
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--- a/arch/x86/Kconfig
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+++ b/arch/x86/Kconfig
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@@ -2413,6 +2413,10 @@
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tristate
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default m
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depends on PCI
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+
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+config PMC_ATOM
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+ def_bool y
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+ depends on PCI
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source "net/Kconfig"
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diff --git a/arch/x86/include/asm/pmc_atom.h b/arch/x86/include/asm/pmc_atom.h
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new file mode 100644
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index 0000000..43b68fc
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--- /dev/null
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+++ b/arch/x86/include/asm/pmc_atom.h
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@@ -0,0 +1,91 @@
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+/*
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+ * Intel Atom SOC Power Management Controller Header File
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+ * Copyright (c) 2014, Intel Corporation.
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms and conditions of the GNU General Public License,
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+ * version 2, as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope it will be useful, but WITHOUT
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+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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+ * more details.
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+ *
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+ */
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+
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+#ifndef PMC_ATOM_H
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+#define PMC_ATOM_H
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+
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+/* ValleyView Power Control Unit PCI Device ID */
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+#define PCI_DEVICE_ID_VLV_PMC 0x0F1C
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+
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+/* PMC Memory mapped IO registers */
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+#define PMC_BASE_ADDR_OFFSET 0x44
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+#define PMC_BASE_ADDR_MASK 0xFFFFFE00
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+#define PMC_MMIO_REG_LEN 0x100
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+#define PMC_REG_BIT_WIDTH 32
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+
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+/* BIOS uses FUNC_DIS to disable specific function */
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+#define PMC_FUNC_DIS 0x34
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+#define PMC_FUNC_DIS_2 0x38
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+/* The timers acumulate time spent in sleep state */
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+#define PMC_S0IR_TMR 0x80
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+#define PMC_S0I1_TMR 0x84
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+#define PMC_S0I2_TMR 0x88
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+#define PMC_S0I3_TMR 0x8C
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+#define PMC_S0_TMR 0x90
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+/* Sleep state counter is in units of of 32us */
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+#define PMC_TMR_SHIFT 5
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+
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+/* These registers reflect D3 status of functions */
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+#define PMC_D3_STS_0 0xA0
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+
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+#define BIT_LPSS1_F0_DMA BIT(0)
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+#define BIT_LPSS1_F1_PWM1 BIT(1)
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+#define BIT_LPSS1_F2_PWM2 BIT(2)
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+#define BIT_LPSS1_F3_HSUART1 BIT(3)
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+#define BIT_LPSS1_F4_HSUART2 BIT(4)
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+#define BIT_LPSS1_F5_SPI BIT(5)
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+#define BIT_LPSS1_F6_XXX BIT(6)
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+#define BIT_LPSS1_F7_XXX BIT(7)
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+#define BIT_SCC_EMMC BIT(8)
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+#define BIT_SCC_SDIO BIT(9)
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+#define BIT_SCC_SDCARD BIT(10)
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+#define BIT_SCC_MIPI BIT(11)
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+#define BIT_HDA BIT(12)
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+#define BIT_LPE BIT(13)
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+#define BIT_OTG BIT(14)
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+#define BIT_USH BIT(15)
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+#define BIT_GBE BIT(16)
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+#define BIT_SATA BIT(17)
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+#define BIT_USB_EHCI BIT(18)
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+#define BIT_SEC BIT(19)
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+#define BIT_PCIE_PORT0 BIT(20)
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+#define BIT_PCIE_PORT1 BIT(21)
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+#define BIT_PCIE_PORT2 BIT(22)
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+#define BIT_PCIE_PORT3 BIT(23)
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+#define BIT_LPSS2_F0_DMA BIT(24)
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+#define BIT_LPSS2_F1_I2C1 BIT(25)
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+#define BIT_LPSS2_F2_I2C2 BIT(26)
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+#define BIT_LPSS2_F3_I2C3 BIT(27)
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+#define BIT_LPSS2_F4_I2C4 BIT(28)
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+#define BIT_LPSS2_F5_I2C5 BIT(29)
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+#define BIT_LPSS2_F6_I2C6 BIT(30)
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+#define BIT_LPSS2_F7_I2C7 BIT(31)
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+
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+#define PMC_D3_STS_1 0xA4
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+#define BIT_SMB BIT(0)
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+#define BIT_USH_SS_PHY BIT(1)
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+#define BIT_OTG_SS_PHY BIT(2)
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+#define BIT_DFX BIT(3)
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+
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+/* PMC I/O Registers */
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+#define ACPI_BASE_ADDR_OFFSET 0x40
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+#define ACPI_BASE_ADDR_MASK 0xFFFFFE00
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+#define ACPI_MMIO_REG_LEN 0x100
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+
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+#define PM1_CNT 0x4
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+#define SLEEP_TYPE_MASK 0xFFFFECFF
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+#define SLEEP_TYPE_S5 0x1C00
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+#define SLEEP_ENABLE 0x2000
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+#endif /* PMC_ATOM_H */
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diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
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index cb648c8..b71a61a 100644
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--- a/arch/x86/kernel/Makefile
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+++ b/arch/x86/kernel/Makefile
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@@ -104,6 +104,7 @@ obj-$(CONFIG_EFI) += sysfb_efi.o
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obj-$(CONFIG_PERF_EVENTS) += perf_regs.o
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obj-$(CONFIG_TRACING) += tracepoint.o
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obj-$(CONFIG_IOSF_MBI) += iosf_mbi.o
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+obj-$(CONFIG_PMC_ATOM) += pmc_atom.o
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###
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# 64 bit specific files
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diff --git a/arch/x86/kernel/pmc_atom.c b/arch/x86/kernel/pmc_atom.c
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new file mode 100644
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index 0000000..5991030
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--- /dev/null
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+++ b/arch/x86/kernel/pmc_atom.c
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@@ -0,0 +1,297 @@
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+/*
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+ * Intel Atom SOC Power Management Controller Driver
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+ * Copyright (c) 2014, Intel Corporation.
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms and conditions of the GNU General Public License,
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+ * version 2, as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope it will be useful, but WITHOUT
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+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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+ * more details.
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+ *
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+ */
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+
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+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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+
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+#include <linux/module.h>
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+#include <linux/init.h>
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+#include <linux/pci.h>
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+#include <linux/device.h>
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+#include <linux/debugfs.h>
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+#include <linux/seq_file.h>
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+#include <linux/io.h>
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+
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+#include <asm/pmc_atom.h>
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+
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+#define DRIVER_NAME KBUILD_MODNAME
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+
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+struct pmc_dev {
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+ struct pci_dev *pdev;
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+ u32 base_addr;
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+ void __iomem *regmap;
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+#ifdef CONFIG_DEBUG_FS
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+ struct dentry *dbgfs_dir;
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+#endif /* CONFIG_DEBUG_FS */
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+};
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+
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+static u32 acpi_base_addr;
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+
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+struct pmc_dev_map {
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+ const char *name;
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+ u32 bit_mask;
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+};
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+
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+static const struct pmc_dev_map dev_map[] = {
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+ {"0 - LPSS1_F0_DMA", BIT_LPSS1_F0_DMA},
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+ {"1 - LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1},
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+ {"2 - LPSS1_F2_PWM2", BIT_LPSS1_F2_PWM2},
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+ {"3 - LPSS1_F3_HSUART1", BIT_LPSS1_F3_HSUART1},
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+ {"4 - LPSS1_F4_HSUART2", BIT_LPSS1_F4_HSUART2},
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+ {"5 - LPSS1_F5_SPI", BIT_LPSS1_F5_SPI},
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+ {"6 - LPSS1_F6_Reserved", BIT_LPSS1_F6_XXX},
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+ {"7 - LPSS1_F7_Reserved", BIT_LPSS1_F7_XXX},
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+ {"8 - SCC_EMMC", BIT_SCC_EMMC},
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+ {"9 - SCC_SDIO", BIT_SCC_SDIO},
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+ {"10 - SCC_SDCARD", BIT_SCC_SDCARD},
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+ {"11 - SCC_MIPI", BIT_SCC_MIPI},
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+ {"12 - HDA", BIT_HDA},
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+ {"13 - LPE", BIT_LPE},
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+ {"14 - OTG", BIT_OTG},
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+ {"15 - USH", BIT_USH},
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+ {"16 - GBE", BIT_GBE},
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+ {"17 - SATA", BIT_SATA},
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+ {"18 - USB_EHCI", BIT_USB_EHCI},
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+ {"19 - SEC", BIT_SEC},
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+ {"20 - PCIE_PORT0", BIT_PCIE_PORT0},
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+ {"21 - PCIE_PORT1", BIT_PCIE_PORT1},
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+ {"22 - PCIE_PORT2", BIT_PCIE_PORT2},
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+ {"23 - PCIE_PORT3", BIT_PCIE_PORT3},
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+ {"24 - LPSS2_F0_DMA", BIT_LPSS2_F0_DMA},
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+ {"25 - LPSS2_F1_I2C1", BIT_LPSS2_F1_I2C1},
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+ {"26 - LPSS2_F2_I2C2", BIT_LPSS2_F2_I2C2},
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+ {"27 - LPSS2_F3_I2C3", BIT_LPSS2_F3_I2C3},
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+ {"28 - LPSS2_F3_I2C4", BIT_LPSS2_F4_I2C4},
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+ {"29 - LPSS2_F5_I2C5", BIT_LPSS2_F5_I2C5},
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+ {"30 - LPSS2_F6_I2C6", BIT_LPSS2_F6_I2C6},
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+ {"31 - LPSS2_F7_I2C7", BIT_LPSS2_F7_I2C7},
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+ {"32 - SMB", BIT_SMB},
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+ {"33 - USH_SS_PHY", BIT_OTG_SS_PHY},
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+ {"34 - OTG_SS_PHY", BIT_USH_SS_PHY},
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+ {"35 - DFX", BIT_DFX},
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+};
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+
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+static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
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+{
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+ return readl(pmc->regmap + reg_offset);
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+}
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+
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+static void pmc_power_off(void)
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+{
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+ u16 pm1_cnt_port;
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+ u32 pm1_cnt_value;
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+
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+ pr_info("Preparing to enter system sleep state S5\n");
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+
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+ pm1_cnt_port = acpi_base_addr + PM1_CNT;
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+
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+ pm1_cnt_value = inl(pm1_cnt_port);
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+ pm1_cnt_value &= SLEEP_TYPE_MASK;
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+ pm1_cnt_value |= SLEEP_TYPE_S5;
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+ pm1_cnt_value |= SLEEP_ENABLE;
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+
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+ outl(pm1_cnt_value, pm1_cnt_port);
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+}
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+
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+#ifdef CONFIG_DEBUG_FS
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+static int pmc_dev_state_show(struct seq_file *s, void *unused)
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+{
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+ struct pmc_dev *pmc = (struct pmc_dev *)s->private;
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+ u32 func_dis, func_dis_2, func_dis_index;
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+ u32 d3_sts_0, d3_sts_1, d3_sts_index;
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+ int dev_num, dev_index, reg_index;
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+
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+ func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
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+ func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
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+ d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
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+ d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
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+
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+ dev_num = sizeof(dev_map) / sizeof(struct pmc_dev_map);
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+
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+ for (dev_index = 0; dev_index < dev_num; dev_index++) {
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+ reg_index = dev_index / PMC_REG_BIT_WIDTH;
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+ if (reg_index) {
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+ func_dis_index = func_dis_2;
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+ d3_sts_index = d3_sts_1;
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+ } else {
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+ func_dis_index = func_dis;
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+ d3_sts_index = d3_sts_0;
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+ }
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+
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+ seq_printf(s, "Dev: %-32s\tState: %s [%s]\n",
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+ dev_map[dev_index].name,
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+ dev_map[dev_index].bit_mask & func_dis_index ?
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+ "Disabled" : "Enabled ",
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+ dev_map[dev_index].bit_mask & d3_sts_index ?
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+ "D3" : "D0");
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+ }
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+ return 0;
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+}
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+
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+static int pmc_dev_state_open(struct inode *inode, struct file *file)
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+{
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+ return single_open(file, pmc_dev_state_show, inode->i_private);
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+}
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+
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+static const struct file_operations pmc_dev_state_ops = {
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+ .open = pmc_dev_state_open,
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+ .read = seq_read,
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+ .llseek = seq_lseek,
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+ .release = single_release,
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+};
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+
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+static int pmc_sleep_tmr_show(struct seq_file *s, void *unused)
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+{
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+ struct pmc_dev *pmc = (struct pmc_dev *)s->private;
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+ u64 s0ir_tmr, s0i1_tmr, s0i2_tmr, s0i3_tmr, s0_tmr;
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+
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+ s0ir_tmr = pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
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+ s0i1_tmr = pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
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+ s0i2_tmr = pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
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+ s0i3_tmr = pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
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+ s0_tmr = pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
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+
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+ seq_printf(s, "S0IR Residency:\t%lldus\n", s0ir_tmr);
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+ seq_printf(s, "S0I1 Residency:\t%lldus\n", s0i1_tmr);
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+ seq_printf(s, "S0I2 Residency:\t%lldus\n", s0i2_tmr);
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+ seq_printf(s, "S0I3 Residency:\t%lldus\n", s0i3_tmr);
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+ seq_printf(s, "S0 Residency:\t%lldus\n", s0_tmr);
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+ return 0;
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+}
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+
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+static int pmc_sleep_tmr_open(struct inode *inode, struct file *file)
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+{
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+ return single_open(file, pmc_sleep_tmr_show, inode->i_private);
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+}
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+
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+static const struct file_operations pmc_sleep_tmr_ops = {
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+ .open = pmc_sleep_tmr_open,
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+ .read = seq_read,
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+ .llseek = seq_lseek,
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+ .release = single_release,
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+};
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+
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+static void pmc_dbgfs_unregister(struct pmc_dev *pmc)
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+{
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+ if (!pmc->dbgfs_dir)
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+ return;
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+
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+ debugfs_remove_recursive(pmc->dbgfs_dir);
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+ pmc->dbgfs_dir = NULL;
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+}
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+
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+static int pmc_dbgfs_register(struct pmc_dev *pmc)
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+{
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+ struct dentry *dir, *f;
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+
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+ dir = debugfs_create_dir("pmc_atom", NULL);
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+ if (!dir)
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+ return -ENOMEM;
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+
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+ f = debugfs_create_file("dev_state", S_IFREG | S_IRUGO,
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+ dir, pmc, &pmc_dev_state_ops);
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+ if (!f) {
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+ dev_err(&pmc->pdev->dev, "dev_states register failed\n");
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+ goto err;
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+ }
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+ f = debugfs_create_file("sleep_state", S_IFREG | S_IRUGO,
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+ dir, pmc, &pmc_sleep_tmr_ops);
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+ if (!f) {
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+ dev_err(&pmc->pdev->dev, "sleep_state register failed\n");
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+ goto err;
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+ }
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+ pmc->dbgfs_dir = dir;
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+ return 0;
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+err:
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+ pmc_dbgfs_unregister(pmc);
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+ return -ENODEV;
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+}
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+#endif /* CONFIG_DEBUG_FS */
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+
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+static int pmc_probe(struct pci_dev *pdev,
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+ const struct pci_device_id *unused)
|
|
+{
|
|
+ struct pmc_dev *pmc;
|
|
+ int ret;
|
|
+
|
|
+ ret = pci_enable_device(pdev);
|
|
+ if (ret < 0) {
|
|
+ dev_err(&pdev->dev, "error: could not enable device\n");
|
|
+ goto err_enable_device;
|
|
+ }
|
|
+
|
|
+ ret = pci_request_regions(pdev, DRIVER_NAME);
|
|
+ if (ret) {
|
|
+ dev_err(&pdev->dev, "error: could not request PCI region\n");
|
|
+ goto err_request_regions;
|
|
+ }
|
|
+
|
|
+ pmc = devm_kzalloc(&pdev->dev, sizeof(struct pmc_dev), GFP_KERNEL);
|
|
+ if (!pmc) {
|
|
+ ret = -ENOMEM;
|
|
+ goto err_devm_kzalloc;
|
|
+ }
|
|
+
|
|
+ pmc->pdev = pci_dev_get(pdev);
|
|
+
|
|
+ pci_read_config_dword(pdev, PMC_BASE_ADDR_OFFSET, &pmc->base_addr);
|
|
+ pmc->base_addr &= PMC_BASE_ADDR_MASK;
|
|
+
|
|
+ pmc->regmap = devm_ioremap_nocache(&pdev->dev,
|
|
+ pmc->base_addr, PMC_MMIO_REG_LEN);
|
|
+ if (!pmc->regmap) {
|
|
+ dev_err(&pdev->dev, "error: ioremap failed\n");
|
|
+ ret = -ENOMEM;
|
|
+ goto err_devm_ioremap;
|
|
+ }
|
|
+ pci_set_drvdata(pdev, pmc);
|
|
+#ifdef CONFIG_DEBUG_FS
|
|
+ pmc_dbgfs_register(pmc);
|
|
+#endif /* CONFIG_DEBUG_FS */
|
|
+
|
|
+ /* Install power off function */
|
|
+ pci_read_config_dword(pdev, ACPI_BASE_ADDR_OFFSET, &acpi_base_addr);
|
|
+ acpi_base_addr &= ACPI_BASE_ADDR_MASK;
|
|
+ if (acpi_base_addr != 0 && pm_power_off == NULL)
|
|
+ pm_power_off = pmc_power_off;
|
|
+ return 0;
|
|
+err_devm_ioremap:
|
|
+ pci_dev_put(pdev);
|
|
+err_devm_kzalloc:
|
|
+ pci_release_regions(pdev);
|
|
+err_request_regions:
|
|
+ pci_disable_device(pdev);
|
|
+err_enable_device:
|
|
+ dev_err(&pdev->dev, "error: probe failed\n");
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static const struct pci_device_id pmc_pci_ids[] = {
|
|
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_VLV_PMC) },
|
|
+ { 0, },
|
|
+};
|
|
+
|
|
+MODULE_DEVICE_TABLE(pci, pmc_pci_ids);
|
|
+
|
|
+static struct pci_driver pmc_pci_driver = {
|
|
+ .name = DRIVER_NAME,
|
|
+ .probe = pmc_probe,
|
|
+ .id_table = pmc_pci_ids,
|
|
+};
|
|
+
|
|
+module_pci_driver(pmc_pci_driver);
|
|
+
|
|
+MODULE_AUTHOR("Aubrey Li <aubrey.li@linux.intel.com>");
|
|
+MODULE_DESCRIPTION("Intel Atom SOC Power Management Controller Interface");
|
|
+MODULE_LICENSE("GPL v2");
|