108 lines
4.1 KiB
Diff
108 lines
4.1 KiB
Diff
From ad66fd35f0b4ec360c4fdc9ace9d7381a998e36c Mon Sep 17 00:00:00 2001
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From: huangyifeng <huangyifeng@eswincomputing.com>
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Date: Mon, 30 Sep 2024 13:26:53 +0800
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Subject: [PATCH 181/222] fix:CPU run 1.6GHz without voltage boost if allowed
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Changelogs:
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Some chips, during ATE testing, have demonstrated that the CPU can run
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at 1.6GHz with a voltage of 0.8V. When this information is read from the
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OTP, U-Boot will add the parameter cpu_no_boost_1_6ghz to the cmdline.
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During Linux startup, this parameter will be checked. For this type of
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chip, when Linux boosts the CPU to 1.6GHz, it will not increase the
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voltage, thereby reducing power consumption. It is important to note,
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however, that when the CPU runs at 1.8GHz, a voltage increase is still
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required.
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Signed-off-by: huangyifeng <huangyifeng@eswincomputing.com>
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---
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drivers/clk/eswin/clk.c | 41 ++++++++++++++++++++++++++++++++++-------
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1 file changed, 34 insertions(+), 7 deletions(-)
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diff --git a/drivers/clk/eswin/clk.c b/drivers/clk/eswin/clk.c
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index b944a5e6ec44..c035da206e7b 100755
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--- a/drivers/clk/eswin/clk.c
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+++ b/drivers/clk/eswin/clk.c
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@@ -281,6 +281,14 @@ static int eswin_calc_pll(u32 *frac_val, u32 *postdiv1_val,
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return ret;
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}
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+static bool cpu_no_boost_1_6ghz = false;
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+static int __init cpu_no_boost_1_6ghz_setup(char *__unused)
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+{
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+ cpu_no_boost_1_6ghz = true;
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+ return 1;
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+}
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+__setup("cpu_no_boost_1_6ghz", cpu_no_boost_1_6ghz_setup);
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+
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#define to_pll_clk(_hw) container_of(_hw, struct eswin_clk_pll, hw)
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static int clk_pll_set_rate(struct clk_hw *hw,
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unsigned long rate,
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@@ -298,6 +306,7 @@ static int clk_pll_set_rate(struct clk_hw *hw,
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char clk_cpu_mux_name[50] = {0};
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char clk_cpu_lp_pll_name[50] = {0};
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char clk_cpu_pll_name[50] = {0};
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+ enum voltage_level cpu_target_volatge;
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ret = eswin_calc_pll(&frac_val, &postdiv1_val, &fbdiv_val, &refdiv_val, (u64)rate, clk);
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if (ret) {
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@@ -355,15 +364,32 @@ static int clk_pll_set_rate(struct clk_hw *hw,
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switch (rate) {
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case CLK_FREQ_1800M:
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case CLK_FREQ_1700M:
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+ cpu_target_volatge = VOLTAGE_0_9V;
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+ ret = eswin_clk_set_cpu_volatge(clk->cpu_voltage_gpio, cpu_target_volatge);
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+ if (ret) {
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+ pr_warn("failed to change cpu volatge to %d mV, not support rate %ld\n",
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+ cpu_target_volatge, rate);
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+ goto switch_back;
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+ } else {
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+ if (clk->cpu_current_volatge != cpu_target_volatge) {
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+ pr_info("cpu volatge change to %d mV, target rate %ld\n",
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+ cpu_target_volatge, rate);
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+ clk->cpu_current_volatge = cpu_target_volatge;
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+ }
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+ }
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+ break;
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case CLK_FREQ_1600M:
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- ret = eswin_clk_set_cpu_volatge(clk->cpu_voltage_gpio, VOLTAGE_0_9V);
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+ cpu_target_volatge = true == cpu_no_boost_1_6ghz ? VOLTAGE_0_8V : VOLTAGE_0_9V;
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+ ret = eswin_clk_set_cpu_volatge(clk->cpu_voltage_gpio, cpu_target_volatge);
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if (ret) {
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- pr_warn("Failed to change cpu volatge to 0.9V, not support rate %ld\n", rate);
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+ pr_warn("failed to change cpu volatge to %d mV, not support rate %ld\n",
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+ cpu_target_volatge , rate);
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goto switch_back;
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} else {
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- if (clk->cpu_current_volatge != VOLTAGE_0_9V) {
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- pr_info("Cpu volatge change to 0.9V, target rate %ld\n", rate);
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- clk->cpu_current_volatge = VOLTAGE_0_9V;
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+ if (clk->cpu_current_volatge != cpu_target_volatge) {
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+ pr_info("cpu volatge change to %d mV, target rate %ld\n",
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+ cpu_target_volatge, rate);
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+ clk->cpu_current_volatge = cpu_target_volatge;
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}
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}
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break;
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@@ -371,7 +397,8 @@ static int clk_pll_set_rate(struct clk_hw *hw,
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ret = eswin_clk_set_cpu_volatge(clk->cpu_voltage_gpio, VOLTAGE_0_8V);
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if (!ret) {
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if (clk->cpu_current_volatge != VOLTAGE_0_8V) {
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- pr_info("cpu volatge change to 0.8V, target rate %ld\n", rate);
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+ pr_info("cpu volatge change to %d mV, target rate %ld\n",
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+ VOLTAGE_0_8V, rate);
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clk->cpu_current_volatge = VOLTAGE_0_8V;
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}
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}
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@@ -659,7 +686,7 @@ void eswin_clk_register_pll(struct eswin_pll_clock *clks,
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p_clk->hw.init = &init;
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p_clk->cpu_voltage_gpio = cpu_voltage_gpio;
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-
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+ p_clk->cpu_current_volatge = VOLTAGE_0_8V;
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clk = clk_register(dev, &p_clk->hw);
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if (IS_ERR(clk)) {
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devm_kfree(dev, p_clk);
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--
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2.47.0
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