2296e4a647
- Add patch to fix intermittent hangs in nouveau driver - Move mtpspi and related mods to kernel-core for VMWare guests (rhbz 1194612)
136 lines
4.2 KiB
Diff
136 lines
4.2 KiB
Diff
From: Ben Skeggs <bskeggs@redhat.com>
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Date: Tue, 27 Jan 2015 15:09:39 +1000
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Subject: [PATCH] fifo/nv04: remove the loop from the interrupt handler
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Complete bong hit (and not the last...), the hardware will reassert the
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interrupt to PMC if it's necessary.
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Also potentially harmful in the face of interrupts such as the non-stall
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interrupt, which remain active in NV_PFIFO_INTR even when we don't care
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about servicing it.
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It appears (hopefully, fdo#87244), that under certain loads, the methods
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may pass quickly enough to hit the "100 spins and kill PFIFO" thing that
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we had going on. Not ideal ;)
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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---
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drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c | 85 ++++++++++---------------
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1 file changed, 35 insertions(+), 50 deletions(-)
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diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
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index b038b6eb51db..043e4296084c 100644
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--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
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+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
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@@ -502,72 +502,57 @@ nv04_fifo_intr(struct nvkm_subdev *subdev)
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{
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struct nvkm_device *device = nv_device(subdev);
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struct nv04_fifo_priv *priv = (void *)subdev;
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- uint32_t status, reassign;
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- int cnt = 0;
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+ u32 mask = nv_rd32(priv, NV03_PFIFO_INTR_EN_0);
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+ u32 stat = nv_rd32(priv, NV03_PFIFO_INTR_0) & mask;
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+ u32 reassign, chid, get, sem;
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reassign = nv_rd32(priv, NV03_PFIFO_CACHES) & 1;
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- while ((status = nv_rd32(priv, NV03_PFIFO_INTR_0)) && (cnt++ < 100)) {
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- uint32_t chid, get;
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-
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- nv_wr32(priv, NV03_PFIFO_CACHES, 0);
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-
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- chid = nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH1) & priv->base.max;
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- get = nv_rd32(priv, NV03_PFIFO_CACHE1_GET);
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+ nv_wr32(priv, NV03_PFIFO_CACHES, 0);
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- if (status & NV_PFIFO_INTR_CACHE_ERROR) {
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- nv04_fifo_cache_error(device, priv, chid, get);
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- status &= ~NV_PFIFO_INTR_CACHE_ERROR;
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- }
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+ chid = nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH1) & priv->base.max;
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+ get = nv_rd32(priv, NV03_PFIFO_CACHE1_GET);
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- if (status & NV_PFIFO_INTR_DMA_PUSHER) {
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- nv04_fifo_dma_pusher(device, priv, chid);
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- status &= ~NV_PFIFO_INTR_DMA_PUSHER;
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- }
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+ if (stat & NV_PFIFO_INTR_CACHE_ERROR) {
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+ nv04_fifo_cache_error(device, priv, chid, get);
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+ stat &= ~NV_PFIFO_INTR_CACHE_ERROR;
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+ }
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- if (status & NV_PFIFO_INTR_SEMAPHORE) {
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- uint32_t sem;
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+ if (stat & NV_PFIFO_INTR_DMA_PUSHER) {
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+ nv04_fifo_dma_pusher(device, priv, chid);
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+ stat &= ~NV_PFIFO_INTR_DMA_PUSHER;
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+ }
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- status &= ~NV_PFIFO_INTR_SEMAPHORE;
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- nv_wr32(priv, NV03_PFIFO_INTR_0,
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- NV_PFIFO_INTR_SEMAPHORE);
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+ if (stat & NV_PFIFO_INTR_SEMAPHORE) {
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+ stat &= ~NV_PFIFO_INTR_SEMAPHORE;
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+ nv_wr32(priv, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_SEMAPHORE);
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- sem = nv_rd32(priv, NV10_PFIFO_CACHE1_SEMAPHORE);
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- nv_wr32(priv, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1);
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+ sem = nv_rd32(priv, NV10_PFIFO_CACHE1_SEMAPHORE);
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+ nv_wr32(priv, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1);
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- nv_wr32(priv, NV03_PFIFO_CACHE1_GET, get + 4);
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- nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1);
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- }
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+ nv_wr32(priv, NV03_PFIFO_CACHE1_GET, get + 4);
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+ nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1);
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+ }
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- if (device->card_type == NV_50) {
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- if (status & 0x00000010) {
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- status &= ~0x00000010;
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- nv_wr32(priv, 0x002100, 0x00000010);
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- }
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-
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- if (status & 0x40000000) {
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- nv_wr32(priv, 0x002100, 0x40000000);
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- nvkm_fifo_uevent(&priv->base);
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- status &= ~0x40000000;
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- }
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+ if (device->card_type == NV_50) {
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+ if (stat & 0x00000010) {
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+ stat &= ~0x00000010;
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+ nv_wr32(priv, 0x002100, 0x00000010);
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}
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- if (status) {
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- nv_warn(priv, "unknown intr 0x%08x, ch %d\n",
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- status, chid);
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- nv_wr32(priv, NV03_PFIFO_INTR_0, status);
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- status = 0;
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+ if (stat & 0x40000000) {
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+ nv_wr32(priv, 0x002100, 0x40000000);
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+ nvkm_fifo_uevent(&priv->base);
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+ stat &= ~0x40000000;
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}
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-
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- nv_wr32(priv, NV03_PFIFO_CACHES, reassign);
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}
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- if (status) {
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- nv_error(priv, "still angry after %d spins, halt\n", cnt);
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- nv_wr32(priv, 0x002140, 0);
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- nv_wr32(priv, 0x000140, 0);
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+ if (stat) {
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+ nv_warn(priv, "unknown intr 0x%08x\n", stat);
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+ nv_mask(priv, NV03_PFIFO_INTR_EN_0, stat, 0x00000000);
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+ nv_wr32(priv, NV03_PFIFO_INTR_0, stat);
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}
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- nv_wr32(priv, 0x000100, 0x00000100);
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+ nv_wr32(priv, NV03_PFIFO_CACHES, reassign);
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}
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static int
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--
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2.1.0
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