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kernel/0382-WIN2030-16919-fix-d2d-cpu-volatge-opp-table-support.patch
Jason Montleon 1937e4ada0 Update to 6.6.81
2025-03-08 09:54:45 -05:00

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From dfc34034bc16ca76f9825241ca421c8b232a974b Mon Sep 17 00:00:00 2001
From: huangyifeng <huangyifeng@eswincomputing.com>
Date: Fri, 10 Jan 2025 10:55:39 +0800
Subject: [PATCH 382/416] WIN2030-16919:fix:d2d cpu volatge & opp table support
Changelogs:
1.The clocks of Die0 and Die1 have two separate sets of registers,
so the CPU's OPP table needs to be configured as two independent sets.
2.Support for CPU volatge boost operation in a dual-die
configuration.
3. Rename eic770x-ooptable.dtsi to eic770x-opptable.dtsi
Change-Id: I1ddae57423452b7f83c637e4aaa76a4d61088334
Signed-off-by: huangyifeng <huangyifeng@eswincomputing.com>
---
arch/riscv/boot/dts/eswin/Makefile | 3 +-
arch/riscv/boot/dts/eswin/eic7700-evb-a3.dts | 2 +-
.../dts/eswin/eic7700-hifive-premier-p550.dts | 2 +-
.../boot/dts/eswin/eic7700-milkv-megrez.dts | 2 +-
.../dts/eswin/eic7700-pine64-starpro64.dts | 2 +-
.../boot/dts/eswin/eic7700-som260-a1.dtsi | 2 +-
arch/riscv/boot/dts/eswin/eic7700-som314.dtsi | 2 +-
arch/riscv/boot/dts/eswin/eic7702-tb.dts | 53 ++++++++++++++
...0x-ooptable.dtsi => eic770x-opptable.dtsi} | 73 ++++++++++++++++++-
.../dts/eswin/eswin-win2030-arch-d2d.dtsi | 10 +--
.../boot/dts/eswin/eswin-win2030-arch.dtsi | 10 +--
drivers/clk/eswin/clk.c | 9 ++-
12 files changed, 150 insertions(+), 20 deletions(-)
rename arch/riscv/boot/dts/eswin/{eic770x-ooptable.dtsi => eic770x-opptable.dtsi} (72%)
diff --git a/arch/riscv/boot/dts/eswin/Makefile b/arch/riscv/boot/dts/eswin/Makefile
index 69074a4a1451..f4f2418da886 100644
--- a/arch/riscv/boot/dts/eswin/Makefile
+++ b/arch/riscv/boot/dts/eswin/Makefile
@@ -11,6 +11,7 @@ dtb-$(CONFIG_SOC_SIFIVE) += eswin-win2030.dtb \
eic7702-evb-a1.dtb\
eic7700-z530.dtb \
eic7700-d314.dtb \
- eic7702-evb-a1-interleave.dtb
+ eic7702-evb-a1-interleave.dtb \
+ eic7702-tb.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/riscv/boot/dts/eswin/eic7700-evb-a3.dts b/arch/riscv/boot/dts/eswin/eic7700-evb-a3.dts
index bfc99f105556..9631c73e0bd3 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-evb-a3.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-evb-a3.dts
@@ -32,7 +32,7 @@ &d0_clock {
cpu-default-frequency = <CLK_FREQ_1600M>;
};
-&cpu_opp_table {
+&d0_cpu_opp_table {
opp-1500000000 {
opp-hz = /bits/ 64 <CLK_FREQ_1500M>;
opp-microvolt = <900000>;
diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
index badde2fa404c..75e180fbf78f 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
@@ -875,7 +875,7 @@ &d0_clock {
cpu-voltage-gpios = <&portc 30 GPIO_ACTIVE_HIGH>;
};
-&cpu_opp_table {
+&d0_cpu_opp_table {
opp-1500000000 {
opp-hz = /bits/ 64 <CLK_FREQ_1500M>;
opp-microvolt = <900000>;
diff --git a/arch/riscv/boot/dts/eswin/eic7700-milkv-megrez.dts b/arch/riscv/boot/dts/eswin/eic7700-milkv-megrez.dts
index 3a016445160a..e2b84bec70e0 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-milkv-megrez.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-milkv-megrez.dts
@@ -955,7 +955,7 @@ &d0_clock {
force-1_8ghz;
};
-&cpu_opp_table {
+&d0_cpu_opp_table {
opp-1500000000 {
opp-hz = /bits/ 64 <CLK_FREQ_1500M>;
opp-microvolt = <900000>;
diff --git a/arch/riscv/boot/dts/eswin/eic7700-pine64-starpro64.dts b/arch/riscv/boot/dts/eswin/eic7700-pine64-starpro64.dts
index 1b7d32898c4c..70889ccceb7d 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-pine64-starpro64.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-pine64-starpro64.dts
@@ -850,7 +850,7 @@ &dev_llc_d0{
apply_npu_high_freq;
};
-&cpu_opp_table {
+&d0_cpu_opp_table {
opp-1600000000 {
opp-hz = /bits/ 64 <CLK_FREQ_1600M>;
opp-microvolt = <900000>;
diff --git a/arch/riscv/boot/dts/eswin/eic7700-som260-a1.dtsi b/arch/riscv/boot/dts/eswin/eic7700-som260-a1.dtsi
index bf6d610b3cf0..eb5fb2350a9d 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-som260-a1.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700-som260-a1.dtsi
@@ -145,7 +145,7 @@ d0_gmac0
d0_gmac1
****************************************************/
-&cpu_opp_table {
+&d0_cpu_opp_table {
opp-1500000000 {
opp-hz = /bits/ 64 <CLK_FREQ_1500M>;
opp-microvolt = <900000>;
diff --git a/arch/riscv/boot/dts/eswin/eic7700-som314.dtsi b/arch/riscv/boot/dts/eswin/eic7700-som314.dtsi
index ff10802cc2a3..bbee71eff099 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-som314.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700-som314.dtsi
@@ -689,7 +689,7 @@ &d0_clock {
cpu-voltage-gpios = <&portc 30 GPIO_ACTIVE_HIGH>;
};
-&cpu_opp_table {
+&d0_cpu_opp_table {
opp-1500000000 {
opp-hz = /bits/ 64 <CLK_FREQ_1500M>;
opp-microvolt = <900000>;
diff --git a/arch/riscv/boot/dts/eswin/eic7702-tb.dts b/arch/riscv/boot/dts/eswin/eic7702-tb.dts
index 2355bd3f422d..aa3be74f7e38 100644
--- a/arch/riscv/boot/dts/eswin/eic7702-tb.dts
+++ b/arch/riscv/boot/dts/eswin/eic7702-tb.dts
@@ -187,11 +187,64 @@ d1_zero_device: zero-device@3a000000 {
};
};
+&d0_cpu_opp_table {
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1500M>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1600M>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1700M>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1800M>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <70000>;
+ };
+};
+
+&d1_cpu_opp_table {
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1500M>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1600M>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1700M>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1800M>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <70000>;
+ };
+};
+
&d0_clock {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_die0_gpio19_default>;
+ cpu-voltage-gpios = <&porta 19 GPIO_ACTIVE_HIGH>;
+ cpu-default-frequency = <CLK_FREQ_1800M>;
};
+
&d1_clock {
status = "okay";
+ cpu-voltage-gpios = <&porta 19 GPIO_ACTIVE_HIGH>;
+ cpu-default-frequency = <CLK_FREQ_1800M>;
};
&d0_reset {
diff --git a/arch/riscv/boot/dts/eswin/eic770x-ooptable.dtsi b/arch/riscv/boot/dts/eswin/eic770x-opptable.dtsi
similarity index 72%
rename from arch/riscv/boot/dts/eswin/eic770x-ooptable.dtsi
rename to arch/riscv/boot/dts/eswin/eic770x-opptable.dtsi
index 471984153c44..2f4deaf21d95 100644
--- a/arch/riscv/boot/dts/eswin/eic770x-ooptable.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic770x-opptable.dtsi
@@ -20,7 +20,78 @@
#include <dt-bindings/clock/win2030-clock.h>
/ {
- cpu_opp_table: opp-table@cpu {
+ d0_cpu_opp_table: opp-table-d0@cpu {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-24000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_24M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-100000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_100M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-200000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_200M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_400M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_500M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_600M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-700000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_700M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-800000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_800M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-900000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_900M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1000M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1200M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1300000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1300M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1400M>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <70000>;
+ };
+ };
+
+ d1_cpu_opp_table: opp-table-d1@cpu {
compatible = "operating-points-v2";
opp-shared;
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-arch-d2d.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-arch-d2d.dtsi
index 48f72db0adfa..2e3228e16ccd 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-arch-d2d.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-arch-d2d.dtsi
@@ -20,7 +20,7 @@
#define CHIPLET_AND_DIE (0x2)
#include "eswin-win2030-arch.dtsi"
-
+#include "eic770x-opptable.dtsi"
&L64 {
cpu-map {
@@ -105,7 +105,7 @@ cpu_4: cpu@4 {
tlb-split;
numa-node-id = <1>;
clocks = <&d1_clock WIN2030_CLK_CPU_EXT_SRC_CORE_CLK_0>;
- operating-points-v2 = <&cpu_opp_table>;
+ operating-points-v2 = <&d1_cpu_opp_table>;
cpu-idle-states = <&CPU_RET>;
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -153,7 +153,7 @@ cpu_5: cpu@5 {
tlb-split;
numa-node-id = <1>;
clocks = <&d1_clock WIN2030_CLK_CPU_EXT_SRC_CORE_CLK_1>;
- operating-points-v2 = <&cpu_opp_table>;
+ operating-points-v2 = <&d1_cpu_opp_table>;
cpu-idle-states = <&CPU_RET>;
cpu5_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -200,7 +200,7 @@ cpu_6: cpu@6 {
tlb-split;
numa-node-id = <1>;
clocks = <&d1_clock WIN2030_CLK_CPU_EXT_SRC_CORE_CLK_2>;
- operating-points-v2 = <&cpu_opp_table>;
+ operating-points-v2 = <&d1_cpu_opp_table>;
cpu-idle-states = <&CPU_RET>;
cpu6_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -247,7 +247,7 @@ cpu_7: cpu@7 {
tlb-split;
numa-node-id = <1>;
clocks = <&d1_clock WIN2030_CLK_CPU_EXT_SRC_CORE_CLK_3>;
- operating-points-v2 = <&cpu_opp_table>;
+ operating-points-v2 = <&d1_cpu_opp_table>;
cpu-idle-states = <&CPU_RET>;
cpu7_intc: interrupt-controller {
#interrupt-cells = <1>;
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-arch.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-arch.dtsi
index 9fa246a5898f..80c512ffa74a 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-arch.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-arch.dtsi
@@ -19,7 +19,7 @@
*/
#include <dt-bindings/clock/win2030-clock.h>
-#include "eic770x-ooptable.dtsi"
+#include "eic770x-opptable.dtsi"
#define UART0_INT 100
#define UART1_INT 101
@@ -85,7 +85,7 @@ cpu_0: cpu@0 {
tlb-split;
numa-node-id = <0>;
clocks = <&d0_clock WIN2030_CLK_CPU_EXT_SRC_CORE_CLK_0>;
- operating-points-v2 = <&cpu_opp_table>;
+ operating-points-v2 = <&d0_cpu_opp_table>;
#cooling-cells = <2>;
dynamic-power-coefficient = <324>;
cpu-idle-states = <&CPU_RET>;
@@ -131,7 +131,7 @@ cpu_1: cpu@1 {
tlb-split;
numa-node-id = <0>;
clocks = <&d0_clock WIN2030_CLK_CPU_EXT_SRC_CORE_CLK_1>;
- operating-points-v2 = <&cpu_opp_table>;
+ operating-points-v2 = <&d0_cpu_opp_table>;
#cooling-cells = <2>;
dynamic-power-coefficient = <324>;
cpu-idle-states = <&CPU_RET>;
@@ -177,7 +177,7 @@ cpu_2: cpu@2 {
tlb-split;
numa-node-id = <0>;
clocks = <&d0_clock WIN2030_CLK_CPU_EXT_SRC_CORE_CLK_2>;
- operating-points-v2 = <&cpu_opp_table>;
+ operating-points-v2 = <&d0_cpu_opp_table>;
#cooling-cells = <2>;
dynamic-power-coefficient = <324>;
cpu-idle-states = <&CPU_RET>;
@@ -223,7 +223,7 @@ cpu_3: cpu@3 {
tlb-split;
numa-node-id = <0>;
clocks = <&d0_clock WIN2030_CLK_CPU_EXT_SRC_CORE_CLK_3>;
- operating-points-v2 = <&cpu_opp_table>;
+ operating-points-v2 = <&d0_cpu_opp_table>;
#cooling-cells = <2>;
dynamic-power-coefficient = <324>;
cpu-idle-states = <&CPU_RET>;
diff --git a/drivers/clk/eswin/clk.c b/drivers/clk/eswin/clk.c
index e243673c771d..425056d394b6 100755
--- a/drivers/clk/eswin/clk.c
+++ b/drivers/clk/eswin/clk.c
@@ -626,7 +626,7 @@ void eswin_clk_register_pll(struct eswin_pll_clock *clks,
struct clk *clk = NULL;
struct clk_init_data init;
int i;
- struct gpio_desc *cpu_voltage_gpio;
+ static struct gpio_desc *cpu_voltage_gpio = NULL;
int force_1_8ghz = 0;
p_clk = devm_kzalloc(dev, sizeof(*p_clk) * nums, GFP_KERNEL);
@@ -634,7 +634,12 @@ void eswin_clk_register_pll(struct eswin_pll_clock *clks,
if (!p_clk)
return;
- cpu_voltage_gpio = devm_gpiod_get(dev, "cpu-voltage", GPIOD_OUT_HIGH);
+ /*
+ In the D2D system, the boost operation is performed using the GPIO on Die0.
+ However, the same GPIO pin cannot be acquired twice, so special handling is implemented:
+ once the GPIO is acquired,the other driver simply uses it directly
+ */
+ cpu_voltage_gpio = IS_ERR_OR_NULL(cpu_voltage_gpio) ? devm_gpiod_get(dev, "cpu-voltage", GPIOD_OUT_HIGH) : cpu_voltage_gpio;
if (IS_ERR_OR_NULL(cpu_voltage_gpio)) {
dev_warn(dev, "failed to get cpu volatge gpio\n");
cpu_voltage_gpio = NULL;
--
2.48.1
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