kernel/0341-WIN2030-16810-fix-npu-devfeq-bug-fix.patch
2025-03-08 09:54:45 -05:00

118 lines
3.9 KiB
Diff

From 2f910a784f403a1a368158849313e607f9967ccc Mon Sep 17 00:00:00 2001
From: donghuawei <donghuawei@eswincomputing.com>
Date: Mon, 16 Dec 2024 11:25:50 +0800
Subject: [PATCH 341/416] WIN2030-16810:fix: npu devfeq bug fix
Changelogs:
1. when rise freq, need firstly rise volt, and then rise freq.
2. when lower freq, need firstly lower freq, and then lower
volt.
3. set npu lower freq volt 0.9v
Change-Id: I6ef35d2515b88573ded40a01a1ea107122fd1b97
Signed-off-by: donghuawei <donghuawei@eswincomputing.com>
---
.../boot/dts/eswin/eic770x-ooptable.dtsi | 2 +-
drivers/soc/eswin/ai_driver/npu/npu_main.c | 66 ++++++++++++-------
2 files changed, 44 insertions(+), 24 deletions(-)
diff --git a/arch/riscv/boot/dts/eswin/eic770x-ooptable.dtsi b/arch/riscv/boot/dts/eswin/eic770x-ooptable.dtsi
index e6adc2e30072..471984153c44 100644
--- a/arch/riscv/boot/dts/eswin/eic770x-ooptable.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic770x-ooptable.dtsi
@@ -106,7 +106,7 @@ npu_opp_table: opp-table@npu {
compatible = "operating-points-v2";
opp@1040000000 {
opp-hz = /bits/ 64 <1040000000>;
- opp-microvolt = <800000>;
+ opp-microvolt = <900000>;
};
opp@1500000000 {
opp-hz = /bits/ 64 <1500000000>;
diff --git a/drivers/soc/eswin/ai_driver/npu/npu_main.c b/drivers/soc/eswin/ai_driver/npu/npu_main.c
index 026a89f803b8..825c432cf2f2 100644
--- a/drivers/soc/eswin/ai_driver/npu/npu_main.c
+++ b/drivers/soc/eswin/ai_driver/npu/npu_main.c
@@ -353,35 +353,55 @@ static int npu_devfreq_target(struct device *dev, unsigned long *freq, u32 flags
return 0;
}
mutex_lock(&nvdla_dev->devfreq_lock);
- ret = regulator_set_voltage(nvdla_dev->npu_regulator, target_volt, target_volt);
- if (ret) {
- dev_err(dev, "Cannot set voltage %lu uV\n", target_volt);
- goto out;
- }
- if (target_volt == NPU_1P5G_VOLTAGE) {
+ if (target_rate > nvdla_dev->rate) { // rise freq
+ ret = regulator_set_voltage(nvdla_dev->npu_regulator, target_volt, target_volt);
+ if (ret) {
+ dev_err(dev, "Cannot set voltage %lu uV\n", target_volt);
+ goto out;
+ }
+
ret = clk_set_parent(nvdla_dev->mux_u_npu_core_3mux1_gfree, nvdla_dev->fixed_rate_clk_spll1_fout1);
- } else if (target_volt == NPU_DEFAULT_VOLTAGE) {
+ if (ret) {
+ dev_err(dev, "Cannot set target voltage %lu parent, (%d)\n", target_rate, ret);
+ goto err_parent;
+ }
+ mdelay(10);
+ rate = clk_round_rate(nvdla_dev->core_clk, target_rate);
+ ret = clk_set_rate(nvdla_dev->core_clk, rate);
+ if (ret != 0)
+ {
+ dev_err(dev, "failed to set core_clk: %d\n", ret);
+ goto err_rate;
+
+ }
+
+ } else { // lower freq
ret = clk_set_parent(nvdla_dev->mux_u_npu_core_3mux1_gfree, nvdla_dev->fixed_rate_clk_spll2_fout2);
- } else {
- dev_err(dev, "Request freq %lu is not supported.\n", *freq);
- ret = -EINVAL;
- goto err_parent;
- }
- if (ret) {
- dev_err(dev, "Cannot set target voltage %lu parent, (%d)\n", target_rate, ret);
- goto err_parent;
- }
+ if (ret) {
+ dev_err(dev, "Cannot set target voltage %lu parent, (%d)\n", target_rate, ret);
+ goto out;
+ }
- rate = clk_round_rate(nvdla_dev->core_clk, target_rate);
- ret = clk_set_rate(nvdla_dev->core_clk, rate);
- if (ret != 0)
- {
- dev_err(dev, "failed to set core_clk: %d\n", ret);
- goto err_rate;
+ rate = clk_round_rate(nvdla_dev->core_clk, target_rate);
+ ret = clk_set_rate(nvdla_dev->core_clk, rate);
+ if (ret != 0)
+ {
+ dev_err(dev, "failed to set core_clk: %d\n", ret);
+ goto err_rate;
- }
+ }
+
+ ret = regulator_set_voltage(nvdla_dev->npu_regulator, target_volt, target_volt);
+ if (ret) {
+ dev_err(dev, "Cannot set voltage %lu uV\n", target_volt);
+ goto err_rate;
+ }
+ mdelay(10);
+
+ }
+
nvdla_dev->rate = clk_get_rate(nvdla_dev->core_clk);
if (nvdla_dev->rate != target_rate) {
dev_err(dev, "Got wrong frequency, Request %lu, Current %lu.\n", target_rate, nvdla_dev->rate);
--
2.48.1