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kernel/0332-WIN2030-16740-feat-support-z530-board.patch
Jason Montleon 1937e4ada0 Update to 6.6.81
2025-03-08 09:54:45 -05:00

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From fd99d25a9848ede53a93a6dd951374aec777db07 Mon Sep 17 00:00:00 2001
From: ningyu <ningyu@eswincomputing.com>
Date: Thu, 5 Dec 2024 20:05:27 +0800
Subject: [PATCH 332/416] WIN2030-16740:feat:support z530 board
Changelogs:
1. Provide som260 dts
2. Provide z530 carrier board dts
Change-Id: I095b5aa7e9326d38567b472c8a1b071909f13a9c
Signed-off-by: ningyu <ningyu@eswincomputing.com>
---
arch/riscv/boot/dts/eswin/Makefile | 3 +-
.../boot/dts/eswin/eic7700-som260-a1.dtsi | 726 ++++++++++++++++++
arch/riscv/boot/dts/eswin/eic7700-z530.dts | 184 +++++
.../boot/dts/eswin/eswin-win2030-arch.dtsi | 9 +-
.../dts/eswin/eswin-win2030-die0-soc.dtsi | 4 +-
5 files changed, 915 insertions(+), 11 deletions(-)
create mode 100644 arch/riscv/boot/dts/eswin/eic7700-som260-a1.dtsi
create mode 100644 arch/riscv/boot/dts/eswin/eic7700-z530.dts
diff --git a/arch/riscv/boot/dts/eswin/Makefile b/arch/riscv/boot/dts/eswin/Makefile
index 80efde30fa4f..cd6b6f5c3dbb 100644
--- a/arch/riscv/boot/dts/eswin/Makefile
+++ b/arch/riscv/boot/dts/eswin/Makefile
@@ -8,6 +8,7 @@ dtb-$(CONFIG_SOC_SIFIVE) += eswin-win2030.dtb \
eic7700-pine64-starpro64.dtb \
eic7702-evb-a1-d0.dtb \
eic7702-evb-a1-d1.dtb \
- eic7702-evb-a1.dtb
+ eic7702-evb-a1.dtb\
+ eic7700-z530.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/riscv/boot/dts/eswin/eic7700-som260-a1.dtsi b/arch/riscv/boot/dts/eswin/eic7700-som260-a1.dtsi
new file mode 100644
index 000000000000..6ae44bf9b159
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eic7700-som260-a1.dtsi
@@ -0,0 +1,726 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for Eswin EIC7700 SoC.
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+
+#define RTCCLK_FREQ 1000000
+#define LSPCLK_FREQ 200000000
+
+/* If wanna enable ECC capability of DDR, should reserve highest zone of 1/8 all space for it */
+#define MEMORY_SIZE_H 0x4
+#define MEMORY_SIZE_L 0x0
+#define CMA_SIZE 0x20000000
+
+#include "eswin-win2030-die0-soc.dtsi"
+#include "eic7700-pinctrl.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "ESWIN 7700S260";
+ compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
+ "sifive,fu740", "eswin,eic7700";
+
+ aliases {
+ serial0 = &d0_uart0;
+ ethernet0 = &d0_gmac0;
+ ethernet1 = &d0_gmac1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ opensbi_domain_config: domain-config {
+ compatible = "opensbi,domain,config";
+ system-suspend-test;
+ };
+ };
+
+ cpus {
+ timebase-frequency = <RTCCLK_FREQ>;
+ };
+
+ memory@59000000 {
+ device_type = "memory";
+ reg = <0x0 0x59000000 0x0 0x400000>;
+ numa-node-id = <0>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 MEMORY_SIZE_H MEMORY_SIZE_L>;
+ numa-node-id = <0>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 CMA_SIZE>;
+ alignment = <0x0 0x1000>;
+ alloc-ranges = <0x0 0x80000000 MEMORY_SIZE_H MEMORY_SIZE_L>;
+ linux,cma-default;
+ };
+
+ npu0_reserved: sprammemory@59000000 {
+ no-map;
+ reg = <0x0 0x59000000 0x0 0x400000>;
+ };
+
+ g2d_4GB_boundary_reserved_4k {
+ no-map;
+ reg = <0x0 0xfffff000 0x0 0x1000>;
+ };
+
+ g2d_8GB_boundary_reserved_4k {
+ no-map;
+ reg = <0x1 0xfffff000 0x0 0x1000>;
+ };
+
+ g2d_12GB_boundary_reserved_4k {
+ no-map;
+ reg = <0x2 0xfffff000 0x0 0x1000>;
+ };
+
+ mmz_nid_0_part_0 {
+ compatible = "eswin-reserve-memory";
+ reg = <0x3 0x0 0x1 0x80000000>;
+ no-map;
+ };
+ };
+};
+
+/****************************************************
+ Carrier board device capability, need be adapted by user according to the carrier board implemented.
+ All of below modules are configured to okay by default, and need be reconfigured by user in dts of carrier board.
+ pcie
+ d0_sata
+ d0_usbdrd3_0
+ d0_usbdrd3_1
+ dw_hdmi
+ mipi csi(2 lanes) x4
+ mipi dsi(4 lanes)
+ sdio0
+ sdio1
+ d0_i2c0
+ d0_i2c1
+ d0_i2c2
+ aon_i2c0
+ d0_uart0
+ d0_uart1
+ d0_uart2
+ d0_uart4
+ ssi0
+ ssi1
+ pwm1
+ pwm2
+ gpio
+ d0_gmac0
+ d0_gmac1
+****************************************************/
+
+&d0_cpu_opp_table {
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1500M>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1600M>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1700M>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <70000>;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <CLK_FREQ_1800M>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <70000>;
+ };
+};
+
+&d0_clock {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio94_default>;
+ cpu-voltage-gpios = <&portc 30 GPIO_ACTIVE_HIGH>;
+};
+
+&d0_reset {
+ status = "okay";
+};
+
+&d0_pmu {
+ status = "okay";
+};
+
+&ddr0 {
+ status = "okay";
+};
+
+&ddr1 {
+ status = "okay";
+};
+
+&smmu0 {
+ status = "okay";
+};
+
+&smmu_pmu0 {
+ status = "disabled";
+};
+
+&dev_foo_a {
+ status = "okay";
+};
+
+&d0_cfg_noc {
+ status = "okay";
+};
+
+&d0_llc_noc {
+ status = "okay";
+ stat,0 = "TracePort:ddr0_p0_req";
+ stat,1 = "TracePort:ddr1_p0_req";
+ //latency,0 = "TracePort:llcnoc_trans_probe";
+ //pending,0 = "TracePort:llcnoc_trans_probe";
+};
+
+&d0_sys_noc {
+ status = "okay";
+
+ //eswin,DSPT-qos-owner;
+ //eswin,NPU-qos-owner;
+ //eswin,SPISLV_TBU3-qos-owner;
+
+#if 0
+ stat,0 = "TracePort:ddr0_p1_req",
+ "InitFlow:mcput_snoc_mp/I/0";
+
+ stat,1 = "TracePort:ddr0_p2_req",
+ "InitFlow:dspt_snoc/I/0",
+ "AddrBase:0x81000000", "AddrSize:0x30",
+ "Opcode:RdWrLockUrg", "Status:ReqRsp", "Length:0x8000", "Urgency:0x0";
+
+ stat,2 = "TracePort:ddr1_p1_req",
+ "Status:Req", "AddrSize:0x28";
+
+ stat,3 = "TracePort:ddr1_p2_req";
+#else
+ stat,0 = "TracePort:ddr0_p1_req";
+
+ stat,1 = "TracePort:ddr0_p2_req";
+
+ stat,2 = "TracePort:ddr1_p1_req";
+
+ stat,3 = "TracePort:ddr1_p2_req";
+#endif
+
+ latency,0 = "TracePort:sysnoc_trans_probe_0", "AddrSize:0x0";
+ latency,1 = "TracePort:sysnoc_trans_probe_1","Mode:latency","AddrBase:0x82000000","AddrSize:0x28","Opcode:RdWr";
+ //latency,2 = "TracePort:sysnoc_trans_probe_2";
+
+ //pending,0 = "TracePort:sysnoc_trans_probe_0";
+ //pending,1 = "TracePort:sysnoc_trans_probe_1","Mode:latency","AddrBase:0x82000000","AddrSize:0x0","Opcode:RdWr";
+ pending,0 = "TracePort:sysnoc_trans_probe_2", "AddrSize:0x3";
+};
+
+&d0_media_noc {
+ status = "okay";
+
+ //eswin,GPU-qos-owner;
+ //eswin,TBU2-qos-owner;
+ //eswin,VC-qos-owner;
+
+ stat,0 = "TracePort:ddr0_p3_req";
+ stat,1 = "TracePort:ddr1_p3_req";
+ //latency,0 = "TracePort:mnoc_trans_probe";
+ //pending,0 = "TracePort:mnoc_trans_probe";
+};
+
+&d0_realtime_noc {
+ status = "okay";
+
+ //eswin,TBU0-qos-owner;
+ //eswin,VO-qos-owner;
+
+ stat,0 = "TracePort:ddr0_p4_req";
+ stat,1 = "TracePort:ddr1_p4_req";
+ //latency,0 = "TracePort:rnoc_trans_probe";
+ //pending,0 = "TracePort:rnoc_trans_probe";
+};
+
+&d0_noc_wdt {
+ status = "okay";
+};
+
+&d0_ipc_scpu {
+ status = "okay";
+};
+
+&d0_lpcpu {
+ status = "okay";
+};
+
+&pcie {
+ status = "okay";
+};
+
+&d0_npu{
+ status = "okay";
+};
+
+&d0_dsp_subsys {
+ status = "okay";
+};
+
+&d0_dsp0 {
+ status = "okay";
+};
+
+&d0_dsp1 {
+ status = "okay";
+};
+
+&d0_dsp2 {
+ status = "okay";
+};
+
+&d0_dsp3 {
+ status = "okay";
+};
+
+&gpu0 {
+ status = "okay";
+};
+
+&gc820 {
+ status = "okay";
+};
+
+&vdec0 {
+ status = "okay";
+};
+
+&venc0 {
+ status = "okay";
+};
+
+&video_output {
+ status = "okay";
+};
+
+&dc {
+ status = "okay";
+};
+
+&dc_test {
+ status = "disabled";
+};
+
+&virtual_display {
+ status = "okay";
+};
+
+&dsi_output {
+ status = "okay";
+};
+
+&dsi_controller {
+ status = "okay";
+};
+
+&dsi_panel {
+ /* backlight0-gpios, rst-gpios */
+ status = "okay";
+};
+
+&dw_hdmi {
+ status = "okay";
+ ports {
+ port@2 {
+ reg = <2>;
+ hdmi_in_i2s: endpoint@1 {
+ system-clock-frequency = <12288000>;
+ remote-endpoint = <&d0_i2s0_endpoint>;
+ };
+ };
+ };
+};
+
+&dw_hdmi_hdcp2 {
+ status = "okay";
+};
+
+&d0_i2s0 {
+ status = "okay";
+ d0_i2s0_port: port {
+ d0_i2s0_endpoint: endpoint {
+ remote-endpoint = <&hdmi_in_i2s>;
+ dai-format = "i2s";
+ };
+ };
+};
+
+&d0_graphcard0 {
+ status = "okay";
+ label = "HDMI Audio";
+ dais = <&d0_i2s0_port>;
+};
+
+&isp_0 {
+ status = "okay";
+};
+
+&isp_1 {
+ status = "okay";
+};
+
+&dewarp {
+ status = "okay";
+};
+
+&mipi_dphy_rx {
+ status = "okay";
+};
+
+&csi_dma0 {
+ status = "okay";
+};
+
+&csi_dma1 {
+ status = "disabled";
+};
+
+&csi2_0 {
+ status = "okay";
+};
+
+&csi2_1 {
+ status = "disabled";
+};
+
+&sdhci_emmc {
+ /* emmc */
+ status = "okay";
+ delay_code = <0x17>;
+ drive-impedance-ohm = <50>;
+ enable-cmd-pullup;
+ enable-data-pullup;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_emmc_led_control_default>;
+ no-sdio;
+ no-sd;
+};
+
+&sdio0 {
+ status = "okay";
+};
+
+&sdio1 {
+ status = "okay";
+};
+
+&d0_gmac0 {
+ pinctrl-names = "default";
+ eswin,rgmiisel = <&pinctrl 0x290 0x3>;
+ eswin,led-cfgs = <0x6100 0xa40 0x420>;
+
+ status = "okay";
+};
+
+&d0_gmac1 {
+ pinctrl-names = "default";
+ eswin,rgmiisel = <&pinctrl 0x294 0x3>;
+ eswin,led-cfgs = <0x6100 0xa40 0x420>;
+
+ status = "okay";
+};
+
+&d0_sata {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sata_act_led_default>;
+};
+
+&d0_usbdrd3_0 {
+ status = "okay";
+};
+
+&d0_usbdrd_dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+};
+
+&d0_usbdrd3_1 {
+ status = "okay";
+};
+
+&d0_usbdrd_dwc3_1 {
+ status = "okay";
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+};
+
+&d0_dmac0 {
+ status = "okay";
+};
+
+&d0_aon_dmac {
+ status = "okay";
+};
+
+&d0_uart0 {
+ /* debug */
+ status = "okay";
+};
+
+&d0_uart1 {
+ status = "okay";
+};
+
+&d0_uart2 {
+ status = "okay";
+};
+
+&d0_uart3 {
+ /* no provide */
+ status = "disabled";
+};
+
+&d0_uart4 {
+ status = "okay";
+};
+
+&ssi0 {
+ status = "okay";
+};
+
+&ssi1 {
+ status = "disabled";
+};
+
+&bootspi {
+ /* spi flash */
+ status = "okay";
+ num-cs = <1>;
+ cs-gpios = <&portd 0 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&portd 4 GPIO_ACTIVE_LOW>;
+ spi-flash@0 {
+ compatible = "winbond,w25q128jw",
+ "jedec,spi-nor";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <4800000>;
+ rx-sample-delay-ns = <10>;
+ };
+};
+
+&d0_mbox0 {
+ status = "okay";
+};
+
+&d0_mbox1 {
+ status = "okay";
+};
+
+&d0_mbox2 {
+ status = "okay";
+};
+
+&d0_mbox3 {
+ status = "okay";
+};
+
+&d0_mbox4 {
+ status = "okay";
+};
+
+&d0_mbox5 {
+ status = "okay";
+};
+
+&d0_mbox6 {
+ status = "okay";
+};
+
+&d0_mbox7 {
+ status = "okay";
+};
+
+&fan_control {
+ status = "okay";
+ eswin,pwm_inverted;
+};
+
+&d0_i2c0 {
+ status = "okay";
+};
+
+&d0_i2c1 {
+ status = "okay";
+};
+
+&d0_i2c2 {
+ status = "okay";
+};
+
+&d0_i2c3 {
+ /* no provide */
+ status = "disabled";
+};
+
+&d0_i2c4 {
+ /* no provide */
+ status = "disabled";
+};
+
+&d0_i2c5 {
+ /* tmp102 */
+ status = "okay";
+ tmp102@48 {
+ compatible = "ti,tmp102";
+ reg = <0x48>;
+ label = "d0_board_tmp";
+ #thermal-sensor-cells = <1>;
+ };
+};
+
+&d0_i2c6 {
+ /* no provide */
+ status = "disabled";
+};
+
+&d0_i2c7 {
+ /* no provide */
+ status = "disabled";
+};
+
+&d0_i2c8 {
+ /* no provide */
+ status = "disabled";
+};
+
+&d0_i2c9 {
+ /* no provide */
+ status = "disabled";
+};
+
+&d0_aon_i2c0 {
+ status = "okay";
+};
+
+&d0_aon_i2c1 {
+ /* pmic es5340 */
+ status = "okay";
+ es5340@f {
+ compatible = "einno,es5340";
+ reg = <0xf>;
+ eswin,regulator_default-microvolt=<1000000>;
+ eswin,regulator_label = "supply vdd1", "npu vdd1", "npu current1", "npu temperature1";
+ label = "npu_vdd";
+ regulators{
+ npu_vcc1:npu_svcc{
+ regulator-name="NPU_SVCC";
+ regulator-min-microvolt=<700000>;
+ regulator-max-microvolt=<1100000>;
+ regulator-min-microamp=<20000000>;
+ regulator-max-microamp=<40000000>;
+ regulator-ov-protection-microvolt=<1100000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&pwm0 {
+ /* fan */
+ status = "okay";
+};
+
+&pvt0 {
+ status = "okay";
+};
+
+&pvt1 {
+ status = "okay";
+};
+
+&wdt0 {
+ status = "disabled";
+};
+
+&wdt1 {
+ status = "disabled";
+};
+
+&wdt2 {
+ status = "disabled";
+};
+
+&wdt3 {
+ status = "disabled";
+};
+
+&die0_rtc {
+ status = "okay";
+};
+
+&timer0 {
+ status = "okay";
+};
+
+&timer1 {
+ status = "okay";
+};
+
+&timer2 {
+ status = "okay";
+};
+
+&timer3 {
+ status = "okay";
+};
+
+&pinctrl {
+ status = "okay";
+};
+
+&gpio0 {
+ status = "okay";
+};
+&dev_llc_d0{
+ /* apply_npu_1G_freq; */
+ npu-supply=<&npu_vcc1>;
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/eswin/eic7700-z530.dts b/arch/riscv/boot/dts/eswin/eic7700-z530.dts
new file mode 100644
index 000000000000..0512aadbfb80
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eic7700-z530.dts
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for Eswin EIC7700 SoC.
+ *
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#include "eic7700-som260-a1.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "ESWIN EIC7700 Z530";
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ ap_backup {
+ label = "ap-backup";
+ linux,code = <KEY_OK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio26_default>;
+ gpios = <&porta 26 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio10_default>;
+ pci-prsnt = <&porta 10 GPIO_ACTIVE_LOW>;
+};
+
+&sdio0 {
+ /* sd card */
+ delay_code = <0x55>;
+ drive-impedance-ohm = <33>;
+ enable-cmd-pullup;
+ enable-data-pullup;
+ no-sdio;
+ no-mmc;
+};
+
+&sdio1 {
+ /* wifi module */
+ delay_code = <0x29>;
+ drive-impedance-ohm = <33>;
+ enable-cmd-pullup;
+ enable-data-pullup;
+ keep-power-in-suspend;
+ non-removable;
+ no-sd;
+ no-mmc;
+ aw3155:wifi_aw3155@0 {
+ compatible = "aml_w1_sdio";
+ reg = <0x0>;
+ interrupt-parent = <&porta>;
+ interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&pinctrl_gpio15_default>;
+ pinctrl-1 = <&pinctrl_gpio79_default>;
+ irq-gpios = <&porta 15 GPIO_ACTIVE_HIGH>;
+ rst-gpios = <&portc 15 GPIO_ACTIVE_HIGH>;
+
+ };
+};
+
+&ssi0 {
+ /* lora */
+};
+
+&ssi1 {
+ /* unused */
+ status = "disabled";
+};
+
+&dsi_panel {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio7_default &pinctrl_gpio92_default>;
+ backlight0-gpios = <&porta 7 GPIO_ACTIVE_HIGH>;
+ rst-gpios = <&portc 28 GPIO_ACTIVE_HIGH>;
+};
+
+&d0_graphcard1 {
+ status = "okay";
+ label = "Analog Audio-0";
+ dais = <&d0_i2s1_port>;
+};
+
+&d0_graphcard2 {
+ status = "disabled";
+};
+
+&d0_i2s1 {
+ status = "okay";
+ d0_i2s1_port: port {
+ d0_i2s1_endpoint: endpoint {
+ remote-endpoint = <&d0_codec0_endpoint>;
+ dai-format = "i2s";
+ };
+ };
+};
+
+&d0_i2s2 {
+ status = "disabled";
+};
+
+&d0_i2c0 {
+ /* codec es8388 */
+ d0_es8388_0: es8388-0@10 {
+ compatible = "eswin,es8388";
+ reg = <0x10>;
+ #sound-dai-cells = <0>;
+ port {
+ d0_codec0_endpoint: endpoint {
+ system-clock-frequency = <12288000>;
+ remote-endpoint = <&d0_i2s1_endpoint>;
+ };
+ };
+ };
+};
+
+&d0_i2c1 {
+ /* rtc rs4c411 & mipi dsi */
+
+};
+
+&d0_i2c2 {
+ /* touch screen*/
+ gt911:touchscreen@14 {
+ compatible = "goodix,gt911";
+ reg = <0x14>;
+ interrupt-parent = <&porta>;
+ interrupts = <0 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio0_default &pinctrl_gpio92_default>;
+ irq-gpios = <&porta 0 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&portc 28 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&d0_aon_i2c0 {
+ /* rk628f x2 */
+
+};
+
+/* GPIO Function Description
+ gpio0 : touch int(I)
+ gpio5 : 5g wake on host(I)
+ gpio6 : 5g disable2(O)
+ gpio7 : mipi dsi ctrl(O)
+ gpio8 : 5g disable1(O)
+ gpio9 : rk628 plugin detect(I)
+ gpio10 : pcie prsnt(I)
+ gpio12 : bt wake host(I)
+ gpio15 : wlan wake host(I)
+ gpio26 : ap backup(I)
+ gpio39 : lora busy(I)
+ gpio41 : host wake bt(I)
+ gpio70 : rk628 int(I)
+ gpio71 : rk628 reset(O)
+ gpio73 : rk628 power enable(O)
+ gpio74 : 5g pwren(O)
+ gpio76 : eth rset(O)
+ gpio77 : lora nreset(O)
+ gpio79 : m2 power on(O)
+ gpio80 : lora ctrl2(O)
+ gpio81 : lora ctrl1(O)
+ gpio92 : touch rstn(O)
+ gpio93 : 5g reset(O)
+*/
\ No newline at end of file
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-arch.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-arch.dtsi
index 0f0e36842fd0..71b68bc3064e 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-arch.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-arch.dtsi
@@ -234,12 +234,7 @@ cpu3_intc: interrupt-controller {
};
};
};
- L50: memory@80000000 {
- compatible = "sifive,axi4-mem-port", "sifive,axi4-port", "sifive,mem-port";
- device_type = "memory";
- reg = <0x0 0x80000000 0x7f 0x80000000>;
- sifive,port-width-bytes = <32>;
- };
+
SOC: soc {
#address-cells = <2>;
#size-cells = <2>;
@@ -329,7 +324,7 @@ D0CACHE: cache-controller@2010000 {
compatible = "sifive,ccache1", "cache", "sifive,fu740-c000-ccache";
interrupt-parent = <&plic0>;
interrupts = <1>, <3>, <4>, <2>;
- next-level-cache = <&L9 &L10 &L11 &L50>;
+ next-level-cache = <&L9 &L10 &L11>;
reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x400000>;
reg-names = "control", "sideband";
sifive,a-mshr-count = <60>;
diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
index 7fb7d3b28df2..e6d2005d854b 100644
--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
@@ -1296,7 +1296,7 @@ fan_control: fan_control@50b50000 {
pwm-minimum-period = <1000>;
pwms = <&pwm0 0 100000>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_die0_fan_tach_default>;
+ pinctrl-0 = <&pinctrl_die0_fan_tach_default &pinctrl_die0_pwm0_default>;
status = "disabled";
label = "fan_control";
};
@@ -1537,8 +1537,6 @@ pwm0: pwm@0x50818000 {
clock-frequency = <200000000>;
resets = <&d0_reset TIMER_RST_CTRL SW_TIMER_RST_N>;
reset-names = "rst";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_die0_pwm0_default>;
status = "disabled";
};
--
2.48.1
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