99 lines
3.8 KiB
Diff
99 lines
3.8 KiB
Diff
From 32d1b4c65de3a1b60ce7edc4629ca6c4397f94d1 Mon Sep 17 00:00:00 2001
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From: liusheng <liusheng@eswincomputing.com>
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Date: Wed, 11 Sep 2024 17:21:40 +0800
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Subject: [PATCH 263/416] WIN2030-16286:feat:fix 2d cannot alloc die0 cma addr
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issue
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Changelogs:
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1.add the numa-node-id for 2d
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Change-Id: Id2fbfd0143d7f028a140511a4ad432df1eb39511
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Signed-off-by: liusheng <liusheng@eswincomputing.com>
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---
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.../dts/eswin/eswin-win2030-die0-soc.dtsi | 1 +
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.../dts/eswin/eswin-win2030-die1-soc.dtsi | 55 ++++++++++---------
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2 files changed, 29 insertions(+), 27 deletions(-)
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diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
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index d87b845a0966..5750ea1646ca 100644
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--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
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+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die0-soc.dtsi
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@@ -751,6 +751,7 @@ gc820: g2d@50140000 {
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contiguous-size = <0xa00000>;
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recovery = <0>;
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dma-noncoherent;
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+ numa-node-id = <0>;
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};
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gpu0: gpu@51400000 {
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diff --git a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
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index 2f36205bc50e..e23aace10f03 100644
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--- a/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
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+++ b/arch/riscv/boot/dts/eswin/eswin-win2030-die1-soc.dtsi
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@@ -1912,34 +1912,35 @@ d1_wdt3: watchdog@0x7080c000 {
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status = "disabled";
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};
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- d1_gc820: g2d@70140000 {
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- compatible = "eswin,galcore_d1";
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- clocks = <&d1_clock WIN2030_CLK_VC_ACLK>,
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- <&d1_clock WIN2030_CLK_VC_CFG_CLK>,
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- <&d1_clock WIN2030_CLK_G2D_CFG_CLK>,
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- <&d1_clock WIN2030_CLK_CLK_G2D_ST2>,
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- <&d1_clock WIN2030_CLK_G2D_CLK>,
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- <&d1_clock WIN2030_CLK_G2D_ACLK>,
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- <&d1_clock WIN2030_CLK_VC_MON_PCLK>;
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- clock-names = "vc_aclk", "vc_cfg", "g2d_cfg", "g2d_st2", "g2d_clk", "g2d_aclk","mon_pclk";
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- resets = <&d1_reset VC_RST_CTRL SW_VC_AXI_RSTN>,
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- <&d1_reset VC_RST_CTRL SW_VC_CFG_RSTN>,
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- <&d1_reset VC_RST_CTRL SW_VC_MONCFG_RSTN>,
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- <&d1_reset G2D_RST_CTRL SW_G2D_CORE_RSTN>,
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- <&d1_reset G2D_RST_CTRL SW_G2D_CFG_RSTN>,
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- <&d1_reset G2D_RST_CTRL SW_G2D_AXI_RSTN>;
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- reset-names = "axi", "cfg", "moncfg", "g2d_core", "g2d_cfg", "g2d_axi";
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- reg = <0 0x70140000 0 0x40000>, <0 0x70180000 0 0x40000>;
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- reg-names = "core_2d", "core_2d1";
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- fe-apb-offset = <0x800>;
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- interrupt-parent = <&plic1>;
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- interrupts = <49>, <50>;
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- interrupt-names = "core_2d", "core_2d1";
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- enable-mmu = <1>;
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- contiguous-size = <0xa00000>;
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- recovery = <0>;
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+ d1_gc820: g2d@70140000 {
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+ compatible = "eswin,galcore_d1";
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+ clocks = <&d1_clock WIN2030_CLK_VC_ACLK>,
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+ <&d1_clock WIN2030_CLK_VC_CFG_CLK>,
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+ <&d1_clock WIN2030_CLK_G2D_CFG_CLK>,
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+ <&d1_clock WIN2030_CLK_CLK_G2D_ST2>,
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+ <&d1_clock WIN2030_CLK_G2D_CLK>,
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+ <&d1_clock WIN2030_CLK_G2D_ACLK>,
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+ <&d1_clock WIN2030_CLK_VC_MON_PCLK>;
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+ clock-names = "vc_aclk", "vc_cfg", "g2d_cfg", "g2d_st2", "g2d_clk", "g2d_aclk","mon_pclk";
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+ resets = <&d1_reset VC_RST_CTRL SW_VC_AXI_RSTN>,
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+ <&d1_reset VC_RST_CTRL SW_VC_CFG_RSTN>,
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+ <&d1_reset VC_RST_CTRL SW_VC_MONCFG_RSTN>,
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+ <&d1_reset G2D_RST_CTRL SW_G2D_CORE_RSTN>,
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+ <&d1_reset G2D_RST_CTRL SW_G2D_CFG_RSTN>,
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+ <&d1_reset G2D_RST_CTRL SW_G2D_AXI_RSTN>;
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+ reset-names = "axi", "cfg", "moncfg", "g2d_core", "g2d_cfg", "g2d_axi";
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+ reg = <0 0x70140000 0 0x40000>, <0 0x70180000 0 0x40000>;
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+ reg-names = "core_2d", "core_2d1";
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+ fe-apb-offset = <0x800>;
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+ interrupt-parent = <&plic1>;
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+ interrupts = <49>, <50>;
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+ interrupt-names = "core_2d", "core_2d1";
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+ enable-mmu = <1>;
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+ contiguous-size = <0xa00000>;
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+ recovery = <0>;
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dma-noncoherent;
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- };
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+ numa-node-id = <1>;
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+ };
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d1_sdhci_emmc: mmc@70450000 {
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compatible = "eswin,emmc-sdhci-5.1";
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--
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2.48.1
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